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net: dwc: Fix cache alignment issues

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Fix remaining cache alignment issues in the DWC Ethernet driver.
Please note that the cache handling in the driver is making the
code hideous and thus the next patch cleans that up. In order to
make this change reviewable though, the cleanup is split from it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Acked-by: Pavel Machek <pavel@denx.de>
This commit is contained in:
Marek Vasut 2014-09-15 00:50:37 +02:00
parent 58ec63d6bc
commit 4f68678b19
1 changed files with 4 additions and 2 deletions
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6
drivers/net/designware.c
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@ -303,7 +303,8 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length)
/* Flush data to be sent */
flush_dcache_range((unsigned long)desc_p->dmamac_addr,
(unsigned long)desc_p->dmamac_addr + length);
(unsigned long)desc_p->dmamac_addr +
roundup(length, ARCH_DMA_MINALIGN));
#if defined(CONFIG_DW_ALTDESCRIPTOR)
desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
@ -372,7 +373,8 @@ static int dw_eth_recv(struct eth_device *dev)
/* Flush only status field - others weren't changed */
flush_dcache_range((unsigned long)&desc_p->txrx_status,
(unsigned long)&desc_p->txrx_status +
sizeof(desc_p->txrx_status));
roundup(sizeof(desc_p->txrx_status),
ARCH_DMA_MINALIGN));
/* Test the wrap-around condition. */
if (++desc_num >= CONFIG_RX_DESCR_NUM)