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net: zynq_gem: Correct SGMII enable bit setting

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Correct the SGMII enable bit position to 27 instead
of 31.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This commit is contained in:
Siva Durga Prasad Paladugu 2016-05-16 15:31:38 +05:30 committed by Michal Simek
parent 27183d7c22
commit 4eaf8f5424
1 changed files with 1 additions and 1 deletions
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2
drivers/net/zynq_gem.c
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@ -57,7 +57,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */
#define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */
#define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */
#define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x80000000 /* SGMII Enable */
#define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */
#define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */
#ifdef CONFIG_ARM64
#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x00100000 /* Div pclk by 64, max 160MHz */