diff --git a/include/linux/intel-smc.h b/include/linux/intel-smc.h
index cacb410691..68d62be417 100644
--- a/include/linux/intel-smc.h
+++ b/include/linux/intel-smc.h
@@ -518,56 +518,4 @@ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE)
 #define INTEL_SIP_SMC_MBOX_SEND_CMD \
 	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_MBOX_SEND_CMD)
 
-/*
- * Request INTEL_SIP_SMC_HPS_SET_PHYINTF
- *
- * Select EMACx PHY interface
- *
- * Call register usage:
- * a0 INTEL_SIP_SMC_HPS_SET_PHYINTF
- * a1 EMAC number:
- *      0 - EMAC0
- *      1 - EMAC1
- *      2 - EMAC2
- * a2 Type of PHY interface:
- *      0 - GMII_MII
- *      1 - RGMII
- *      2 - RMII
- *      3 - RESET
- * a3-7 not used
- *
- * Return status
- * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR
- */
-#define INTEL_SIP_SMC_FUNCID_HPS_SET_PHYINTF	61
-#define INTEL_SIP_SMC_HPS_SET_PHYINTF \
-	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_HPS_SET_PHYINTF)
-
-/*
- * Request INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK
- *
- * Select which phase shift of the clocks (drvsel & smplsel) for SDMMC
- *
- * Call register usage:
- * a0 INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK
- * a1 Select which phase shift of the clock for cclk_in_drv (drvsel):
- *      0 - 0 degree
- *      1 - 45 degrees
- *      2 - 90 degrees
- *      3 - 135 degrees
- *      4 - 180 degrees
- *      5 - 225 degrees
- *      6 - 270 degrees
- *      7 - 315 degrees
- * a2 Select which phase shift of the clock for cclk_in_sample (smplsel):
- *      (Same as above)
- * a3-7 not used
- *
- * Return status
- * a0 INTEL_SIP_SMC_STATUS_OK
- */
-#define INTEL_SIP_SMC_FUNCID_HPS_SET_SDMMC_CCLK	62
-#define INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK \
-	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_HPS_SET_SDMMC_CCLK)
-
 #endif