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https://github.com/brain-hackers/u-boot-brain
synced 2024-09-25 06:00:25 +09:00
pico-imx7d: Convert DM MMC
This patch enable convert DM MMC for imx7d-pico board and variant. Before the DM conversion only usdhc3 was enabled and therefore it appeared as MMC 0 to u-boot. After enabling MMC DM though usdhc3 defaults to MMC 2, which left unattended would drive changes to existing pico-pi bootscripts and environment variables that rely on mmc 0. Setup the alias of mmc0 and usdhc3 so that existing pico-imx7d boot code will work unmodified. When converting to DM_MMC it is necessary that SPL initializes eMMC by itself, so move the original eMMC initialization from U-Boot proper to SPL. Signed-off-by: Joris Offouga <offougajoris@gmail.com> Signed-off-by: Fabio Estevam <festevam@gmail.com>
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@ -8,6 +8,10 @@
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/ {
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/ {
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aliases {
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mmc0 = &usdhc3;
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};
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/* Will be filled by the bootloader */
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/* Will be filled by the bootloader */
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memory@80000000 {
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memory@80000000 {
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device_type = "memory";
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device_type = "memory";
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@ -13,10 +13,8 @@
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#include <asm/mach-imx/mxc_i2c.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <asm/io.h>
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#include <asm/io.h>
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#include <common.h>
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#include <common.h>
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#include <fsl_esdhc.h>
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#include <i2c.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <miiphy.h>
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#include <mmc.h>
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#include <netdev.h>
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#include <netdev.h>
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#include <usb.h>
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#include <usb.h>
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#include <power/pmic.h>
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#include <power/pmic.h>
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@ -28,9 +26,6 @@ DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
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#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
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PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
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PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
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#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
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PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
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#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
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#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
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@ -126,20 +121,6 @@ static iomux_v3_cfg_t const uart5_pads[] = {
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MX7D_PAD_I2C4_SDA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX7D_PAD_I2C4_SDA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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};
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static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
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MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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};
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#ifdef CONFIG_FEC_MXC
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#ifdef CONFIG_FEC_MXC
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static iomux_v3_cfg_t const fec1_pads[] = {
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static iomux_v3_cfg_t const fec1_pads[] = {
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MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
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MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
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@ -224,25 +205,6 @@ static void setup_iomux_uart(void)
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imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
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imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
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}
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}
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static struct fsl_esdhc_cfg usdhc_cfg[1] = {
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{USDHC3_BASE_ADDR},
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};
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int board_mmc_getcd(struct mmc *mmc)
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{
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/* Assume uSDHC3 emmc is always present */
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return 1;
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}
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int board_mmc_init(bd_t *bis)
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{
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imx_iomux_v3_setup_multiple_pads(
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usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads));
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
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}
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int board_early_init_f(void)
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int board_early_init_f(void)
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{
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{
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setup_iomux_uart();
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setup_iomux_uart();
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@ -5,11 +5,15 @@
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* Author: Richard Hu <richard.hu@technexion.com>
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* Author: Richard Hu <richard.hu@technexion.com>
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*/
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/mx7-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch-mx7/mx7-ddr.h>
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#include <asm/arch-mx7/mx7-ddr.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/gpio.h>
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#include <asm/gpio.h>
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#include <fsl_esdhc.h>
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#include <spl.h>
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#include <spl.h>
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#if defined(CONFIG_SPL_BUILD)
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#if defined(CONFIG_SPL_BUILD)
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@ -119,4 +123,38 @@ void board_init_f(ulong dummy)
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void reset_cpu(ulong addr)
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void reset_cpu(ulong addr)
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{
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{
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}
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}
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#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
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PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
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static iomux_v3_cfg_t const usdhc3_pads[] = {
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MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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};
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static struct fsl_esdhc_cfg usdhc_cfg[1] = {
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{USDHC3_BASE_ADDR},
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};
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int board_mmc_getcd(struct mmc *mmc)
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{
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/* Assume uSDHC3 emmc is always present */
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return 1;
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}
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int board_mmc_init(bd_t *bis)
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{
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imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
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}
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#endif
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#endif
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@ -34,6 +34,7 @@ CONFIG_CMD_SPL=y
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CONFIG_CMD_SPL_WRITE_SIZE=0x20000
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CONFIG_CMD_SPL_WRITE_SIZE=0x20000
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CONFIG_CMD_DFU=y
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CONFIG_CMD_DFU=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_GPIO=y
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CONFIG_DM_MMC=y
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CONFIG_CMD_GPT=y
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CONFIG_CMD_GPT=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_MMC=y
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@ -30,6 +30,7 @@ CONFIG_CMD_BOOTMENU=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_IMX7=y
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CONFIG_PINCTRL_IMX7=y
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CONFIG_DM_GPIO=y
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CONFIG_DM_GPIO=y
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CONFIG_DM_MMC=y
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CONFIG_CMD_SPL=y
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CONFIG_CMD_SPL=y
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CONFIG_CMD_SPL_WRITE_SIZE=0x20000
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CONFIG_CMD_SPL_WRITE_SIZE=0x20000
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CONFIG_CMD_DFU=y
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CONFIG_CMD_DFU=y
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@ -34,6 +34,7 @@ CONFIG_CMD_SPL=y
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CONFIG_CMD_SPL_WRITE_SIZE=0x20000
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CONFIG_CMD_SPL_WRITE_SIZE=0x20000
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CONFIG_CMD_DFU=y
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CONFIG_CMD_DFU=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_GPIO=y
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CONFIG_DM_MMC=y
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CONFIG_CMD_GPT=y
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CONFIG_CMD_GPT=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_MMC=y
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