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Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv

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- add DM based reset driver for SiFive SoC's.
This commit is contained in:
Tom Rini 2020-08-04 11:07:38 -04:00
commit 4d23857abd
8 changed files with 239 additions and 25 deletions
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12
arch/riscv/dts/fu540-c000-u-boot.dtsi
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@ -3,6 +3,8 @@
* (C) Copyright 2019 SiFive, Inc
*/
#include <dt-bindings/reset/sifive-fu540-prci.h>
/ {
cpus {
assigned-clocks = <&prci PRCI_CLK_COREPLL>;
@ -59,6 +61,16 @@
reg = <0x0 0x2000000 0x0 0xc0000>;
u-boot,dm-spl;
};
prci: clock-controller@10000000 {
#reset-cells = <1>;
resets = <&prci PRCI_RST_DDR_CTRL_N>,
<&prci PRCI_RST_DDR_AXI_N>,
<&prci PRCI_RST_DDR_AHB_N>,
<&prci PRCI_RST_DDR_PHY_N>,
<&prci PRCI_RST_GEMGXL_N>;
reset-names = "ddr_ctrl", "ddr_axi", "ddr_ahb",
"ddr_phy", "gemgxl_reset";
};
dmc: dmc@100b0000 {
compatible = "sifive,fu540-c000-ddr";
reg = <0x0 0x100b0000 0x0 0x0800

13
arch/riscv/include/asm/arch-fu540/reset.h Normal file
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@ -0,0 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2020 SiFive, Inc.
*
* Author: Sagar Kadam <sagar.kadam@sifive.com>
*/
#ifndef __RESET_SIFIVE_H
#define __RESET_SIFIVE_H
int sifive_reset_bind(struct udevice *dev, ulong count);
#endif

2
configs/sifive_fu540_defconfig
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@ -25,3 +25,5 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_CLK=y
CONFIG_DM_MTD=y
CONFIG_SPL_DM_RESET=y
CONFIG_DM_RESET=y

90
drivers/clk/sifive/fu540-prci.c
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@ -30,17 +30,22 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/reset.h>
#include <clk-uclass.h>
#include <clk.h>
#include <div64.h>
#include <dm.h>
#include <errno.h>
#include <reset-uclass.h>
#include <dm/device.h>
#include <dm/uclass.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/math64.h>
#include <linux/clk/analogbits-wrpll-cln28hpc.h>
#include <dt-bindings/clock/sifive-fu540-prci.h>
#include <dt-bindings/reset/sifive-fu540-prci.h>
/*
* EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects:
@ -131,21 +136,18 @@
/* DEVICESRESETREG */
#define PRCI_DEVICESRESETREG_OFFSET 0x28
#define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT 0
#define PRCI_DEVICERESETCNT 5
#define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_MASK \
(0x1 << PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT)
#define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_SHIFT 1
(0x1 << PRCI_RST_DDR_CTRL_N)
#define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_MASK \
(0x1 << PRCI_DEVICESRESETREG_DDR_AXI_RST_N_SHIFT)
#define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_SHIFT 2
(0x1 << PRCI_RST_DDR_AXI_N)
#define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_MASK \
(0x1 << PRCI_DEVICESRESETREG_DDR_AHB_RST_N_SHIFT)
#define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT 3
(0x1 << PRCI_RST_DDR_AHB_N)
#define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_MASK \
(0x1 << PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT)
#define PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT 5
(0x1 << PRCI_RST_DDR_PHY_N)
#define PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK \
(0x1 << PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT)
(0x1 << PRCI_RST_GEMGXL_N)
/* CLKMUXSTATUSREG */
#define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c
@ -528,6 +530,41 @@ static const struct __prci_clock_ops sifive_fu540_prci_tlclksel_clk_ops = {
.recalc_rate = sifive_fu540_prci_tlclksel_recalc_rate,
};
static int __prci_consumer_reset(const char *rst_name, bool trigger)
{
struct udevice *dev;
struct reset_ctl rst_sig;
int ret;
ret = uclass_get_device_by_driver(UCLASS_RESET,
DM_GET_DRIVER(sifive_reset),
&dev);
if (ret) {
dev_err(dev, "Reset driver not found: %d\n", ret);
return ret;
}
ret = reset_get_by_name(dev, rst_name, &rst_sig);
if (ret) {
dev_err(dev, "failed to get %s reset\n", rst_name);
return ret;
}
if (reset_valid(&rst_sig)) {
if (trigger)
ret = reset_deassert(&rst_sig);
else
ret = reset_assert(&rst_sig);
if (ret) {
dev_err(dev, "failed to trigger reset id = %ld\n",
rst_sig.id);
return ret;
}
}
return ret;
}
/**
* __prci_ddr_release_reset() - Release DDR reset
* @pd: struct __prci_data * for the PRCI containing the DDRCLK mux reg
@ -535,19 +572,20 @@ static const struct __prci_clock_ops sifive_fu540_prci_tlclksel_clk_ops = {
*/
static void __prci_ddr_release_reset(struct __prci_data *pd)
{
u32 v;
v = __prci_readl(pd, PRCI_DEVICESRESETREG_OFFSET);
v |= PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_MASK;
__prci_writel(v, PRCI_DEVICESRESETREG_OFFSET, pd);
/* Release DDR ctrl reset */
__prci_consumer_reset("ddr_ctrl", true);
/* HACK to get the '1 full controller clock cycle'. */
asm volatile ("fence");
v = __prci_readl(pd, PRCI_DEVICESRESETREG_OFFSET);
v |= (PRCI_DEVICESRESETREG_DDR_AXI_RST_N_MASK |
PRCI_DEVICESRESETREG_DDR_AHB_RST_N_MASK |
PRCI_DEVICESRESETREG_DDR_PHY_RST_N_MASK);
__prci_writel(v, PRCI_DEVICESRESETREG_OFFSET, pd);
/* Release DDR AXI reset */
__prci_consumer_reset("ddr_axi", true);
/* Release DDR AHB reset */
__prci_consumer_reset("ddr_ahb", true);
/* Release DDR PHY reset */
__prci_consumer_reset("ddr_phy", true);
/* HACK to get the '1 full controller clock cycle'. */
asm volatile ("fence");
@ -567,12 +605,8 @@ static void __prci_ddr_release_reset(struct __prci_data *pd)
*/
static void __prci_ethernet_release_reset(struct __prci_data *pd)
{
u32 v;
/* Release GEMGXL reset */
v = __prci_readl(pd, PRCI_DEVICESRESETREG_OFFSET);
v |= PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK;
__prci_writel(v, PRCI_DEVICESRESETREG_OFFSET, pd);
__prci_consumer_reset("gemgxl_reset", true);
/* Procmon => core clock */
__prci_writel(PRCI_PROCMONCFG_CORE_CLOCK_MASK, PRCI_PROCMONCFG_OFFSET,
@ -757,6 +791,11 @@ static struct clk_ops sifive_fu540_prci_ops = {
.disable = sifive_fu540_prci_disable,
};
static int sifive_fu540_clk_bind(struct udevice *dev)
{
return sifive_reset_bind(dev, PRCI_DEVICERESETCNT);
}
static const struct udevice_id sifive_fu540_prci_ids[] = {
{ .compatible = "sifive,fu540-c000-prci" },
{ }
@ -769,4 +808,5 @@ U_BOOT_DRIVER(sifive_fu540_prci) = {
.probe = sifive_fu540_prci_probe,
.ops = &sifive_fu540_prci_ops,
.priv_auto_alloc_size = sizeof(struct __prci_data),
.bind = sifive_fu540_clk_bind,
};

9
drivers/reset/Kconfig
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@ -148,6 +148,15 @@ config RESET_IMX7
help
Support for reset controller on i.MX7/8 SoCs.
config RESET_SIFIVE
bool "Reset Driver for SiFive SoC's"
depends on DM_RESET && CLK_SIFIVE_FU540_PRCI && TARGET_SIFIVE_FU540
default y
help
PRCI module within SiFive SoC's provides mechanism to reset
different hw blocks like DDR, gemgxl. With this driver we leverage
U-Boot's reset framework to reset these hardware blocks.
config RESET_SYSCON
bool "Enable generic syscon reset driver support"
depends on DM_RESET

1
drivers/reset/Makefile
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@ -23,5 +23,6 @@ obj-$(CONFIG_RESET_MTMIPS) += reset-mtmips.o
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o
obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
obj-$(CONFIG_RESET_SIFIVE) += reset-sifive.o
obj-$(CONFIG_RESET_SYSCON) += reset-syscon.o
obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o

118
drivers/reset/reset-sifive.c Normal file
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@ -0,0 +1,118 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2020 Sifive, Inc.
* Author: Sagar Kadam <sagar.kadam@sifive.com>
*/
#include <common.h>
#include <dm.h>
#include <reset-uclass.h>
#include <asm/io.h>
#include <dm/device_compat.h>
#include <dm/lists.h>
#include <linux/bitops.h>
#define PRCI_RESETREG_OFFSET 0x28
struct sifive_reset_priv {
void *base;
/* number of reset signals */
int nr_reset;
};
static int sifive_rst_trigger(struct reset_ctl *rst, bool level)
{
struct sifive_reset_priv *priv = dev_get_priv(rst->dev);
int id = rst->id;
int regval = readl(priv->base + PRCI_RESETREG_OFFSET);
/* Derive bitposition from rst id */
if (level)
/* Reset deassert */
regval |= BIT(id);
else
/* Reset assert */
regval &= ~BIT(id);
writel(regval, priv->base + PRCI_RESETREG_OFFSET);
return 0;
}
static int sifive_reset_assert(struct reset_ctl *rst)
{
return sifive_rst_trigger(rst, false);
}
static int sifive_reset_deassert(struct reset_ctl *rst)
{
return sifive_rst_trigger(rst, true);
}
static int sifive_reset_request(struct reset_ctl *rst)
{
struct sifive_reset_priv *priv = dev_get_priv(rst->dev);
debug("%s(rst=%p) (dev=%p, id=%lu) (nr_reset=%d)\n", __func__,
rst, rst->dev, rst->id, priv->nr_reset);
if (rst->id > priv->nr_reset)
return -EINVAL;
return 0;
}
static int sifive_reset_free(struct reset_ctl *rst)
{
struct sifive_reset_priv *priv = dev_get_priv(rst->dev);
debug("%s(rst=%p) (dev=%p, id=%lu) (nr_reset=%d)\n", __func__,
rst, rst->dev, rst->id, priv->nr_reset);
return 0;
}
static int sifive_reset_probe(struct udevice *dev)
{
struct sifive_reset_priv *priv = dev_get_priv(dev);
priv->base = dev_remap_addr(dev);
if (!priv->base)
return -ENOMEM;
return 0;
}
int sifive_reset_bind(struct udevice *dev, ulong count)
{
struct udevice *rst_dev;
struct sifive_reset_priv *priv;
int ret;
ret = device_bind_driver_to_node(dev, "sifive-reset", "reset",
dev_ofnode(dev), &rst_dev);
if (ret) {
dev_err(dev, "failed to bind sifive_reset driver (ret=%d)\n", ret);
return ret;
}
priv = malloc(sizeof(struct sifive_reset_priv));
priv->nr_reset = count;
rst_dev->priv = priv;
return 0;
}
const struct reset_ops sifive_reset_ops = {
.request = sifive_reset_request,
.rfree = sifive_reset_free,
.rst_assert = sifive_reset_assert,
.rst_deassert = sifive_reset_deassert,
};
U_BOOT_DRIVER(sifive_reset) = {
.name = "sifive-reset",
.id = UCLASS_RESET,
.ops = &sifive_reset_ops,
.probe = sifive_reset_probe,
.priv_auto_alloc_size = sizeof(struct sifive_reset_priv),
};

19
include/dt-bindings/reset/sifive-fu540-prci.h Normal file
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@ -0,0 +1,19 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2020 Sifive, Inc.
* Author: Sagar Kadam <sagar.kadam@sifive.com>
*/
#ifndef __DT_BINDINGS_RESET_SIFIVE_FU540_PRCI_H
#define __DT_BINDINGS_RESET_SIFIVE_FU540_PRCI_H
/* Reset indexes for use by device tree data and the PRCI driver */
#define PRCI_RST_DDR_CTRL_N 0
#define PRCI_RST_DDR_AXI_N 1
#define PRCI_RST_DDR_AHB_N 2
#define PRCI_RST_DDR_PHY_N 3
/* bit 4 is reserved bit */
#define PRCI_RST_RSVD_N 4
#define PRCI_RST_GEMGXL_N 5
#endif