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https://github.com/brain-hackers/u-boot-brain
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orion5x: allow overriding default mappings windows
Turn all ORION5X_DEF{ADR,SZ}_xxx macros into ORION5X_{ADR,SZ}_xxx
and allow defining them from board code to override defaults. This
is particularly useful for defining board-specific FLASH address
and size in board header file rather than having to tweak orion5x
code.
Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
This commit is contained in:
Albert Aribaud
Wolfgang Denk
parent
fe8d63c8c7
commit
4cfa0ab2c9
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@ -87,56 +87,56 @@ int orion5x_config_adr_windows(void)
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(struct orion5x_win_registers *)ORION5X_CPU_WIN_BASE;
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/* Window 0: PCIE MEM address space */
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writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCIE_MEM,
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writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_MEM,
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ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM,
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ORION5X_WIN_ENABLE), &winregs[0].ctrl);
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writel(ORION5X_DEFADR_PCIE_MEM, &winregs[0].base);
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writel(ORION5X_DEFADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo);
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writel(ORION5X_DEFADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi);
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writel(ORION5X_ADR_PCIE_MEM, &winregs[0].base);
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writel(ORION5X_ADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo);
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writel(ORION5X_ADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi);
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/* Window 1: PCIE IO address space */
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writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCIE_IO,
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writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_IO,
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ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO,
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ORION5X_WIN_ENABLE), &winregs[1].ctrl);
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writel(ORION5X_DEFADR_PCIE_IO, &winregs[1].base);
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writel(ORION5X_DEFADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo);
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writel(ORION5X_DEFADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi);
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writel(ORION5X_ADR_PCIE_IO, &winregs[1].base);
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writel(ORION5X_ADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo);
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writel(ORION5X_ADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi);
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/* Window 2: PCI MEM address space */
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writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCI_MEM,
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writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_MEM,
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ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_MEM,
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ORION5X_WIN_ENABLE), &winregs[2].ctrl);
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writel(ORION5X_DEFADR_PCI_MEM, &winregs[2].base);
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writel(ORION5X_ADR_PCI_MEM, &winregs[2].base);
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/* Window 3: PCI IO address space */
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writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCI_IO,
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writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_IO,
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ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_IO,
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ORION5X_WIN_ENABLE), &winregs[3].ctrl);
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writel(ORION5X_DEFADR_PCI_IO, &winregs[3].base);
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writel(ORION5X_ADR_PCI_IO, &winregs[3].base);
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/* Window 4: DEV_CS0 address space */
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writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS0,
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writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS0,
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ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS0,
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ORION5X_WIN_ENABLE), &winregs[4].ctrl);
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writel(ORION5X_DEFADR_DEV_CS0, &winregs[4].base);
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writel(ORION5X_ADR_DEV_CS0, &winregs[4].base);
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/* Window 5: DEV_CS1 address space */
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writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS1,
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writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS1,
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ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS1,
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ORION5X_WIN_ENABLE), &winregs[5].ctrl);
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writel(ORION5X_DEFADR_DEV_CS1, &winregs[5].base);
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writel(ORION5X_ADR_DEV_CS1, &winregs[5].base);
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/* Window 6: DEV_CS2 address space */
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writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS2,
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writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS2,
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ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2,
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ORION5X_WIN_ENABLE), &winregs[6].ctrl);
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writel(ORION5X_DEFADR_DEV_CS2, &winregs[6].base);
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writel(ORION5X_ADR_DEV_CS2, &winregs[6].base);
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/* Window 7: BOOT Memory address space */
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writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_BOOTROM,
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writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM,
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ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
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ORION5X_WIN_ENABLE), &winregs[7].ctrl);
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writel(ORION5X_DEFADR_BOOTROM, &winregs[7].base);
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writel(ORION5X_ADR_BOOTROM, &winregs[7].base);
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return 0;
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}
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@ -75,35 +75,91 @@ enum orion5x_cpu_attrib {
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};
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/*
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* Default Device Address MAP BAR values
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* Device Address MAP BAR values
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/*
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* All addresses and sizes not defined by board code
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* will be given default values here.
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*/
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#define ORION5X_DEFADR_PCIE_MEM 0x90000000
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#define ORION5X_DEFADR_PCIE_MEM_REMAP_LO 0x90000000
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#define ORION5X_DEFADR_PCIE_MEM_REMAP_HI 0
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#define ORION5X_DEFSZ_PCIE_MEM (128*1024*1024)
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#define ORION5X_DEFADR_PCIE_IO 0xf0000000
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#define ORION5X_DEFADR_PCIE_IO_REMAP_LO 0x90000000
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#define ORION5X_DEFADR_PCIE_IO_REMAP_HI 0
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#define ORION5X_DEFSZ_PCIE_IO (64*1024)
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#if !defined (ORION5X_ADR_PCIE_MEM)
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#define ORION5X_ADR_PCIE_MEM 0x90000000
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#endif
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#define ORION5X_DEFADR_PCI_MEM 0x98000000
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#define ORION5X_DEFSZ_PCI_MEM (128*1024*1024)
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#if !defined (ORION5X_ADR_PCIE_MEM_REMAP_LO)
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#define ORION5X_ADR_PCIE_MEM_REMAP_LO 0x90000000
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#endif
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#define ORION5X_DEFADR_PCI_IO 0xf0100000
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#define ORION5X_DEFSZ_PCI_IO (64*1024)
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#if !defined (ORION5X_ADR_PCIE_MEM_REMAP_HI)
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#define ORION5X_ADR_PCIE_MEM_REMAP_HI 0
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#endif
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#define ORION5X_DEFADR_DEV_CS0 0xfa000000
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#define ORION5X_DEFSZ_DEV_CS0 (2*1024*1024)
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#if !defined (ORION5X_SZ_PCIE_MEM)
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#define ORION5X_SZ_PCIE_MEM (128*1024*1024)
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#endif
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#define ORION5X_DEFADR_DEV_CS1 0xf8000000
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#define ORION5X_DEFSZ_DEV_CS1 (32*1024*1024)
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#if !defined (ORION5X_ADR_PCIE_IO)
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#define ORION5X_ADR_PCIE_IO 0xf0000000
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#endif
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#define ORION5X_DEFADR_DEV_CS2 0xfa800000
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#define ORION5X_DEFSZ_DEV_CS2 (1*1024*1024)
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#if !defined (ORION5X_ADR_PCIE_IO_REMAP_LO)
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#define ORION5X_ADR_PCIE_IO_REMAP_LO 0x90000000
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#endif
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#define ORION5X_DEFADR_BOOTROM 0xFFF80000
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#define ORION5X_DEFSZ_BOOTROM (512*1024)
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#if !defined (ORION5X_ADR_PCIE_IO_REMAP_HI)
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#define ORION5X_ADR_PCIE_IO_REMAP_HI 0
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#endif
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#if !defined (ORION5X_SZ_PCIE_IO)
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#define ORION5X_SZ_PCIE_IO (64*1024)
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#endif
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#if !defined (ORION5X_ADR_PCI_MEM)
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#define ORION5X_ADR_PCI_MEM 0x98000000
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#endif
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#if !defined (ORION5X_SZ_PCI_MEM)
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#define ORION5X_SZ_PCI_MEM (128*1024*1024)
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#endif
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#if !defined (ORION5X_ADR_PCI_IO)
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#define ORION5X_ADR_PCI_IO 0xf0100000
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#endif
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#if !defined (ORION5X_SZ_PCI_IO)
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#define ORION5X_SZ_PCI_IO (64*1024)
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#endif
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#if !defined (ORION5X_ADR_DEV_CS0)
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#define ORION5X_ADR_DEV_CS0 0xfa000000
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#endif
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#if !defined (ORION5X_SZ_DEV_CS0)
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#define ORION5X_SZ_DEV_CS0 (2*1024*1024)
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#endif
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#if !defined (ORION5X_ADR_DEV_CS1)
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#define ORION5X_ADR_DEV_CS1 0xf8000000
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#endif
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#if !defined (ORION5X_SZ_DEV_CS1)
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#define ORION5X_SZ_DEV_CS1 (32*1024*1024)
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#endif
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#if !defined (ORION5X_ADR_DEV_CS2)
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#define ORION5X_ADR_DEV_CS2 0xfa800000
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#endif
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#if !defined (ORION5X_SZ_DEV_CS2)
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#define ORION5X_SZ_DEV_CS2 (1*1024*1024)
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#endif
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#if !defined (ORION5X_ADR_BOOTROM)
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#define ORION5X_ADR_BOOTROM 0xFFF80000
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#endif
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#if !defined (ORION5X_SZ_BOOTROM)
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#define ORION5X_SZ_BOOTROM (512*1024)
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#endif
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/*
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* PCIE registers are used for SoC device ID and revision
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