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https://github.com/brain-hackers/u-boot-brain
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phy: mt76x8-usb-phy: add slew rate calibration and remove non-mt7628 part
This patch adds slew rate calibration for mt76x8-usb-phy, removes code which belongs to mt7620, and gets rid of using syscon and regmap by using clock driver and reset controller. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This commit is contained in:
Weijie Gao
Daniel Schwierzeck
parent
6658ebc96a
commit
4cce51141f
@ -200,6 +200,7 @@ config KEYSTONE_USB_PHY
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config MT76X8_USB_PHY
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bool "MediaTek MT76x8 (7628/88) USB PHY support"
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depends on PHY
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depends on SOC_MT7628
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help
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Support the USB PHY in MT76x8 SoCs
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@ -6,93 +6,185 @@
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* Copyright (C) 2017 John Crispin <john@phrozen.org>
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*/
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#include <clk.h>
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#include <common.h>
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#include <dm.h>
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#include <generic-phy.h>
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#include <regmap.h>
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#include <reset-uclass.h>
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#include <syscon.h>
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#include <reset.h>
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#include <asm/io.h>
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#define RT_SYSC_REG_SYSCFG1 0x014
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#define RT_SYSC_REG_CLKCFG1 0x030
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#define RT_SYSC_REG_USB_PHY_CFG 0x05c
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#include <linux/bitops.h>
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#define OFS_U2_PHY_AC0 0x800
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#define USBPLL_FBDIV_S 16
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#define USBPLL_FBDIV_M GENMASK(22, 16)
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#define BG_TRIM_S 8
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#define BG_TRIM_M GENMASK(11, 8)
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#define BG_RBSEL_S 6
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#define BG_RBSEL_M GENMASK(7, 6)
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#define BG_RASEL_S 4
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#define BG_RASEL_M GENMASK(5, 4)
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#define BGR_DIV_S 2
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#define BGR_DIV_M GENMASK(3, 2)
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#define CHP_EN BIT(1)
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#define OFS_U2_PHY_AC1 0x804
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#define VRT_VREF_SEL_S 28
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#define VRT_VREF_SEL_M GENMASK(30, 28)
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#define TERM_VREF_SEL_S 24
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#define TERM_VREF_SEL_M GENMASK(26, 24)
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#define USBPLL_RSVD BIT(4)
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#define USBPLL_ACCEN BIT(3)
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#define USBPLL_LF BIT(2)
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#define OFS_U2_PHY_AC2 0x808
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#define OFS_U2_PHY_ACR0 0x810
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#define OFS_U2_PHY_ACR1 0x814
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#define OFS_U2_PHY_ACR2 0x818
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#define HSTX_SRCAL_EN BIT(23)
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#define HSTX_SRCTRL_S 16
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#define HSTX_SRCTRL_M GENMASK(18, 16)
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#define OFS_U2_PHY_ACR3 0x81C
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#define OFS_U2_PHY_ACR4 0x820
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#define OFS_U2_PHY_AMON0 0x824
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#define HSTX_DBIST_S 28
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#define HSTX_DBIST_M GENMASK(31, 28)
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#define HSRX_BIAS_EN_SEL_S 20
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#define HSRX_BIAS_EN_SEL_M GENMASK(21, 20)
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#define OFS_U2_PHY_DCR0 0x860
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#define OFS_U2_PHY_DCR1 0x864
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#define PHYD_RESERVE_S 8
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#define PHYD_RESERVE_M GENMASK(23, 8)
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#define CDR_FILT_S 0
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#define CDR_FILT_M GENMASK(3, 0)
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#define OFS_U2_PHY_DTM0 0x868
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#define OFS_U2_PHY_DTM1 0x86C
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#define FORCE_USB_CLKEN BIT(25)
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#define RT_RSTCTRL_UDEV BIT(25)
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#define RT_RSTCTRL_UHST BIT(22)
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#define RT_SYSCFG1_USB0_HOST_MODE BIT(10)
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#define OFS_FM_CR0 0xf00
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#define FREQDET_EN BIT(24)
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#define CYCLECNT_S 0
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#define CYCLECNT_M GENMASK(23, 0)
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#define MT7620_CLKCFG1_UPHY0_CLK_EN BIT(25)
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#define MT7620_CLKCFG1_UPHY1_CLK_EN BIT(22)
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#define RT_CLKCFG1_UPHY1_CLK_EN BIT(20)
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#define RT_CLKCFG1_UPHY0_CLK_EN BIT(18)
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#define OFS_FM_MONR0 0xf0c
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#define USB_PHY_UTMI_8B60M BIT(1)
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#define UDEV_WAKEUP BIT(0)
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#define OFS_FM_MONR1 0xf10
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#define FRCK_EN BIT(8)
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#define U2_SR_COEF_7628 32
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struct mt76x8_usb_phy {
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u32 clk;
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void __iomem *base;
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struct regmap *sysctl;
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struct clk cg; /* for clock gating */
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struct reset_ctl rst_phy;
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};
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static void u2_phy_w32(struct mt76x8_usb_phy *phy, u32 val, u32 reg)
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static void phy_w32(struct mt76x8_usb_phy *phy, u32 reg, u32 val)
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{
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writel(val, phy->base + reg);
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}
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static u32 u2_phy_r32(struct mt76x8_usb_phy *phy, u32 reg)
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static u32 phy_r32(struct mt76x8_usb_phy *phy, u32 reg)
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{
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return readl(phy->base + reg);
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}
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static void phy_rmw32(struct mt76x8_usb_phy *phy, u32 reg, u32 clr, u32 set)
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{
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clrsetbits_32(phy->base + reg, clr, set);
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}
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static void mt76x8_usb_phy_init(struct mt76x8_usb_phy *phy)
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{
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u2_phy_r32(phy, OFS_U2_PHY_AC2);
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u2_phy_r32(phy, OFS_U2_PHY_ACR0);
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u2_phy_r32(phy, OFS_U2_PHY_DCR0);
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phy_r32(phy, OFS_U2_PHY_AC2);
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phy_r32(phy, OFS_U2_PHY_ACR0);
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phy_r32(phy, OFS_U2_PHY_DCR0);
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u2_phy_w32(phy, 0x00ffff02, OFS_U2_PHY_DCR0);
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u2_phy_r32(phy, OFS_U2_PHY_DCR0);
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u2_phy_w32(phy, 0x00555502, OFS_U2_PHY_DCR0);
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u2_phy_r32(phy, OFS_U2_PHY_DCR0);
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u2_phy_w32(phy, 0x00aaaa02, OFS_U2_PHY_DCR0);
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u2_phy_r32(phy, OFS_U2_PHY_DCR0);
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u2_phy_w32(phy, 0x00000402, OFS_U2_PHY_DCR0);
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u2_phy_r32(phy, OFS_U2_PHY_DCR0);
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u2_phy_w32(phy, 0x0048086a, OFS_U2_PHY_AC0);
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u2_phy_w32(phy, 0x4400001c, OFS_U2_PHY_AC1);
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u2_phy_w32(phy, 0xc0200000, OFS_U2_PHY_ACR3);
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u2_phy_w32(phy, 0x02000000, OFS_U2_PHY_DTM0);
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phy_w32(phy, OFS_U2_PHY_DCR0,
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(0xffff << PHYD_RESERVE_S) | (2 << CDR_FILT_S));
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phy_r32(phy, OFS_U2_PHY_DCR0);
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phy_w32(phy, OFS_U2_PHY_DCR0,
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(0x5555 << PHYD_RESERVE_S) | (2 << CDR_FILT_S));
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phy_r32(phy, OFS_U2_PHY_DCR0);
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phy_w32(phy, OFS_U2_PHY_DCR0,
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(0xaaaa << PHYD_RESERVE_S) | (2 << CDR_FILT_S));
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phy_r32(phy, OFS_U2_PHY_DCR0);
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phy_w32(phy, OFS_U2_PHY_DCR0,
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(4 << PHYD_RESERVE_S) | (2 << CDR_FILT_S));
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phy_r32(phy, OFS_U2_PHY_DCR0);
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phy_w32(phy, OFS_U2_PHY_AC0,
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(0x48 << USBPLL_FBDIV_S) | (8 << BG_TRIM_S) |
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(1 << BG_RBSEL_S) | (2 << BG_RASEL_S) | (2 << BGR_DIV_S) |
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CHP_EN);
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phy_w32(phy, OFS_U2_PHY_AC1,
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(4 << VRT_VREF_SEL_S) | (4 << TERM_VREF_SEL_S) | USBPLL_RSVD |
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USBPLL_ACCEN | USBPLL_LF);
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phy_w32(phy, OFS_U2_PHY_ACR3,
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(12 << HSTX_DBIST_S) | (2 << HSRX_BIAS_EN_SEL_S));
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phy_w32(phy, OFS_U2_PHY_DTM0, FORCE_USB_CLKEN);
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}
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static void mt76x8_usb_phy_sr_calibrate(struct mt76x8_usb_phy *phy)
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{
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u32 fmout, tmp = 4;
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int i;
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/* Enable HS TX SR calibration */
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phy_rmw32(phy, OFS_U2_PHY_ACR0, 0, HSTX_SRCAL_EN);
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mdelay(1);
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/* Enable free run clock */
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phy_rmw32(phy, OFS_FM_MONR1, 0, FRCK_EN);
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/* Set cycle count = 0x400 */
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phy_rmw32(phy, OFS_FM_CR0, CYCLECNT_M, 0x400 << CYCLECNT_S);
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/* Enable frequency meter */
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phy_rmw32(phy, OFS_FM_CR0, 0, FREQDET_EN);
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/* Wait for FM detection done, set timeout to 10ms */
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for (i = 0; i < 10; i++) {
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fmout = phy_r32(phy, OFS_FM_MONR0);
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if (fmout)
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break;
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mdelay(1);
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}
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/* Disable frequency meter */
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phy_rmw32(phy, OFS_FM_CR0, FREQDET_EN, 0);
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/* Disable free run clock */
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phy_rmw32(phy, OFS_FM_MONR1, FRCK_EN, 0);
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/* Disable HS TX SR calibration */
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phy_rmw32(phy, OFS_U2_PHY_ACR0, HSTX_SRCAL_EN, 0);
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mdelay(1);
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if (fmout) {
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/*
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* set reg = (1024 / FM_OUT) * 25 * 0.028
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* (round to the nearest digits)
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*/
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tmp = (((1024 * 25 * U2_SR_COEF_7628) / fmout) + 500) / 1000;
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}
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phy_rmw32(phy, OFS_U2_PHY_ACR0, HSTX_SRCTRL_M,
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(tmp << HSTX_SRCTRL_S) & HSTX_SRCTRL_M);
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}
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static int mt76x8_usb_phy_power_on(struct phy *_phy)
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{
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struct mt76x8_usb_phy *phy = dev_get_priv(_phy->dev);
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u32 t;
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/* enable the phy */
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regmap_update_bits(phy->sysctl, RT_SYSC_REG_CLKCFG1,
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phy->clk, phy->clk);
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clk_enable(&phy->cg);
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/* setup host mode */
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regmap_update_bits(phy->sysctl, RT_SYSC_REG_SYSCFG1,
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RT_SYSCFG1_USB0_HOST_MODE,
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RT_SYSCFG1_USB0_HOST_MODE);
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reset_deassert(&phy->rst_phy);
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/*
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* The SDK kernel had a delay of 100ms. however on device
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@ -100,17 +192,8 @@ static int mt76x8_usb_phy_power_on(struct phy *_phy)
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*/
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mdelay(10);
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if (phy->base)
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mt76x8_usb_phy_init(phy);
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/* print some status info */
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regmap_read(phy->sysctl, RT_SYSC_REG_USB_PHY_CFG, &t);
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printf("remote usb device wakeup %s\n",
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(t & UDEV_WAKEUP) ? "enabled" : "disabled");
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if (t & USB_PHY_UTMI_8B60M)
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printf("UTMI 8bit 60MHz\n");
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else
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printf("UTMI 16bit 30MHz\n");
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mt76x8_usb_phy_init(phy);
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mt76x8_usb_phy_sr_calibrate(phy);
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return 0;
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}
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@ -119,9 +202,9 @@ static int mt76x8_usb_phy_power_off(struct phy *_phy)
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{
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struct mt76x8_usb_phy *phy = dev_get_priv(_phy->dev);
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/* disable the phy */
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regmap_update_bits(phy->sysctl, RT_SYSC_REG_CLKCFG1,
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phy->clk, 0);
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clk_disable(&phy->cg);
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reset_assert(&phy->rst_phy);
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return 0;
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}
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@ -129,15 +212,21 @@ static int mt76x8_usb_phy_power_off(struct phy *_phy)
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static int mt76x8_usb_phy_probe(struct udevice *dev)
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{
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struct mt76x8_usb_phy *phy = dev_get_priv(dev);
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phy->sysctl = syscon_regmap_lookup_by_phandle(dev, "ralink,sysctl");
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if (IS_ERR(phy->sysctl))
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return PTR_ERR(phy->sysctl);
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int ret;
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phy->base = dev_read_addr_ptr(dev);
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if (!phy->base)
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return -EINVAL;
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/* clock gate */
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ret = clk_get_by_name(dev, "cg", &phy->cg);
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if (ret)
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return ret;
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ret = reset_get_by_name(dev, "phy", &phy->rst_phy);
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if (ret)
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return ret;
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return 0;
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}
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