mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-09 03:33:45 +09:00
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
This commit is contained in:
commit
4b7594c308
@ -146,7 +146,7 @@ _start_e500:
|
|||||||
beq 2b
|
beq 2b
|
||||||
|
|
||||||
/* Setup interrupt vectors */
|
/* Setup interrupt vectors */
|
||||||
lis r1,CONFIG_SYS_TEXT_BASE@h
|
lis r1,CONFIG_SYS_MONITOR_BASE@h
|
||||||
mtspr IVPR,r1
|
mtspr IVPR,r1
|
||||||
|
|
||||||
li r1,0x0100
|
li r1,0x0100
|
||||||
@ -292,25 +292,25 @@ _start_e500:
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|||||||
lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h
|
lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h
|
||||||
ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l
|
ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l
|
||||||
|
|
||||||
lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h
|
lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h
|
||||||
ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l
|
ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l
|
||||||
|
|
||||||
/* The 85xx has the default boot window 0xff800000 - 0xffffffff */
|
/* The 85xx has the default boot window 0xff800000 - 0xffffffff */
|
||||||
lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
|
lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
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||||||
ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
|
ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
|
||||||
#else
|
#else
|
||||||
/*
|
/*
|
||||||
* create a temp mapping in AS=1 to the 1M CONFIG_SYS_TEXT_BASE space, the main
|
* create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main
|
||||||
* image has been relocated to CONFIG_SYS_TEXT_BASE on the second stage.
|
* image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage.
|
||||||
*/
|
*/
|
||||||
lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
|
lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
|
||||||
ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
|
ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
|
||||||
|
|
||||||
lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, (MAS2_I|MAS2_G))@h
|
lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h
|
||||||
ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, (MAS2_I|MAS2_G))@l
|
ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l
|
||||||
|
|
||||||
lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
|
lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
|
||||||
ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
|
ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
mtspr MAS0,r6
|
mtspr MAS0,r6
|
||||||
|
@ -34,42 +34,16 @@ SECTIONS
|
|||||||
/* Read-only sections, merged into text segment: */
|
/* Read-only sections, merged into text segment: */
|
||||||
. = + SIZEOF_HEADERS;
|
. = + SIZEOF_HEADERS;
|
||||||
.interp : { *(.interp) }
|
.interp : { *(.interp) }
|
||||||
.hash : { *(.hash) }
|
|
||||||
.dynsym : { *(.dynsym) }
|
|
||||||
.dynstr : { *(.dynstr) }
|
|
||||||
.rel.text : { *(.rel.text) }
|
|
||||||
.rela.text : { *(.rela.text) }
|
|
||||||
.rel.data : { *(.rel.data) }
|
|
||||||
.rela.data : { *(.rela.data) }
|
|
||||||
.rel.rodata : { *(.rel.rodata) }
|
|
||||||
.rela.rodata : { *(.rela.rodata) }
|
|
||||||
.rel.got : { *(.rel.got) }
|
|
||||||
.rela.got : { *(.rela.got) }
|
|
||||||
.rel.ctors : { *(.rel.ctors) }
|
|
||||||
.rela.ctors : { *(.rela.ctors) }
|
|
||||||
.rel.dtors : { *(.rel.dtors) }
|
|
||||||
.rela.dtors : { *(.rela.dtors) }
|
|
||||||
.rel.bss : { *(.rel.bss) }
|
|
||||||
.rela.bss : { *(.rela.bss) }
|
|
||||||
.rel.plt : { *(.rel.plt) }
|
|
||||||
.rela.plt : { *(.rela.plt) }
|
|
||||||
.init : { *(.init) }
|
|
||||||
.plt : { *(.plt) }
|
|
||||||
.text :
|
.text :
|
||||||
{
|
{
|
||||||
*(.text)
|
*(.text*)
|
||||||
*(.got1)
|
|
||||||
} :text
|
} :text
|
||||||
_etext = .;
|
_etext = .;
|
||||||
PROVIDE (etext = .);
|
PROVIDE (etext = .);
|
||||||
.rodata :
|
.rodata :
|
||||||
{
|
{
|
||||||
*(.eh_frame)
|
|
||||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
|
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
|
||||||
} :text
|
} :text
|
||||||
.fini : { *(.fini) } =0
|
|
||||||
.ctors : { *(.ctors) }
|
|
||||||
.dtors : { *(.dtors) }
|
|
||||||
|
|
||||||
/* Read-write section, merged into data segment: */
|
/* Read-write section, merged into data segment: */
|
||||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||||
@ -77,23 +51,19 @@ SECTIONS
|
|||||||
PROVIDE (erotext = .);
|
PROVIDE (erotext = .);
|
||||||
.reloc :
|
.reloc :
|
||||||
{
|
{
|
||||||
*(.got)
|
KEEP(*(.got))
|
||||||
_GOT2_TABLE_ = .;
|
_GOT2_TABLE_ = .;
|
||||||
*(.got2)
|
KEEP(*(.got2))
|
||||||
_FIXUP_TABLE_ = .;
|
_FIXUP_TABLE_ = .;
|
||||||
*(.fixup)
|
KEEP(*(.fixup))
|
||||||
}
|
}
|
||||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
|
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
|
||||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
|
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
|
||||||
|
|
||||||
.data :
|
.data :
|
||||||
{
|
{
|
||||||
*(.data)
|
*(.data*)
|
||||||
*(.data1)
|
*(.sdata*)
|
||||||
*(.sdata)
|
|
||||||
*(.sdata2)
|
|
||||||
*(.dynamic)
|
|
||||||
CONSTRUCTORS
|
|
||||||
}
|
}
|
||||||
_edata = .;
|
_edata = .;
|
||||||
PROVIDE (edata = .);
|
PROVIDE (edata = .);
|
||||||
@ -117,7 +87,7 @@ SECTIONS
|
|||||||
|
|
||||||
.bootpg ADDR(.text) - 0x1000 :
|
.bootpg ADDR(.text) - 0x1000 :
|
||||||
{
|
{
|
||||||
arch/powerpc/cpu/mpc85xx/start.o (.bootpg)
|
arch/powerpc/cpu/mpc85xx/start.o KEEP(*(.bootpg))
|
||||||
} :text = 0xffff
|
} :text = 0xffff
|
||||||
|
|
||||||
. = ADDR(.text) + 0x80000;
|
. = ADDR(.text) + 0x80000;
|
||||||
@ -125,9 +95,8 @@ SECTIONS
|
|||||||
__bss_start = .;
|
__bss_start = .;
|
||||||
.bss (NOLOAD) :
|
.bss (NOLOAD) :
|
||||||
{
|
{
|
||||||
*(.sbss) *(.scommon)
|
*(.sbss*)
|
||||||
*(.dynbss)
|
*(.bss*)
|
||||||
*(.bss)
|
|
||||||
*(COMMON)
|
*(COMMON)
|
||||||
} :bss
|
} :bss
|
||||||
|
|
||||||
|
@ -28,15 +28,15 @@ SECTIONS
|
|||||||
{
|
{
|
||||||
. = 0xfff00000;
|
. = 0xfff00000;
|
||||||
.text : {
|
.text : {
|
||||||
*(.text)
|
*(.text*)
|
||||||
}
|
}
|
||||||
_etext = .;
|
_etext = .;
|
||||||
|
|
||||||
.reloc : {
|
.reloc : {
|
||||||
_GOT2_TABLE_ = .;
|
_GOT2_TABLE_ = .;
|
||||||
*(.got2)
|
KEEP(*(.got2))
|
||||||
_FIXUP_TABLE_ = .;
|
_FIXUP_TABLE_ = .;
|
||||||
*(.fixup)
|
KEEP(*(.fixup))
|
||||||
}
|
}
|
||||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
|
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
|
||||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
|
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
|
||||||
@ -54,13 +54,13 @@ SECTIONS
|
|||||||
__init_end = .;
|
__init_end = .;
|
||||||
|
|
||||||
.resetvec ADDR(.text) + 0xffc : {
|
.resetvec ADDR(.text) + 0xffc : {
|
||||||
*(.resetvec)
|
KEEP(*(.resetvec))
|
||||||
} = 0xffff
|
} = 0xffff
|
||||||
|
|
||||||
__bss_start = .;
|
__bss_start = .;
|
||||||
.bss : {
|
.bss : {
|
||||||
*(.sbss)
|
*(.sbss*)
|
||||||
*(.bss)
|
*(.bss*)
|
||||||
}
|
}
|
||||||
_end = .;
|
_end = .;
|
||||||
}
|
}
|
||||||
|
@ -45,6 +45,8 @@ int checkboard (void)
|
|||||||
{
|
{
|
||||||
u8 sw;
|
u8 sw;
|
||||||
struct cpu_type *cpu = gd->cpu;
|
struct cpu_type *cpu = gd->cpu;
|
||||||
|
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
|
||||||
|
unsigned int i;
|
||||||
|
|
||||||
printf("Board: %sDS, ", cpu->name);
|
printf("Board: %sDS, ", cpu->name);
|
||||||
printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
|
printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
|
||||||
@ -66,6 +68,19 @@ int checkboard (void)
|
|||||||
puts("36-bit Addressing\n");
|
puts("36-bit Addressing\n");
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
/* Display the RCW, so that no one gets confused as to what RCW
|
||||||
|
* we're actually using for this boot.
|
||||||
|
*/
|
||||||
|
puts("Reset Configuration Word (RCW):");
|
||||||
|
for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
|
||||||
|
u32 rcw = in_be32(&gur->rcwsr[i]);
|
||||||
|
|
||||||
|
if ((i % 4) == 0)
|
||||||
|
printf("\n %08x:", i * 4);
|
||||||
|
printf(" %08x", rcw);
|
||||||
|
}
|
||||||
|
puts("\n");
|
||||||
|
|
||||||
/* Display the actual SERDES reference clocks as configured by the
|
/* Display the actual SERDES reference clocks as configured by the
|
||||||
* dip switches on the board. Note that the SWx registers could
|
* dip switches on the board. Note that the SWx registers could
|
||||||
* technically be set to force the reference clocks to match the
|
* technically be set to force the reference clocks to match the
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
* Copyright 2009 Freescale Semiconductor, Inc.
|
* Copyright 2009-2010 Freescale Semiconductor, Inc.
|
||||||
*
|
*
|
||||||
* See file CREDITS for list of people who contributed to this
|
* See file CREDITS for list of people who contributed to this
|
||||||
* project.
|
* project.
|
||||||
@ -33,6 +33,7 @@
|
|||||||
#include <tsec.h>
|
#include <tsec.h>
|
||||||
#include <vsc7385.h>
|
#include <vsc7385.h>
|
||||||
#include <netdev.h>
|
#include <netdev.h>
|
||||||
|
#include <rtc.h>
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
@ -156,6 +157,7 @@ int board_early_init_r(void)
|
|||||||
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
|
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||||
0, flash_esel, BOOKE_PAGESZ_16M, 1);
|
0, flash_esel, BOOKE_PAGESZ_16M, 1);
|
||||||
|
rtc_reset();
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -298,7 +298,7 @@ int misc_init_r (void)
|
|||||||
*/
|
*/
|
||||||
set_lbc_or(0, ((-flash_info[1].size) & 0xffff8000) |
|
set_lbc_or(0, ((-flash_info[1].size) & 0xffff8000) |
|
||||||
(CONFIG_SYS_OR0_PRELIM & 0x00007fff));
|
(CONFIG_SYS_OR0_PRELIM & 0x00007fff));
|
||||||
set_lbc_br(0, gd->bd->bi_flashstart |
|
set_lbc_br(0, (gd->bd->bi_flashstart + flash_info[0].size) |
|
||||||
(CONFIG_SYS_BR0_PRELIM & 0x00007fff));
|
(CONFIG_SYS_BR0_PRELIM & 0x00007fff));
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -569,6 +569,7 @@ MPC8540EVAL powerpc mpc85xx mpc8540eval - - MPC8540EVAL:SYSCLK_66M
|
|||||||
MPC8540EVAL_33 powerpc mpc85xx mpc8540eval - - MPC8540EVAL
|
MPC8540EVAL_33 powerpc mpc85xx mpc8540eval - - MPC8540EVAL
|
||||||
MPC8540EVAL_66 powerpc mpc85xx mpc8540eval - - MPC8540EVAL:SYSCLK_66M
|
MPC8540EVAL_66 powerpc mpc85xx mpc8540eval - - MPC8540EVAL:SYSCLK_66M
|
||||||
P2020DS_36BIT powerpc mpc85xx p2020ds freescale - P2020DS:36BIT
|
P2020DS_36BIT powerpc mpc85xx p2020ds freescale - P2020DS:36BIT
|
||||||
|
P2020DS_DDR2 powerpc mpc85xx p2020ds freescale - P2020DS:DDR2
|
||||||
MPC8536DS powerpc mpc85xx mpc8536ds freescale - MPC8536DS
|
MPC8536DS powerpc mpc85xx mpc8536ds freescale - MPC8536DS
|
||||||
MPC8536DS_36BIT powerpc mpc85xx mpc8536ds freescale - MPC8536DS:36BIT
|
MPC8536DS_36BIT powerpc mpc85xx mpc8536ds freescale - MPC8536DS:36BIT
|
||||||
MPC8536DS_NAND powerpc mpc85xx mpc8536ds freescale - MPC8536DS:NAND
|
MPC8536DS_NAND powerpc mpc85xx mpc8536ds freescale - MPC8536DS:NAND
|
||||||
@ -589,7 +590,6 @@ P1020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,SDCARD
|
|||||||
P2010RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010
|
P2010RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010
|
||||||
P2010RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010,NAND
|
P2010RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010,NAND
|
||||||
P2010RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010,SDCARD
|
P2010RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010,SDCARD
|
||||||
P2020DS_DDR2 powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020,DDR2
|
|
||||||
P2020RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020
|
P2020RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020
|
||||||
P2020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020,NAND
|
P2020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020,NAND
|
||||||
P2020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020,SDCARD
|
P2020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020,SDCARD
|
||||||
|
@ -36,7 +36,12 @@
|
|||||||
#ifdef CONFIG_NAND
|
#ifdef CONFIG_NAND
|
||||||
#define CONFIG_NAND_U_BOOT 1
|
#define CONFIG_NAND_U_BOOT 1
|
||||||
#define CONFIG_RAMBOOT_NAND 1
|
#define CONFIG_RAMBOOT_NAND 1
|
||||||
|
#ifdef CONFIG_NAND_SPL
|
||||||
|
#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
|
||||||
|
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
|
||||||
|
#else
|
||||||
#define CONFIG_SYS_TEXT_BASE 0xf8f82000
|
#define CONFIG_SYS_TEXT_BASE 0xf8f82000
|
||||||
|
#endif /* CONFIG_NAND_SPL */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_SDCARD
|
#ifdef CONFIG_SDCARD
|
||||||
@ -53,6 +58,10 @@
|
|||||||
#define CONFIG_SYS_TEXT_BASE 0xeff80000
|
#define CONFIG_SYS_TEXT_BASE 0xeff80000
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#ifndef CONFIG_SYS_MONITOR_BASE
|
||||||
|
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
|
||||||
|
#endif
|
||||||
|
|
||||||
/* High Level Configuration Options */
|
/* High Level Configuration Options */
|
||||||
#define CONFIG_BOOKE 1 /* BOOKE */
|
#define CONFIG_BOOKE 1 /* BOOKE */
|
||||||
#define CONFIG_E500 1 /* BOOKE e500 family */
|
#define CONFIG_E500 1 /* BOOKE e500 family */
|
||||||
@ -233,8 +242,6 @@
|
|||||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
||||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||||
|
|
||||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
|
|
||||||
|
|
||||||
#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \
|
#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \
|
||||||
|| defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
|
|| defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
|
||||||
#define CONFIG_SYS_RAMBOOT
|
#define CONFIG_SYS_RAMBOOT
|
||||||
|
@ -65,13 +65,22 @@ extern unsigned long get_clock_freq(void);
|
|||||||
#ifdef CONFIG_NAND
|
#ifdef CONFIG_NAND
|
||||||
#define CONFIG_NAND_U_BOOT 1
|
#define CONFIG_NAND_U_BOOT 1
|
||||||
#define CONFIG_RAMBOOT_NAND 1
|
#define CONFIG_RAMBOOT_NAND 1
|
||||||
|
#ifdef CONFIG_NAND_SPL
|
||||||
|
#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
|
||||||
|
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
|
||||||
|
#else
|
||||||
#define CONFIG_SYS_TEXT_BASE 0xf8f82000
|
#define CONFIG_SYS_TEXT_BASE 0xf8f82000
|
||||||
#endif
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
#ifndef CONFIG_SYS_TEXT_BASE
|
#ifndef CONFIG_SYS_TEXT_BASE
|
||||||
#define CONFIG_SYS_TEXT_BASE 0xfff80000
|
#define CONFIG_SYS_TEXT_BASE 0xfff80000
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#ifndef CONFIG_SYS_MONITOR_BASE
|
||||||
|
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
|
||||||
|
#endif
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Only possible on E500 Version 2 or newer cores.
|
* Only possible on E500 Version 2 or newer cores.
|
||||||
*/
|
*/
|
||||||
@ -194,8 +203,6 @@ extern unsigned long get_clock_freq(void);
|
|||||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
||||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||||
|
|
||||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
|
|
||||||
|
|
||||||
#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND)
|
#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND)
|
||||||
#define CONFIG_SYS_RAMBOOT
|
#define CONFIG_SYS_RAMBOOT
|
||||||
#else
|
#else
|
||||||
@ -488,6 +495,7 @@ extern unsigned long get_clock_freq(void);
|
|||||||
|
|
||||||
#undef CONFIG_EEPRO100
|
#undef CONFIG_EEPRO100
|
||||||
#undef CONFIG_TULIP
|
#undef CONFIG_TULIP
|
||||||
|
#define CONFIG_E1000 /* Define e1000 pci Ethernet card */
|
||||||
|
|
||||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||||
|
|
||||||
|
@ -474,6 +474,7 @@
|
|||||||
#undef CONFIG_EEPRO100
|
#undef CONFIG_EEPRO100
|
||||||
#undef CONFIG_TULIP
|
#undef CONFIG_TULIP
|
||||||
#undef CONFIG_RTL8139
|
#undef CONFIG_RTL8139
|
||||||
|
#define CONFIG_E1000 /* Define e1000 pci Ethernet card */
|
||||||
|
|
||||||
#ifndef CONFIG_PCI_PNP
|
#ifndef CONFIG_PCI_PNP
|
||||||
#define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
|
#define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
|
||||||
|
@ -270,6 +270,7 @@
|
|||||||
#define CONFIG_NET_MULTI
|
#define CONFIG_NET_MULTI
|
||||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||||
|
#define CONFIG_E1000 /* Define e1000 pci Ethernet card */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* SATA */
|
/* SATA */
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
* Copyright 2009 Freescale Semiconductor, Inc.
|
* Copyright 2009-2010 Freescale Semiconductor, Inc.
|
||||||
*
|
*
|
||||||
* See file CREDITS for list of people who contributed to this
|
* See file CREDITS for list of people who contributed to this
|
||||||
* project.
|
* project.
|
||||||
@ -46,7 +46,12 @@
|
|||||||
#ifdef CONFIG_NAND
|
#ifdef CONFIG_NAND
|
||||||
#define CONFIG_NAND_U_BOOT 1
|
#define CONFIG_NAND_U_BOOT 1
|
||||||
#define CONFIG_RAMBOOT_NAND 1
|
#define CONFIG_RAMBOOT_NAND 1
|
||||||
|
#ifdef CONFIG_NAND_SPL
|
||||||
|
#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
|
||||||
|
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
|
||||||
|
#else
|
||||||
#define CONFIG_SYS_TEXT_BASE 0xf8f82000
|
#define CONFIG_SYS_TEXT_BASE 0xf8f82000
|
||||||
|
#endif /* CONFIG_NAND_SPL */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_SDCARD
|
#ifdef CONFIG_SDCARD
|
||||||
@ -63,6 +68,10 @@
|
|||||||
#define CONFIG_SYS_TEXT_BASE 0xeff80000
|
#define CONFIG_SYS_TEXT_BASE 0xeff80000
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#ifndef CONFIG_SYS_MONITOR_BASE
|
||||||
|
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
|
||||||
|
#endif
|
||||||
|
|
||||||
/* High Level Configuration Options */
|
/* High Level Configuration Options */
|
||||||
#define CONFIG_BOOKE 1 /* BOOKE */
|
#define CONFIG_BOOKE 1 /* BOOKE */
|
||||||
#define CONFIG_E500 1 /* BOOKE e500 family */
|
#define CONFIG_E500 1 /* BOOKE e500 family */
|
||||||
@ -192,8 +201,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
|
|||||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
||||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||||
|
|
||||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
|
|
||||||
|
|
||||||
#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \
|
#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \
|
||||||
|| defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
|
|| defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
|
||||||
#define CONFIG_SYS_RAMBOOT
|
#define CONFIG_SYS_RAMBOOT
|
||||||
@ -343,6 +350,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
|
|||||||
#define CONFIG_SYS_EEPROM_BUS_NUM 1
|
#define CONFIG_SYS_EEPROM_BUS_NUM 1
|
||||||
|
|
||||||
#define CONFIG_RTC_DS1337
|
#define CONFIG_RTC_DS1337
|
||||||
|
#define CONFIG_SYS_RTC_DS1337_NOOSC
|
||||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
|
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
|
||||||
/*
|
/*
|
||||||
* General PCI
|
* General PCI
|
||||||
|
@ -33,11 +33,9 @@
|
|||||||
#define CONFIG_SYS_NUM_FM2_10GEC 1
|
#define CONFIG_SYS_NUM_FM2_10GEC 1
|
||||||
#define CONFIG_NUM_DDR_CONTROLLERS 2
|
#define CONFIG_NUM_DDR_CONTROLLERS 2
|
||||||
|
|
||||||
|
#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 ref clk freq */
|
||||||
|
|
||||||
#define CONFIG_SYS_P4080_ERRATUM_CPU22
|
#define CONFIG_SYS_P4080_ERRATUM_CPU22
|
||||||
#define CONFIG_SYS_P4080_ERRATUM_SERDES8
|
#define CONFIG_SYS_P4080_ERRATUM_SERDES8
|
||||||
|
|
||||||
#ifndef CONFIG_SYS_TEXT_BASE
|
|
||||||
#define CONFIG_SYS_TEXT_BASE 0xeff80000
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#include "corenet_ds.h"
|
#include "corenet_ds.h"
|
||||||
|
@ -37,6 +37,10 @@
|
|||||||
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
||||||
#define CONFIG_MP /* support multiple processors */
|
#define CONFIG_MP /* support multiple processors */
|
||||||
|
|
||||||
|
#ifndef CONFIG_SYS_TEXT_BASE
|
||||||
|
#define CONFIG_SYS_TEXT_BASE 0xeff80000
|
||||||
|
#endif
|
||||||
|
|
||||||
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
|
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
|
||||||
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
|
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
|
||||||
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
|
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
|
||||||
@ -64,7 +68,6 @@
|
|||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
|
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
|
||||||
#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* These can be toggled for performance analysis, otherwise use default.
|
* These can be toggled for performance analysis, otherwise use default.
|
||||||
@ -475,6 +478,7 @@
|
|||||||
#define CONFIG_CMD_MII
|
#define CONFIG_CMD_MII
|
||||||
#define CONFIG_CMD_PING
|
#define CONFIG_CMD_PING
|
||||||
#define CONFIG_CMD_SETEXPR
|
#define CONFIG_CMD_SETEXPR
|
||||||
|
#define CONFIG_CMD_DHCP
|
||||||
|
|
||||||
#ifdef CONFIG_PCI
|
#ifdef CONFIG_PCI
|
||||||
#define CONFIG_CMD_PCI
|
#define CONFIG_CMD_PCI
|
||||||
|
@ -24,13 +24,13 @@
|
|||||||
#
|
#
|
||||||
|
|
||||||
NAND_SPL := y
|
NAND_SPL := y
|
||||||
CONFIG_SYS_TEXT_BASE := 0xfff00000
|
CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000
|
||||||
PAD_TO := 0xfff01000
|
PAD_TO := 0xfff01000
|
||||||
|
|
||||||
include $(TOPDIR)/config.mk
|
include $(TOPDIR)/config.mk
|
||||||
|
|
||||||
LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
|
LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
|
||||||
LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(CONFIG_SYS_TEXT_BASE) $(PLATFORM_LDFLAGS)
|
LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) $(PLATFORM_LDFLAGS)
|
||||||
AFLAGS += -DCONFIG_NAND_SPL
|
AFLAGS += -DCONFIG_NAND_SPL
|
||||||
CFLAGS += -DCONFIG_NAND_SPL
|
CFLAGS += -DCONFIG_NAND_SPL
|
||||||
|
|
||||||
|
@ -24,13 +24,13 @@
|
|||||||
#
|
#
|
||||||
|
|
||||||
NAND_SPL := y
|
NAND_SPL := y
|
||||||
CONFIG_SYS_TEXT_BASE := 0xfff00000
|
CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000
|
||||||
PAD_TO := 0xfff01000
|
PAD_TO := 0xfff01000
|
||||||
|
|
||||||
include $(TOPDIR)/config.mk
|
include $(TOPDIR)/config.mk
|
||||||
|
|
||||||
LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
|
LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
|
||||||
LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(CONFIG_SYS_TEXT_BASE) $(PLATFORM_LDFLAGS)
|
LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) $(PLATFORM_LDFLAGS)
|
||||||
AFLAGS += -DCONFIG_NAND_SPL
|
AFLAGS += -DCONFIG_NAND_SPL
|
||||||
CFLAGS += -DCONFIG_NAND_SPL
|
CFLAGS += -DCONFIG_NAND_SPL
|
||||||
|
|
||||||
|
@ -24,13 +24,13 @@
|
|||||||
#
|
#
|
||||||
|
|
||||||
NAND_SPL := y
|
NAND_SPL := y
|
||||||
CONFIG_SYS_TEXT_BASE := 0xfff00000
|
CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000
|
||||||
PAD_TO := 0xfff01000
|
PAD_TO := 0xfff01000
|
||||||
|
|
||||||
include $(TOPDIR)/config.mk
|
include $(TOPDIR)/config.mk
|
||||||
|
|
||||||
LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
|
LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
|
||||||
LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(CONFIG_SYS_TEXT_BASE) $(PLATFORM_LDFLAGS)
|
LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) $(PLATFORM_LDFLAGS)
|
||||||
AFLAGS += -DCONFIG_NAND_SPL
|
AFLAGS += -DCONFIG_NAND_SPL
|
||||||
CFLAGS += -DCONFIG_NAND_SPL
|
CFLAGS += -DCONFIG_NAND_SPL
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user