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https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
ARM: dts: omap3-beagle{-xm}: Enable DM and devicetree for BeagleBoard
This commit updates the configuration files needed to support OF_CONTROL on the OMAP3 BeagleBoard(s).
This commit is contained in:
Derald D. Woods
Tom Rini
parent
3ff0d80181
commit
4b37928d35
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@ -103,6 +103,17 @@ int board_init(void)
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return 0;
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}
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#if defined(CONFIG_SPL_OS_BOOT)
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int spl_start_uboot(void)
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{
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/* break into full u-boot on 'c' */
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if (serial_tstc() && serial_getc() == 'c')
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return 1;
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return 0;
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}
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#endif /* CONFIG_SPL_OS_BOOT */
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/*
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* Routine: get_board_revision
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* Description: Detect if we are running on a Beagle revision Ax/Bx,
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@ -2,9 +2,11 @@ CONFIG_ARM=y
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CONFIG_ARCH_OMAP2PLUS=y
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CONFIG_SYS_TEXT_BASE=0x80100000
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CONFIG_TARGET_OMAP3_BEAGLE=y
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CONFIG_DEFAULT_DEVICE_TREE="omap3-beagle"
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CONFIG_DISTRO_DEFAULTS=y
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# CONFIG_USE_BOOTCOMMAND is not set
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CONFIG_SYS_CONSOLE_INFO_QUIET=y
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CONFIG_DEFAULT_FDT_FILE="omap3-beagle.dtb"
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CONFIG_VERSION_VARIABLE=y
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CONFIG_SPL=y
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CONFIG_SPL_MTD_SUPPORT=y
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@ -26,7 +28,9 @@ CONFIG_CMD_EXT4_WRITE=y
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CONFIG_CMD_MTDPARTS=y
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CONFIG_MTDIDS_DEFAULT="nand0=nand"
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CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:512k(x-loader),1920k(u-boot),128k(u-boot-env),4m(kernel),-(fs)"
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CONFIG_OF_CONTROL=y
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CONFIG_ENV_IS_IN_NAND=y
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# CONFIG_BLK is not set
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CONFIG_LED_STATUS=y
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CONFIG_LED_STATUS0=y
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CONFIG_LED_STATUS_BIT=1
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@ -59,4 +63,5 @@ CONFIG_USB_ETHER_ASIX=y
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CONFIG_USB_ETHER_MCS7830=y
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CONFIG_USB_ETHER_SMSC95XX=y
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CONFIG_FAT_WRITE=y
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CONFIG_BCH=y
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CONFIG_OF_LIBFDT=y
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@ -14,57 +14,69 @@
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#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
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/*
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* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
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* 64 bytes before this address should be set aside for u-boot.img's
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* header. That is 0x800FFFC0--0x80100000 should not be used for any
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* other needs. We use this rather than the inherited defines from
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* ti_armv7_common.h for backwards compatibility.
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*/
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#define CONFIG_SYS_TEXT_BASE 0x80100000
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#define CONFIG_SPL_BSS_START_ADDR 0x80000000
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#define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */
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#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
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#include <configs/ti_omap3_common.h>
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/*
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* We are only ever GP parts and will utilize all of the "downloaded image"
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* area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB).
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*/
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#undef CONFIG_SPL_TEXT_BASE
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#define CONFIG_SPL_TEXT_BASE 0x40200000
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_MISC_INIT_R
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_REVISION_TAG
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#define CONFIG_REVISION_TAG 1
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/* NAND */
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#if defined(CONFIG_NAND)
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#define CONFIG_SYS_FLASH_BASE NAND_BASE
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_PAGE_COUNT 64
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
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#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
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10, 11, 12, 13}
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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#define CONFIG_ENV_IS_IN_NAND 1
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#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
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#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
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#define CONFIG_ENV_OFFSET 0x260000
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#define CONFIG_ENV_ADDR 0x260000
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_MTD_PARTITIONS /* required for UBI partition support */
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/* NAND: SPL falcon mode configs */
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#if defined(CONFIG_SPL_OS_BOOT)
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#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
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#endif /* CONFIG_SPL_OS_BOOT */
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#endif /* CONFIG_NAND */
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/* Status LED */
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/* Enable Multi Bus support for I2C */
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#define CONFIG_I2C_MULTI_BUS 1
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/* Probe all devices */
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#define CONFIG_SYS_I2C_NOPROBES {{0x0, 0x0}}
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/* USB */
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/* MUSB */
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#define CONFIG_USB_OMAP3
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#define CONFIG_USB_MUSB_OMAP2PLUS
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#define CONFIG_USB_MUSB_PIO_ONLY
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#define CONFIG_TWL4030_USB 1
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#define CONFIG_TWL4030_USB
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/* USB EHCI */
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#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 147
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/* commands to include */
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/* Enable Multi Bus support for I2C */
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#define CONFIG_I2C_MULTI_BUS
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#define CONFIG_VIDEO_OMAP3 /* DSS Support */
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/* DSS Support */
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#define CONFIG_VIDEO_OMAP3
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/*
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* TWL4030
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*/
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#define CONFIG_TWL4030_LED 1
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/*
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* Board NAND Info.
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*/
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
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/* devices */
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/* TWL4030 LED Support */
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#define CONFIG_TWL4030_LED
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 0)
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@ -91,6 +103,7 @@
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"run bootscript; " \
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"else " \
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"if run loadimage; then " \
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"run loadfdt;" \
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"run mmcboot;" \
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"fi;" \
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"fi; " \
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@ -105,13 +118,8 @@
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#include <config_distro_bootcmd.h>
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"loadaddr=0x80200000\0" \
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"kernel_addr_r=0x80200000\0" \
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"rdaddr=0x81000000\0" \
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"initrd_addr_r=0x81000000\0" \
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DEFAULT_LINUX_BOOT_ENV \
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"fdt_high=0xffffffff\0" \
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"fdtaddr=0x80f80000\0" \
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"fdt_addr_r=0x80f80000\0" \
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"usbtty=cdc_acm\0" \
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"bootfile=uImage\0" \
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"ramdisk=ramdisk.gz\0" \
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@ -127,7 +135,7 @@
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"defaultdisplay=dvi\0" \
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"mmcdev=0\0" \
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"mmcroot=/dev/mmcblk0p2 rw\0" \
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"mmcrootfstype=ext3 rootwait\0" \
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"mmcrootfstype=ext4 rootwait\0" \
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"nandroot=ubi0:rootfs ubi.mtd=4\0" \
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"nandrootfstype=ubifs\0" \
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"ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=0x81000000,64M\0" \
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@ -190,10 +198,10 @@
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"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
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"source ${loadaddr}\0" \
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"loadfdt=run validatefdt; load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
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"mmcboot=echo Booting from mmc ...; " \
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"mmcboot=echo Booting ${bootfile} with DT from mmc${mmcdev} ...; " \
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"run mmcargs; " \
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"bootm ${loadaddr}\0" \
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"mmcbootz=echo Booting with DT from mmc${mmcdev} ...; " \
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"bootm ${loadaddr} - ${fdtaddr}\0" \
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"mmcbootz=echo Booting ${bootfile} with DT from mmc${mmcdev} ...; " \
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"run mmcargs; " \
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"bootz ${loadaddr} - ${fdtaddr}\0" \
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"nandboot=echo Booting from nand ...; " \
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@ -209,51 +217,4 @@
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"userbutton_nonxm=gpio input 7;\0" \
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BOOTENV
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/*
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* OMAP3 has 12 GP timers, they can be driven by the system clock
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* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
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* This rate is divided by a local divisor.
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*/
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#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*/
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/* **** PISMO SUPPORT *** */
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#if defined(CONFIG_CMD_NAND)
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#define CONFIG_SYS_FLASH_BASE NAND_BASE
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#endif
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/* Monitor at start of flash */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
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#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
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#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
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#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
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#define CONFIG_ENV_OFFSET 0x260000
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#define CONFIG_ENV_ADDR 0x260000
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/* Defines for SPL */
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/* NAND boot config */
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_PAGE_COUNT 64
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
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#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
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10, 11, 12, 13}
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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/* NAND: SPL falcon mode configs */
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#ifdef CONFIG_SPL_OS_BOOT
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#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
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#endif
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#endif /* __CONFIG_H */
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