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Merge branch 'master' of /home/stefan/git/u-boot/u-boot into next

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This commit is contained in:
Stefan Roese 2008-07-14 10:45:47 +02:00
commit 4b326101d6
69 changed files with 712 additions and 1297 deletions
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663
MAINTAINERS
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File diff suppressed because it is too large Load Diff

14
MAKEALL
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@ -462,13 +462,6 @@ LIST_ARM7=" \
#########################################################################
LIST_ARM9=" \
at91cap9adk \
at91rm9200dk \
at91sam9260ek \
at91sam9261ek \
at91sam9263ek \
at91sam9rlek \
cmc_pu2 \
ap920t \
ap922_XA10 \
ap926ejs \
@ -479,11 +472,7 @@ LIST_ARM9=" \
cp926ejs \
cp946es \
cp966 \
csb637 \
kb9202 \
lpd7a400 \
m501sk \
mp2usb \
mx1ads \
mx1fs2 \
netstar \
@ -588,6 +577,7 @@ LIST_arm=" \
${LIST_ARM9} \
${LIST_ARM10} \
${LIST_ARM11} \
${LIST_at91} \
${LIST_pxa} \
${LIST_ixp} \
"
@ -702,7 +692,7 @@ LIST_coldfire=" \
M52277EVB \
M5235EVB \
M5249EVB \
M5253EVB \
M5253EVBE \
M5271EVB \
M5272C3 \
M5275EVB \

2
board/BuS/EB+MCF-EV123/mii.c
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@ -201,7 +201,7 @@ int mii_discover_phy(struct eth_device *dev)
}
#endif /* CFG_DISCOVER_PHY */
int mii_init(void) __attribute__((weak,alias("__mii_init")));
void mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{

1
board/ads5121/ads5121.c
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@ -23,6 +23,7 @@
#include <common.h>
#include <mpc512x.h>
#include "iopin.h"
#include <asm/bitops.h>
#include <command.h>
#include <fdt_support.h>

2
board/ads5121/ads5121_diu.c
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@ -57,7 +57,7 @@ void diu_set_pixel_clock(unsigned int pixclock)
/* Modify PXCLK in GUTS CLKDVDR */
debug("DIU: Current value of CLKDVDR = 0x%08x\n", *clkdvdr);
temp = *clkdvdr & 0xFFFFFF00;
*clkdvdr = temp | (pixval & 0x1F);
*clkdvdr = temp | (pixval & 0xFF);
debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *clkdvdr);
}

111
board/ads5121/iopin.c
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@ -25,71 +25,90 @@
#include <linux/types.h>
#include "iopin.h"
/*
* IO PAD TYPES
* for all types fmux is used to select the funtion
* ds sets the slew rate
* STD pins nothing extra (can set ds & fmux only)
* STD_PU pue=1 to enable pull & pud sets whether up or down resistors
* STD_ST st sets the Schmitt trigger
* STD_PU_ST pue & pud sets pull-up/down resistors as in STD_PU
* st sets the Schmitt trigger
* PCI hold sets output delay
* PCI_ST hold sets output delay and st sets the Schmitt trigger
*/
/* IO pin fields */
#define IO_PIN_FMUX(v) ((v) << 7) /* pin function */
#define IO_PIN_HOLD(v) ((v) << 5) /* hold time, pci only */
#define IO_PIN_PUD(v) ((v) << 4) /* if PUE, 0=pull-down, 1=pull-up */
#define IO_PIN_PUE(v) ((v) << 3) /* pull up/down enable */
#define IO_PIN_ST(v) ((v) << 2) /* schmitt trigger */
#define IO_PIN_DS(v) ((v)) /* slew rate */
static struct iopin_t {
u_short p_offset; /* offset from IOCTL_MEM_OFFSET */
u_short p_no; /* number of pins to set this way */
u_short bit_or:7; /* Do bitwise OR instead of setting */
u_short fmux:2; /* pad function select 0-3 */
u_short hold:2; /* PCI pad types only; */
u_short pud:1; /* pull resistor; PU types only; */
/* if pue=1 then 0=pull-down, 1=pull-up */
u_short pue:1; /* Pull resistor enable; _PU types only */
u_short st:1; /* Schmitt trigger enable; _ST types only */
u_short ds:2; /* Slew rate class, 0=class1, ..., 3=class4 */
int p_offset; /* offset from IOCTL_MEM_OFFSET */
int nr_pins; /* number of pins to set this way */
int bit_or; /* or in the value instead of overwrite */
u_long val; /* value to write or or */
} ioregs_init[] = {
/* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
{IOCTL_SPDIF_TXCLK, 3, 0, 1, 0, 0, 0, 0, 3},
/* Set highest Slew on 9 PATA pins */
{IOCTL_PATA_CE1, 9, 1, 0, 0, 0, 0, 0, 3},
/* FUNC1=FEC_COL Sets Next 15 to FEC pads */
{IOCTL_PSC0_0, 15, 0, 1, 0, 0, 0, 0, 3},
/* FUNC1=SPDIF_TXCLK */
{IOCTL_LPC_CS1, 1, 0, 1, 0, 0, 0, 1, 3},
/* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
{IOCTL_I2C1_SCL, 2, 0, 2, 0, 0, 0, 1, 3},
/* FUNC2=DIU CLK */
{IOCTL_PSC6_0, 1, 0, 2, 0, 0, 0, 1, 3},
/* FUNC2=DIU_HSYNC */
{IOCTL_PSC6_1, 1, 0, 2, 0, 0, 0, 0, 3},
/* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
{IOCTL_PSC6_4, 26, 0, 2, 0, 0, 0, 0, 3}
/* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
{
IOCTL_SPDIF_TXCLK, 3, 0,
IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
},
/* Set highest Slew on 9 PATA pins */
{
IOCTL_PATA_CE1, 9, 1,
IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
},
/* FUNC1=FEC_COL Sets Next 15 to FEC pads */
{
IOCTL_PSC0_0, 15, 0,
IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
},
/* FUNC1=SPDIF_TXCLK */
{
IOCTL_LPC_CS1, 1, 0,
IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
},
/* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
{
IOCTL_I2C1_SCL, 2, 0,
IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
},
/* FUNC2=DIU CLK */
{
IOCTL_PSC6_0, 1, 0,
IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
},
/* FUNC2=DIU_HSYNC */
{
IOCTL_PSC6_1, 1, 0,
IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
},
/* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
{
IOCTL_PSC6_4, 26, 0,
IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
}
};
void iopin_initialize(void)
{
short i, j, n, p;
u_long *reg;
immap_t *im = (immap_t *)CFG_IMMR;
reg = (u_long *)&(im->io_ctrl.regs[0]);
if (sizeof(ioregs_init) == 0)
return;
immap_t *im = (immap_t *)CFG_IMMR;
reg = (u_long *)&(im->io_ctrl.regs[0]);
n = sizeof(ioregs_init) / sizeof(ioregs_init[0]);
for (i = 0; i < n; i++) {
for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long);
p < ioregs_init[i].p_no; p++, j++) {
/* lowest 9 bits sets the register */
p < ioregs_init[i].nr_pins; p++, j++) {
if (ioregs_init[i].bit_or)
reg[j] |= *((u_long *) &ioregs_init[i].p_no)
& 0x000001ff;
reg[j] |= ioregs_init[i].val;
else
reg[j] = *((u_long *) &ioregs_init[i].p_no)
& 0x000001ff;
reg[j] = ioregs_init[i].val;
}
}
return;

104
board/amcc/taishan/showinfo.c
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@ -34,59 +34,59 @@ void show_reset_reg(void)
/* read clock regsiter */
printf("===== Display reset and initialize register Start =========\n");
mfcpr(clk_pllc,reg);
printf("cpr_pllc = %#010x\n",reg);
printf("cpr_pllc = %#010lx\n",reg);
mfcpr(clk_plld,reg);
printf("cpr_plld = %#010x\n",reg);
printf("cpr_plld = %#010lx\n",reg);
mfcpr(clk_primad,reg);
printf("cpr_primad = %#010x\n",reg);
printf("cpr_primad = %#010lx\n",reg);
mfcpr(clk_primbd,reg);
printf("cpr_primbd = %#010x\n",reg);
printf("cpr_primbd = %#010lx\n",reg);
mfcpr(clk_opbd,reg);
printf("cpr_opbd = %#010x\n",reg);
printf("cpr_opbd = %#010lx\n",reg);
mfcpr(clk_perd,reg);
printf("cpr_perd = %#010x\n",reg);
printf("cpr_perd = %#010lx\n",reg);
mfcpr(clk_mald,reg);
printf("cpr_mald = %#010x\n",reg);
printf("cpr_mald = %#010lx\n",reg);
/* read sdr register */
mfsdr(sdr_ebc,reg);
printf("sdr_ebc = %#010x\n",reg);
printf("sdr_ebc = %#010lx\n",reg);
mfsdr(sdr_cp440,reg);
printf("sdr_cp440 = %#010x\n",reg);
printf("sdr_cp440 = %#010lx\n",reg);
mfsdr(sdr_xcr,reg);
printf("sdr_xcr = %#010x\n",reg);
printf("sdr_xcr = %#010lx\n",reg);
mfsdr(sdr_xpllc,reg);
printf("sdr_xpllc = %#010x\n",reg);
printf("sdr_xpllc = %#010lx\n",reg);
mfsdr(sdr_xplld,reg);
printf("sdr_xplld = %#010x\n",reg);
printf("sdr_xplld = %#010lx\n",reg);
mfsdr(sdr_pfc0,reg);
printf("sdr_pfc0 = %#010x\n",reg);
printf("sdr_pfc0 = %#010lx\n",reg);
mfsdr(sdr_pfc1,reg);
printf("sdr_pfc1 = %#010x\n",reg);
printf("sdr_pfc1 = %#010lx\n",reg);
mfsdr(sdr_cust0,reg);
printf("sdr_cust0 = %#010x\n",reg);
printf("sdr_cust0 = %#010lx\n",reg);
mfsdr(sdr_cust1,reg);
printf("sdr_cust1 = %#010x\n",reg);
printf("sdr_cust1 = %#010lx\n",reg);
mfsdr(sdr_uart0,reg);
printf("sdr_uart0 = %#010x\n",reg);
printf("sdr_uart0 = %#010lx\n",reg);
mfsdr(sdr_uart1,reg);
printf("sdr_uart1 = %#010x\n",reg);
printf("sdr_uart1 = %#010lx\n",reg);
printf("===== Display reset and initialize register End =========\n");
}
@ -97,13 +97,13 @@ void show_xbridge_info(void)
printf("PCI-X chip control registers\n");
mfsdr(sdr_xcr, reg);
printf("sdr_xcr = %#010x\n", reg);
printf("sdr_xcr = %#010lx\n", reg);
mfsdr(sdr_xpllc, reg);
printf("sdr_xpllc = %#010x\n", reg);
printf("sdr_xpllc = %#010lx\n", reg);
mfsdr(sdr_xplld, reg);
printf("sdr_xplld = %#010x\n", reg);
printf("sdr_xplld = %#010lx\n", reg);
printf("PCI-X Bridge Configure registers\n");
printf("PCIX0_VENDID = %#06x\n", in16r(PCIX0_VENDID));
@ -116,49 +116,49 @@ void show_xbridge_info(void)
printf("PCIX0_HDTYPE = %#04x\n", in8(PCIX0_HDTYPE));
printf("PCIX0_BIST = %#04x\n", in8(PCIX0_BIST));
printf("PCIX0_BAR0 = %#010x\n", in32r(PCIX0_BAR0));
printf("PCIX0_BAR1 = %#010x\n", in32r(PCIX0_BAR1));
printf("PCIX0_BAR2 = %#010x\n", in32r(PCIX0_BAR2));
printf("PCIX0_BAR3 = %#010x\n", in32r(PCIX0_BAR3));
printf("PCIX0_BAR4 = %#010x\n", in32r(PCIX0_BAR4));
printf("PCIX0_BAR5 = %#010x\n", in32r(PCIX0_BAR5));
printf("PCIX0_BAR0 = %#010lx\n", in32r(PCIX0_BAR0));
printf("PCIX0_BAR1 = %#010lx\n", in32r(PCIX0_BAR1));
printf("PCIX0_BAR2 = %#010lx\n", in32r(PCIX0_BAR2));
printf("PCIX0_BAR3 = %#010lx\n", in32r(PCIX0_BAR3));
printf("PCIX0_BAR4 = %#010lx\n", in32r(PCIX0_BAR4));
printf("PCIX0_BAR5 = %#010lx\n", in32r(PCIX0_BAR5));
printf("PCIX0_CISPTR = %#010x\n", in32r(PCIX0_CISPTR));
printf("PCIX0_CISPTR = %#010lx\n", in32r(PCIX0_CISPTR));
printf("PCIX0_SBSSYSVID = %#010x\n", in16r(PCIX0_SBSYSVID));
printf("PCIX0_SBSSYSID = %#010x\n", in16r(PCIX0_SBSYSID));
printf("PCIX0_EROMBA = %#010x\n", in32r(PCIX0_EROMBA));
printf("PCIX0_EROMBA = %#010lx\n", in32r(PCIX0_EROMBA));
printf("PCIX0_CAP = %#04x\n", in8(PCIX0_CAP));
printf("PCIX0_INTLN = %#04x\n", in8(PCIX0_INTLN));
printf("PCIX0_INTPN = %#04x\n", in8(PCIX0_INTPN));
printf("PCIX0_MINGNT = %#04x\n", in8(PCIX0_MINGNT));
printf("PCIX0_MAXLTNCY = %#04x\n", in8(PCIX0_MAXLTNCY));
printf("PCIX0_BRDGOPT1 = %#010x\n", in32r(PCIX0_BRDGOPT1));
printf("PCIX0_BRDGOPT2 = %#010x\n", in32r(PCIX0_BRDGOPT2));
printf("PCIX0_BRDGOPT1 = %#010lx\n", in32r(PCIX0_BRDGOPT1));
printf("PCIX0_BRDGOPT2 = %#010lx\n", in32r(PCIX0_BRDGOPT2));
printf("PCIX0_POM0LAL = %#010x\n", in32r(PCIX0_POM0LAL));
printf("PCIX0_POM0LAH = %#010x\n", in32r(PCIX0_POM0LAH));
printf("PCIX0_POM0SA = %#010x\n", in32r(PCIX0_POM0SA));
printf("PCIX0_POM0PCILAL = %#010x\n", in32r(PCIX0_POM0PCIAL));
printf("PCIX0_POM0PCILAH = %#010x\n", in32r(PCIX0_POM0PCIAH));
printf("PCIX0_POM1LAL = %#010x\n", in32r(PCIX0_POM1LAL));
printf("PCIX0_POM1LAH = %#010x\n", in32r(PCIX0_POM1LAH));
printf("PCIX0_POM1SA = %#010x\n", in32r(PCIX0_POM1SA));
printf("PCIX0_POM1PCILAL = %#010x\n", in32r(PCIX0_POM1PCIAL));
printf("PCIX0_POM1PCILAH = %#010x\n", in32r(PCIX0_POM1PCIAH));
printf("PCIX0_POM2SA = %#010x\n", in32r(PCIX0_POM2SA));
printf("PCIX0_POM0LAL = %#010lx\n", in32r(PCIX0_POM0LAL));
printf("PCIX0_POM0LAH = %#010lx\n", in32r(PCIX0_POM0LAH));
printf("PCIX0_POM0SA = %#010lx\n", in32r(PCIX0_POM0SA));
printf("PCIX0_POM0PCILAL = %#010lx\n", in32r(PCIX0_POM0PCIAL));
printf("PCIX0_POM0PCILAH = %#010lx\n", in32r(PCIX0_POM0PCIAH));
printf("PCIX0_POM1LAL = %#010lx\n", in32r(PCIX0_POM1LAL));
printf("PCIX0_POM1LAH = %#010lx\n", in32r(PCIX0_POM1LAH));
printf("PCIX0_POM1SA = %#010lx\n", in32r(PCIX0_POM1SA));
printf("PCIX0_POM1PCILAL = %#010lx\n", in32r(PCIX0_POM1PCIAL));
printf("PCIX0_POM1PCILAH = %#010lx\n", in32r(PCIX0_POM1PCIAH));
printf("PCIX0_POM2SA = %#010lx\n", in32r(PCIX0_POM2SA));
printf("PCIX0_PIM0SA = %#010x\n", in32r(PCIX0_PIM0SA));
printf("PCIX0_PIM0LAL = %#010x\n", in32r(PCIX0_PIM0LAL));
printf("PCIX0_PIM0LAH = %#010x\n", in32r(PCIX0_PIM0LAH));
printf("PCIX0_PIM1SA = %#010x\n", in32r(PCIX0_PIM1SA));
printf("PCIX0_PIM1LAL = %#010x\n", in32r(PCIX0_PIM1LAL));
printf("PCIX0_PIM1LAH = %#010x\n", in32r(PCIX0_PIM1LAH));
printf("PCIX0_PIM2SA = %#010x\n", in32r(PCIX0_PIM1SA));
printf("PCIX0_PIM2LAL = %#010x\n", in32r(PCIX0_PIM1LAL));
printf("PCIX0_PIM2LAH = %#010x\n", in32r(PCIX0_PIM1LAH));
printf("PCIX0_PIM0SA = %#010lx\n", in32r(PCIX0_PIM0SA));
printf("PCIX0_PIM0LAL = %#010lx\n", in32r(PCIX0_PIM0LAL));
printf("PCIX0_PIM0LAH = %#010lx\n", in32r(PCIX0_PIM0LAH));
printf("PCIX0_PIM1SA = %#010lx\n", in32r(PCIX0_PIM1SA));
printf("PCIX0_PIM1LAL = %#010lx\n", in32r(PCIX0_PIM1LAL));
printf("PCIX0_PIM1LAH = %#010lx\n", in32r(PCIX0_PIM1LAH));
printf("PCIX0_PIM2SA = %#010lx\n", in32r(PCIX0_PIM1SA));
printf("PCIX0_PIM2LAL = %#010lx\n", in32r(PCIX0_PIM1LAL));
printf("PCIX0_PIM2LAH = %#010lx\n", in32r(PCIX0_PIM1LAH));
printf("PCIX0_XSTS = %#010x\n", in32r(PCIX0_STS));
printf("PCIX0_XSTS = %#010lx\n", in32r(PCIX0_STS));
}
int do_show_xbridge_info(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])

2
board/armadillo/flash.c
View File

@ -279,7 +279,7 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
int i, rc;
wp = (addr & ~1); /* get lower word aligned address */
printf ("Writing %d short data to 0x%p from 0x%p.\n ", cnt, wp, src);
printf ("Writing %lu short data to 0x%lx from 0x%p.\n ", cnt, wp, src);
/*
* handle unaligned start bytes

9
board/atmel/at91sam9260ek/at91sam9260ek.c
View File

@ -188,8 +188,17 @@ static void at91sam9260ek_macb_hw_init(void)
at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */
at91_set_B_periph(AT91_PIN_PA26, 0); /* ERX3 */
at91_set_B_periph(AT91_PIN_PA27, 0); /* ERXCK */
#if defined(CONFIG_AT91SAM9260EK)
/*
* use PA10, PA11 for ETX2, ETX3.
* PA23 and PA24 are for TWI EEPROM
*/
at91_set_B_periph(AT91_PIN_PA10, 0); /* ETX2 */
at91_set_B_periph(AT91_PIN_PA11, 0); /* ETX3 */
#else
at91_set_B_periph(AT91_PIN_PA23, 0); /* ETX2 */
at91_set_B_periph(AT91_PIN_PA24, 0); /* ETX3 */
#endif
at91_set_B_periph(AT91_PIN_PA22, 0); /* ETXER */
#endif

2
board/cobra5272/mii.c
View File

@ -200,7 +200,7 @@ int mii_discover_phy(struct eth_device *dev)
}
#endif /* CFG_DISCOVER_PHY */
int mii_init(void) __attribute__((weak,alias("__mii_init")));
void mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{

2
board/delta/nand.c
View File

@ -254,7 +254,7 @@ static unsigned long dfc_wait_event(unsigned long event)
break;
}
if(get_delta(start) > timeout) {
DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%x.\n", event);
DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%lx.\n", event);
return 0xff000000;
}

3
board/freescale/m5235evb/m5235evb.c
View File

@ -75,9 +75,11 @@ phys_size_t initdram(int board_type)
sdram->dacr0 =
SDRAMC_DARCn_BA(CFG_SDRAM_BASE) | SDRAMC_DARCn_CASL_C1 |
SDRAMC_DARCn_CBM_CMD20 | SDRAMC_DARCn_PS_32;
asm("nop");
/* Initialize DMR0 */
sdram->dmr0 = ((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V;
asm("nop");
/* Set IP (bit 3) in DACR */
sdram->dacr0 |= SDRAMC_DARCn_IP;
@ -100,6 +102,7 @@ phys_size_t initdram(int board_type)
/* Finish the configuration by issuing the MRS. */
sdram->dacr0 |= SDRAMC_DARCn_IMRS;
asm("nop");
/* Write to the SDRAM Mode Register */
*(u32 *) (CFG_SDRAM_BASE + 0x400) = 0xA5A59696;

2
board/freescale/m5275evb/Makefile
View File

@ -31,7 +31,7 @@ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): .depend $(OBJS)
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################

8
board/freescale/mpc7448hpc2/tsi108_init.c
View File

@ -165,8 +165,8 @@ int board_early_init_f (void)
printf ("Invalid DDR2 clock setting\n");
return -1;
}
printf ("BUS: %d MHz\n", get_board_bus_clk() / 1000000);
printf ("MEM: %d MHz\n", gd->mem_clk / 1000000);
printf ("BUS: %lu MHz\n", get_board_bus_clk() / 1000000);
printf ("MEM: %lu MHz\n", gd->mem_clk / 1000000);
return 0;
}
@ -622,8 +622,8 @@ int misc_init_r (void)
#ifdef CFG_L2
l2cache_enable ();
#endif
printf ("BUS: %d MHz\n", gd->bus_clk / 1000000);
printf ("MEM: %d MHz\n", gd->mem_clk / 1000000);
printf ("BUS: %lu MHz\n", gd->bus_clk / 1000000);
printf ("MEM: %lu MHz\n", gd->mem_clk / 1000000);
/*
* All the information needed to print the cache details is avaiblable

6
board/integratorcp/flash.c
View File

@ -393,7 +393,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
*addr = (FPW) 0x00D000D0;
} else {
#ifdef DEBUG
printf ("Timeout,0x%08x\n", status);
printf ("Timeout,0x%08lx\n", status);
#else
printf("Timeout\n");
#endif
@ -515,7 +515,7 @@ static int write_data (flash_info_t * info, ulong dest, FPW data)
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
return (2);
}
@ -542,7 +542,7 @@ static int write_data (flash_info_t * info, ulong dest, FPW data)
#ifdef DEBUG
*addr = (FPW) 0x00700070;
status = *addr;
printf("## status=0x%08x, addr=0x%08x\n", status, addr);
printf("## status=0x%08lx, addr=0x%p\n", status, addr);
#endif
*addr = (FPW) 0x00500050; /* clear status register cmd */
*addr = (FPW) 0x00FF00FF; /* restore read mode */

2
board/mp2usb/flash.c
View File

@ -426,7 +426,7 @@ static int write_data (flash_info_t *info, ulong dest, FPW data)
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
printf ("not erased at %08lx (%lx)\n", (ulong) addr, (ulong) *addr);
return (2);
}
/*

2
board/netstal/hcu5/sdram.c
View File

@ -71,7 +71,7 @@ void board_add_ram_info(int use_default)
}
get_sys_info(&board_cfg);
printf(", %d MHz", (board_cfg.freqPLB * 2) / 1000000);
printf(", %lu MHz", (board_cfg.freqPLB * 2) / 1000000);
mfsdram(DDR0_03, val);
val = DDR0_03_CASLAT_DECODE(val);

2
board/sandburst/metrobox/metrobox.c
View File

@ -282,7 +282,7 @@ int checkboard (void)
}
printf ("OptoFPGA ID:\t0x%02X\tRev: 0x%02X\n", opto_id, opto_rev);
printf ("Board Rev:\t0x%02X\tID: %s\n", brd_rev, (char *)board_id_as[brd_id]);
printf ("Board Rev:\t0x%02X\tID: %s\n", brd_rev, board_id_as[brd_id].name);
/* Fix the ack in the bme 32 */
udelay(5000);

2
board/versatile/flash.c
View File

@ -476,7 +476,7 @@ static int write_data (flash_info_t * info, ulong dest, FPW data)
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
printf ("not erased at %08lx (%lx)\n", (ulong) addr, (ulong) *addr);
return (2);
}

2
board/zylonite/nand.c
View File

@ -254,7 +254,7 @@ static unsigned long dfc_wait_event(unsigned long event)
break;
}
if(get_delta(start) > timeout) {
DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%x.\n", event);
DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%lx.\n", event);
return 0xff000000;
}

3
common/cmd_nvedit.c
View File

@ -99,7 +99,8 @@ int do_printenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
}
printf("\nEnvironment size: %d/%d bytes\n", i, ENV_SIZE);
printf("\nEnvironment size: %d/%ld bytes\n",
i, (ulong)ENV_SIZE);
return 0;
}

4
common/cmd_onenand.c
View File

@ -70,14 +70,14 @@ int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
if (!end || end < 0)
end = start;
printf("Erase block from %d to %d\n", start, end);
printf("Erase block from %lu to %lu\n", start, end);
for (block = start; block <= end; block++) {
instr.addr = block << onenand_chip.erase_shift;
instr.len = 1 << onenand_chip.erase_shift;
ret = onenand_erase(&onenand_mtd, &instr);
if (ret) {
printf("erase failed %d\n", block);
printf("erase failed %lu\n", block);
break;
}
}

2
common/env_onenand.c
View File

@ -103,7 +103,7 @@ int saveenv(void)
instr.addr = env_addr;
instr.addr -= (unsigned long)onenand_chip.base;
if (onenand_erase(&onenand_mtd, &instr)) {
printf("OneNAND: erase failed at 0x%08x\n", env_addr);
printf("OneNAND: erase failed at 0x%08lx\n", env_addr);
return 1;
}

16
common/image.c
View File

@ -827,13 +827,13 @@ int boot_get_ramdisk (int argc, char *argv[], bootm_headers_t *images,
cfg_noffset = fit_conf_get_node (fit_hdr, fit_uname_config);
if (cfg_noffset < 0) {
debug ("* ramdisk: no such config\n");
return 0;
return 1;
}
rd_noffset = fit_conf_get_ramdisk_node (fit_hdr, cfg_noffset);
if (rd_noffset < 0) {
debug ("* ramdisk: no ramdisk in config\n");
return 0;
return 1;
}
}
#endif
@ -872,7 +872,7 @@ int boot_get_ramdisk (int argc, char *argv[], bootm_headers_t *images,
if (!fit_check_format (fit_hdr)) {
puts ("Bad FIT ramdisk image format!\n");
show_boot_progress (-120);
return 0;
return 1;
}
show_boot_progress (121);
@ -887,7 +887,7 @@ int boot_get_ramdisk (int argc, char *argv[], bootm_headers_t *images,
if (cfg_noffset < 0) {
puts ("Could not find configuration node\n");
show_boot_progress (-122);
return 0;
return 1;
}
fit_uname_config = fdt_get_name (fit_hdr, cfg_noffset, NULL);
printf (" Using '%s' configuration\n", fit_uname_config);
@ -902,20 +902,20 @@ int boot_get_ramdisk (int argc, char *argv[], bootm_headers_t *images,
if (rd_noffset < 0) {
puts ("Could not find subimage node\n");
show_boot_progress (-124);
return 0;
return 1;
}
printf (" Trying '%s' ramdisk subimage\n", fit_uname_ramdisk);
show_boot_progress (125);
if (!fit_check_ramdisk (fit_hdr, rd_noffset, arch, images->verify))
return 0;
return 1;
/* get ramdisk image data address and length */
if (fit_image_get_data (fit_hdr, rd_noffset, &data, &size)) {
puts ("Could not find ramdisk subimage data!\n");
show_boot_progress (-127);
return 0;
return 1;
}
show_boot_progress (128);
@ -925,7 +925,7 @@ int boot_get_ramdisk (int argc, char *argv[], bootm_headers_t *images,
if (fit_image_get_load (fit_hdr, rd_noffset, &rd_load)) {
puts ("Can't get ramdisk subimage load address!\n");
show_boot_progress (-129);
return 0;
return 1;
}
show_boot_progress (129);

51
cpu/arm926ejs/cpu.c
View File

@ -134,25 +134,52 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return (0);
}
void icache_enable (void)
/* cache_bit must be either C1_IC or C1_DC */
static void cache_enable(uint32_t cache_bit)
{
ulong reg;
uint32_t reg;
reg = read_p15_c1 (); /* get control reg. */
cp_delay ();
write_p15_c1 (reg | C1_IC);
reg = read_p15_c1(); /* get control reg. */
cp_delay();
write_p15_c1(reg | cache_bit);
}
void icache_disable (void)
/* cache_bit must be either C1_IC or C1_DC */
static void cache_disable(uint32_t cache_bit)
{
ulong reg;
uint32_t reg;
reg = read_p15_c1 ();
cp_delay ();
write_p15_c1 (reg & ~C1_IC);
reg = read_p15_c1();
cp_delay();
write_p15_c1(reg & ~cache_bit);
}
int icache_status (void)
void icache_enable(void)
{
return (read_p15_c1 () & C1_IC) != 0;
cache_enable(C1_IC);
}
void icache_disable(void)
{
cache_disable(C1_IC);
}
int icache_status(void)
{
return (read_p15_c1() & C1_IC) != 0;
}
void dcache_enable(void)
{
cache_enable(C1_DC);
}
void dcache_disable(void)
{
cache_disable(C1_DC);
}
int dcache_status(void)
{
return (read_p15_c1() & C1_DC) != 0;
}

2
cpu/mcf5227x/cpu_init.c
View File

@ -106,7 +106,7 @@ void cpu_init_f(void)
*/
int cpu_init_r(void)
{
#ifdef CONFIG_MCFTMR
#ifdef CONFIG_MCFRTC
volatile rtc_t *rtc = (volatile rtc_t *)(CFG_MCFRTC_BASE);
volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended;
u32 oscillator = CFG_RTC_OSCILLATOR;

12
cpu/mcf52x2/cpu_init.c
View File

@ -419,8 +419,7 @@ void cpu_init_f(void)
else is doing it! */
#if defined(CFG_CS0_BASE) & defined(CFG_CS0_SIZE) & \
defined(CFG_CS0_WIDTH) & defined(CFG_CS0_RO) & \
defined(CFG_CS0_WS)
defined(CFG_CS0_WIDTH) & defined(CFG_CS0_WS)
MCFCSM_CSAR0 = (CFG_CS0_BASE >> 16) & 0xFFFF;
@ -447,8 +446,7 @@ void cpu_init_f(void)
#endif
#if defined(CFG_CS1_BASE) & defined(CFG_CS1_SIZE) & \
defined(CFG_CS1_WIDTH) & defined(CFG_CS1_RO) & \
defined(CFG_CS1_WS)
defined(CFG_CS1_WIDTH) & defined(CFG_CS1_WS)
MCFCSM_CSAR1 = (CFG_CS1_BASE >> 16) & 0xFFFF;
@ -476,8 +474,7 @@ void cpu_init_f(void)
#endif
#if defined(CFG_CS2_BASE) & defined(CFG_CS2_SIZE) & \
defined(CFG_CS2_WIDTH) & defined(CFG_CS2_RO) & \
defined(CFG_CS2_WS)
defined(CFG_CS2_WIDTH) & defined(CFG_CS2_WS)
MCFCSM_CSAR2 = (CFG_CS2_BASE >> 16) & 0xFFFF;
@ -505,8 +502,7 @@ void cpu_init_f(void)
#endif
#if defined(CFG_CS3_BASE) & defined(CFG_CS3_SIZE) & \
defined(CFG_CS3_WIDTH) & defined(CFG_CS3_RO) & \
defined(CFG_CS3_WS)
defined(CFG_CS3_WIDTH) & defined(CFG_CS3_WS)
MCFCSM_CSAR3 = (CFG_CS3_BASE >> 16) & 0xFFFF;

2
cpu/mcf52x2/speed.c
View File

@ -69,7 +69,7 @@ int get_clocks (void)
/* Setup PLL */
pll->syncr = 0x01080000;
while (!(pll->synsr & FMPLL_SYNSR_LOCK)
while (!(pll->synsr & FMPLL_SYNSR_LOCK))
;
pll->syncr = 0x01000000;
while (!(pll->synsr & FMPLL_SYNSR_LOCK))

6
cpu/mcf5445x/config.mk
View File

@ -29,3 +29,9 @@ PLATFORM_CPPFLAGS += -mcpu=54455 -fPIC
else
PLATFORM_CPPFLAGS += -m5407 -fPIC
endif
ifneq (,$(findstring -linux-,$(shell $(CC) --version)))
ifneq (,$(findstring GOT,$(shell $(LD) --help)))
PLATFORM_LDFLAGS += --got=single
endif
endif

2
cpu/mcf5445x/cpu_init.c
View File

@ -110,7 +110,7 @@ void cpu_init_f(void)
*/
int cpu_init_r(void)
{
#ifdef CONFIG_MCFTMR
#ifdef CONFIG_MCFRTC
volatile rtc_t *rtc = (volatile rtc_t *)(CFG_MCFRTC_BASE);
volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended;

2
cpu/mcf5445x/start.S
View File

@ -253,7 +253,7 @@ clear_bss:
/* exception code */
.globl _fault
_fault:
jmp _fault
bra _fault
.globl _exc_handler
_exc_handler:

6
cpu/mcf547x_8x/config.mk
View File

@ -29,3 +29,9 @@ PLATFORM_CPPFLAGS += -mcpu=5485 -fPIC
else
PLATFORM_CPPFLAGS += -m5407 -fPIC
endif
ifneq (,$(findstring -linux-,$(shell $(CC) --version)))
ifneq (,$(findstring GOT,$(shell $(LD) --help)))
PLATFORM_LDFLAGS += --got=single
endif
endif

2
cpu/mcf547x_8x/start.S
View File

@ -259,7 +259,7 @@ clear_bss:
/* exception code */
.globl _fault
_fault:
jmp _fault
bra _fault
.globl _exc_handler
_exc_handler:

6
cpu/ppc4xx/4xx_pcie.c
View File

@ -25,11 +25,11 @@
#define DEBUG
#endif
#include <asm/processor.h>
#include <asm-ppc/io.h>
#include <ppc4xx.h>
#include <common.h>
#include <pci.h>
#include <ppc4xx.h>
#include <asm/processor.h>
#include <asm-ppc/io.h>
#if (defined(CONFIG_440SPE) || defined(CONFIG_405EX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \

6
cpu/pxa/mmc.c
View File

@ -535,8 +535,10 @@ static void mmc_decode_csd(uint32_t * resp)
mmc_dev.removable = 0;
mmc_dev.block_read = mmc_bread;
printf("Detected: %u blocks of %u bytes (%uMB) ", mmc_dev.lba,
mmc_dev.blksz, mmc_dev.lba * mmc_dev.blksz / (1024 * 1024));
printf("Detected: %lu blocks of %lu bytes (%luMB) ",
mmc_dev.lba,
mmc_dev.blksz,
mmc_dev.lba * mmc_dev.blksz / (1024 * 1024));
}
int

12
drivers/hwmon/Makefile
View File

@ -30,13 +30,13 @@ include $(TOPDIR)/config.mk
LIB = $(obj)libhwmon.a
COBJS-y += adm1021.o
COBJS-y += ds1621.o
COBJS-y += ds1722.o
COBJS-y += ds1775.o
COBJS-$(CONFIG_DTT_ADM1021) += adm1021.o
COBJS-$(CONFIG_DTT_DS1621) += ds1621.o
COBJS-$(CONFIG_DTT_DS1722) += ds1722.o
COBJS-$(CONFIG_DTT_DS1775) += ds1775.o
COBJS-$(CONFIG_DTT_LM73) += lm73.o
COBJS-y += lm75.o
COBJS-y += lm81.o
COBJS-$(CONFIG_DTT_LM75) += lm75.o
COBJS-$(CONFIG_DTT_LM81) += lm81.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)

35
drivers/hwmon/adm1021.c
View File

@ -33,11 +33,40 @@
#include <common.h>
#ifdef CONFIG_DTT_ADM1021
#include <i2c.h>
#include <dtt.h>
#define DTT_READ_LOC_VALUE 0x00
#define DTT_READ_REM_VALUE 0x01
#define DTT_READ_STATUS 0x02
#define DTT_READ_CONFIG 0x03
#define DTT_READ_CONVRATE 0x04
#define DTT_READ_LOC_HIGHLIM 0x05
#define DTT_READ_LOC_LOWLIM 0x06
#define DTT_READ_REM_HIGHLIM 0x07
#define DTT_READ_REM_LOWLIM 0x08
#define DTT_READ_DEVID 0xfe
#define DTT_WRITE_CONFIG 0x09
#define DTT_WRITE_CONVRATE 0x0a
#define DTT_WRITE_LOC_HIGHLIM 0x0b
#define DTT_WRITE_LOC_LOWLIM 0x0c
#define DTT_WRITE_REM_HIGHLIM 0x0d
#define DTT_WRITE_REM_LOWLIM 0x0e
#define DTT_WRITE_ONESHOT 0x0f
#define DTT_STATUS_BUSY 0x80 /* 1=ADC Converting */
#define DTT_STATUS_LHIGH 0x40 /* 1=Local High Temp Limit Tripped */
#define DTT_STATUS_LLOW 0x20 /* 1=Local Low Temp Limit Tripped */
#define DTT_STATUS_RHIGH 0x10 /* 1=Remote High Temp Limit Tripped */
#define DTT_STATUS_RLOW 0x08 /* 1=Remote Low Temp Limit Tripped */
#define DTT_STATUS_OPEN 0x04 /* 1=Remote Sensor Open-Circuit */
#define DTT_CONFIG_ALERT_MASKED 0x80 /* 0=ALERT Enabled, 1=ALERT Masked */
#define DTT_CONFIG_STANDBY 0x40 /* 0=Run, 1=Standby */
#define DTT_ADM1021_DEVID 0x41
typedef
struct {
uint i2c_addr:7; /* 7bit i2c chip address */
@ -170,5 +199,3 @@ dtt_get_temp (int sensor)
return (int) val;
} /* dtt_get_temp() */
#endif /* CONFIG_DTT_ADM1021 */

12
drivers/hwmon/ds1621.c
View File

@ -27,7 +27,6 @@
#include <common.h>
#ifdef CONFIG_DTT_DS1621
#if !defined(CFG_EEPROM_PAGE_WRITE_ENABLE) || \
(CFG_EEPROM_PAGE_WRITE_BITS < 1)
# error "CFG_EEPROM_PAGE_WRITE_ENABLE must be defined and CFG_EEPROM_PAGE_WRITE_BITS must be greater than 1 to use CONFIG_DTT_DS1621"
@ -39,6 +38,14 @@
* Device code
*/
#define DTT_I2C_DEV_CODE 0x48 /* Dallas Semi's DS1621 */
#define DTT_READ_TEMP 0xAA
#define DTT_READ_COUNTER 0xA8
#define DTT_READ_SLOPE 0xA9
#define DTT_WRITE_START_CONV 0xEE
#define DTT_WRITE_STOP_CONV 0x22
#define DTT_TEMP_HIGH 0xA1
#define DTT_TEMP_LOW 0xA2
#define DTT_CONFIG 0xAC
int dtt_read(int sensor, int reg)
{
@ -185,6 +192,3 @@ int dtt_get_temp(int sensor)
return (dtt_read(sensor, DTT_READ_TEMP) / 256);
} /* dtt_get_temp() */
#endif /* CONFIG_DTT_DS1621 */

5
drivers/hwmon/ds1722.c
View File

@ -1,8 +1,5 @@
#include <common.h>
#ifdef CONFIG_DS1722
#include <ssi.h>
static void ds1722_select(int dev)
@ -138,5 +135,3 @@ int ds1722_probe(int dev)
printf("%d.%d deg C\n\n", (char)(temp >> 8), temp & 0xff);
return 0;
}
#endif

8
drivers/hwmon/ds1775.c
View File

@ -21,11 +21,14 @@
#include <common.h>
#ifdef CONFIG_DTT_DS1775
#include <i2c.h>
#include <dtt.h>
#define DTT_I2C_DEV_CODE CFG_I2C_DTT_ADDR /* Dallas Semi's DS1775 device code */
#define DTT_READ_TEMP 0x0
#define DTT_CONFIG 0x1
#define DTT_TEMP_HYST 0x2
#define DTT_TEMP_OS 0x3
int dtt_read(int sensor, int reg)
{
@ -151,6 +154,3 @@ int dtt_get_temp(int sensor)
{
return (dtt_read(sensor, DTT_READ_TEMP) / 256);
}
#endif /* CONFIG_DTT_DS1775 */

6
drivers/hwmon/lm73.c
View File

@ -38,6 +38,12 @@
* Device code
*/
#define DTT_I2C_DEV_CODE 0x48 /* National Semi's LM73 device */
#define DTT_READ_TEMP 0x0
#define DTT_CONFIG 0x1
#define DTT_TEMP_HIGH 0x2
#define DTT_TEMP_LOW 0x3
#define DTT_CONTROL 0x4
#define DTT_ID 0x7
int dtt_read(int const sensor, int const reg)
{

8
drivers/hwmon/lm75.c
View File

@ -27,7 +27,6 @@
#include <common.h>
#ifdef CONFIG_DTT_LM75
#if !defined(CFG_EEPROM_PAGE_WRITE_ENABLE) || \
(CFG_EEPROM_PAGE_WRITE_BITS < 1)
# error "CFG_EEPROM_PAGE_WRITE_ENABLE must be defined and CFG_EEPROM_PAGE_WRITE_BITS must be greater than 1 to use CONFIG_DTT_LM75"
@ -36,11 +35,14 @@
#include <i2c.h>
#include <dtt.h>
/*
* Device code
*/
#define DTT_I2C_DEV_CODE 0x48 /* ON Semi's LM75 device */
#define DTT_READ_TEMP 0x0
#define DTT_CONFIG 0x1
#define DTT_TEMP_HYST 0x2
#define DTT_TEMP_SET 0x3
int dtt_read(int sensor, int reg)
{
@ -200,5 +202,3 @@ int dtt_get_temp(int sensor)
}
return (int)((int16_t) ret / 256);
} /* dtt_get_temp() */
#endif /* CONFIG_DTT_LM75 */

8
drivers/hwmon/lm81.c
View File

@ -32,7 +32,6 @@
#include <common.h>
#ifdef CONFIG_DTT_LM81
#if !defined(CFG_EEPROM_PAGE_WRITE_ENABLE) || \
(CFG_EEPROM_PAGE_WRITE_BITS < 1)
# error "CFG_EEPROM_PAGE_WRITE_ENABLE must be defined and CFG_EEPROM_PAGE_WRITE_BITS must be greater than 1 to use CONFIG_DTT_LM81"
@ -45,6 +44,11 @@
* Device code
*/
#define DTT_I2C_DEV_CODE 0x2c /* ON Semi's LM81 device */
#define DTT_READ_TEMP 0x27
#define DTT_CONFIG_TEMP 0x4b
#define DTT_TEMP_MAX 0x39
#define DTT_TEMP_HYST 0x3a
#define DTT_CONFIG 0x40
int dtt_read(int sensor, int reg)
{
@ -144,5 +148,3 @@ int dtt_get_temp(int sensor)
return (TEMP_FROM_REG((val << 1) + ((tmpcnf & 0x80) >> 7))) / 10;
} /* dtt_get_temp() */
#endif /* CONFIG_DTT_LM81 */

16
drivers/mtd/dataflash.c
View File

@ -54,6 +54,17 @@ int AT91F_DataflashInit (void)
&dataflash_info[i].Desc);
switch (dfcode) {
case AT45DB021:
dataflash_info[i].Device.pages_number = 1024;
dataflash_info[i].Device.pages_size = 263;
dataflash_info[i].Device.page_offset = 9;
dataflash_info[i].Device.byte_mask = 0x300;
dataflash_info[i].Device.cs = cs[i].cs;
dataflash_info[i].Desc.DataFlash_state = IDLE;
dataflash_info[i].logical_address = cs[i].addr;
dataflash_info[i].id = dfcode;
found[i] += dfcode;;
break;
case AT45DB161:
dataflash_info[i].Device.pages_number = 4096;
dataflash_info[i].Device.pages_size = 528;
@ -162,7 +173,7 @@ void AT91F_DataflashSetEnv (void)
if((env & FLAG_SETENV) == FLAG_SETENV) {
start =
dataflash_info[i].Device.area_list[j].start;
sprintf((char*) s,"%X",start);
sprintf((char*) s,"%lX",start);
setenv((char*) area_list[part].label,(char*) s);
}
part++;
@ -178,6 +189,9 @@ void dataflash_print_info (void)
if (dataflash_info[i].id != 0) {
printf("DataFlash:");
switch (dataflash_info[i].id) {
case AT45DB021:
printf("AT45DB021\n");
break;
case AT45DB161:
printf("AT45DB161\n");
break;

4
drivers/net/smc911x.c
View File

@ -597,7 +597,7 @@ int eth_init(bd_t *bd)
val = reg_read(BYTE_TEST);
if (val != 0x87654321) {
printf(DRIVERNAME ": Invalid chip endian 0x%08x\n", val);
printf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val);
goto err_out;
}
@ -606,7 +606,7 @@ int eth_init(bd_t *bd)
if (chip_ids[i].id == val) break;
}
if (!chip_ids[i].id) {
printf(DRIVERNAME ": Unknown chip ID %04x\n", val);
printf(DRIVERNAME ": Unknown chip ID %04lx\n", val);
goto err_out;
}

4
drivers/net/tsi108_eth.c
View File

@ -899,7 +899,7 @@ static int tsi108_eth_send (struct eth_device *dev,
status = le32_to_cpu(tx_descr->config_status);
if ((status & DMA_DESCR_TX_OK) == 0) {
#ifdef TX_PRINT_ERRORS
printf ("TX packet error: 0x%08x\n %s%s%s%s\n", status,
printf ("TX packet error: 0x%08lx\n %s%s%s%s\n", status,
status & DMA_DESCR_TX_OK ? "tx error, " : "",
status & DMA_DESCR_TX_RETRY_LIMIT ?
"retry limit reached, " : "",
@ -959,7 +959,7 @@ static int tsi108_eth_recv (struct eth_device *dev)
status = le32_to_cpu(rx_descr->config_status);
if (status & DMA_DESCR_RX_BAD_FRAME) {
#ifdef RX_PRINT_ERRORS
printf ("RX packet error: 0x%08x\n %s%s%s%s%s%s\n",
printf ("RX packet error: 0x%08lx\n %s%s%s%s%s%s\n",
status,
status & DMA_DESCR_RX_FRAME_IS_TYPE ? "too big, "
: "",

4
drivers/serial/mcfuart.c
View File

@ -63,8 +63,8 @@ int serial_init(void)
uart->umr = UART_UMR_SB_STOP_BITS_1;
/* Setting up BaudRate */
counter = (u32) (gd->bus_clk / (gd->baudrate));
counter >>= 5;
counter = (u32) ((gd->bus_clk / 32) + (gd->baudrate / 2));
counter = counter / gd->baudrate;
/* write to CTUR: divide counter upper byte */
uart->ubg1 = (u8) ((counter & 0xff00) >> 8);

11
drivers/serial/serial.c
View File

@ -124,6 +124,8 @@ static NS16550_t serial_ports[4] = {
static int calc_divisor (NS16550_t port)
{
uint32_t clk_divisor;
#ifdef CONFIG_OMAP1510
/* If can't cleanly clock 115200 set div to 1 */
if ((CFG_NS16550_CLK == 12000000) && (gd->baudrate == 115200)) {
@ -147,10 +149,15 @@ static int calc_divisor (NS16550_t port)
/* Compute divisor value. Normally, we should simply return:
* CFG_NS16550_CLK) / MODE_X_DIV / gd->baudrate
* but we need to round that value by adding 0.5 or 8/16.
* but we need to round that value by adding 0.5 (2/4).
* Rounding is especially important at high baud rates.
*/
return (((16 * CFG_NS16550_CLK) / MODE_X_DIV / gd->baudrate) + 8) / 16;
clk_divisor = (((4 * CFG_NS16550_CLK) /
(MODE_X_DIV * gd->baudrate)) + 2) / 4;
debug("NS16550 clock divisor = %d\n", clk_divisor);
return clk_divisor;
}
#if !defined(CONFIG_SERIAL_MULTI)

37
drivers/serial/serial_xuartlite.c
View File

@ -1,6 +1,8 @@
/*
* (C) Copyright 2004 Atmark Techno, Inc.
* (C) Copyright 2008 Michal Simek <monstr@monstr.eu>
* Clean driver and add xilinx constant from header file
*
* (C) Copyright 2004 Atmark Techno, Inc.
* Yasushi SHOJI <yashi@atmark-techno.com>
*
* See file CREDITS for list of people who contributed to this
@ -13,7 +15,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@ -23,19 +25,21 @@
*/
#include <config.h>
#include <asm/io.h>
#ifdef CONFIG_XILINX_UARTLITE
#include <asm/serial_xuartlite.h>
#define RX_FIFO_OFFSET 0 /* receive FIFO, read only */
#define TX_FIFO_OFFSET 4 /* transmit FIFO, write only */
#define STATUS_REG_OFFSET 8 /* status register, read only */
/* FIXME: we should convert these to in32 and out32 */
#define IO_WORD(offset) (*(volatile unsigned long *)(offset))
#define IO_SERIAL(offset) IO_WORD(CONFIG_SERIAL_BASE + (offset))
#define SR_TX_FIFO_FULL 0x08 /* transmit FIFO full */
#define SR_RX_FIFO_VALID_DATA 0x01 /* data in receive FIFO */
#define SR_RX_FIFO_FULL 0x02 /* receive FIFO full */
#define IO_SERIAL_RX_FIFO IO_SERIAL(XUL_RX_FIFO_OFFSET)
#define IO_SERIAL_TX_FIFO IO_SERIAL(XUL_TX_FIFO_OFFSET)
#define IO_SERIAL_STATUS IO_SERIAL(XUL_STATUS_REG_OFFSET)
#define IO_SERIAL_CONTROL IO_SERIAL(XUL_CONTROL_REG_OFFSET)
#define UARTLITE_STATUS (CONFIG_SERIAL_BASE + STATUS_REG_OFFSET)
#define UARTLITE_TX_FIFO (CONFIG_SERIAL_BASE + TX_FIFO_OFFSET)
#define UARTLITE_RX_FIFO (CONFIG_SERIAL_BASE + RX_FIFO_OFFSET)
int serial_init(void)
{
@ -50,9 +54,10 @@ void serial_setbrg(void)
void serial_putc(const char c)
{
if (c == '\n') serial_putc('\r');
while (IO_SERIAL_STATUS & XUL_SR_TX_FIFO_FULL);
IO_SERIAL_TX_FIFO = (unsigned char) (c & 0xff);
if (c == '\n')
serial_putc('\r');
while (in_be32(UARTLITE_STATUS) & SR_TX_FIFO_FULL);
out_be32(UARTLITE_TX_FIFO, (unsigned char) (c & 0xff));
}
void serial_puts(const char * s)
@ -64,13 +69,13 @@ void serial_puts(const char * s)
int serial_getc(void)
{
while (!(IO_SERIAL_STATUS & XUL_SR_RX_FIFO_VALID_DATA));
return IO_SERIAL_RX_FIFO & 0xff;
while (!(in_be32(UARTLITE_STATUS) & SR_RX_FIFO_VALID_DATA));
return in_be32(UARTLITE_RX_FIFO) & 0xff;
}
int serial_tstc(void)
{
return (IO_SERIAL_STATUS & XUL_SR_RX_FIFO_VALID_DATA);
return (in_be32(UARTLITE_STATUS) & SR_RX_FIFO_VALID_DATA);
}
#endif /* CONFIG_MICROBLZE */

16
drivers/usb/usbdcore.c
View File

@ -546,21 +546,23 @@ void urb_append (urb_link * hd, struct urb *urb)
*
* NOTE: endpoint_address MUST contain a direction flag.
*/
struct urb *usbd_alloc_urb (struct usb_device_instance *device, struct usb_endpoint_instance *endpoint)
struct urb *usbd_alloc_urb (struct usb_device_instance *device,
struct usb_endpoint_instance *endpoint)
{
struct urb *urb;
if( !(urb = (struct urb*)malloc(sizeof(struct urb))) ) {
usberr(" F A T A L: malloc(%u) FAILED!!!!", sizeof(struct urb));
return NULL;
if (!(urb = (struct urb *) malloc (sizeof (struct urb)))) {
usberr (" F A T A L: malloc(%u) FAILED!!!!",
sizeof (struct urb));
return NULL;
}
/* Fill in known fields */
memset(urb, 0, sizeof(struct urb));
memset (urb, 0, sizeof (struct urb));
urb->endpoint = endpoint;
urb->device = device;
urb->buffer = (u8*)urb->buffer_data;
urb->buffer_length = sizeof(urb->buffer_data);
urb->buffer = (u8 *) urb->buffer_data;
urb->buffer_length = sizeof (urb->buffer_data);
urb_link_init (&urb->link);

2
drivers/video/mb862xx.c
View File

@ -173,6 +173,8 @@ static void de_init (void)
DE_WR_FIFO (0x09410000);
DE_WR_FIFO (0x00000000);
DE_WR_FIFO (pGD->winSizeY<<16 | pGD->winSizeX);
/* sync with SW access to framebuffer */
de_wait ();
}
#if defined(CONFIG_VIDEO_CORALP)

4
fs/jffs2/jffs2_1pass.c
View File

@ -1213,12 +1213,12 @@ jffs2_1pass_build_lists(struct part_info * part)
} else if (node->nodetype == JFFS2_NODETYPE_CLEANMARKER) {
if (node->totlen != sizeof(struct jffs2_unknown_node))
printf("OOPS Cleanmarker has bad size "
"%d != %d\n", node->totlen,
"%d != %u\n", node->totlen,
sizeof(struct jffs2_unknown_node));
} else if (node->nodetype == JFFS2_NODETYPE_PADDING) {
if (node->totlen < sizeof(struct jffs2_unknown_node))
printf("OOPS Padding has bad size "
"%d < %d\n", node->totlen,
"%d < %u\n", node->totlen,
sizeof(struct jffs2_unknown_node));
} else {
printf("Unknown node type: %x len %d "

2
include/asm-m68k/timer.h
View File

@ -33,7 +33,7 @@
/****************************************************************************/
/* DMA Timer module registers */
typedef struct dtimer_ctrl {
#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5272)
u16 tmr; /* 0x00 Mode register */
u16 res1; /* 0x02 */
u16 trr; /* 0x04 Reference register */

301
include/asm-microblaze/arch-microblaze/xbasic_types.h
View File

@ -1,301 +0,0 @@
/******************************************************************************
*
* Author: Xilinx, Inc.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE.
*
*
* Xilinx hardware products are not intended for use in life support
* appliances, devices, or systems. Use in such applications is
* expressly prohibited.
*
*
* (c) Copyright 2002-2003 Xilinx Inc.
* All rights reserved.
*
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xbasic_types.h
*
* This file contains basic types for Xilinx software IP. These types do not
* follow the standard naming convention with respect to using the component
* name in front of each name because they are considered to be primitives.
*
* @note
*
* This file contains items which are architecture dependent.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a rmm 12/14/01 First release
* rmm 05/09/03 Added "xassert always" macros to rid ourselves of diab
* compiler warnings
* </pre>
*
******************************************************************************/
#ifndef XBASIC_TYPES_H /* prevent circular inclusions */
#define XBASIC_TYPES_H /* by using protection macros */
/***************************** Include Files *********************************/
/************************** Constant Definitions *****************************/
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
#ifndef NULL
#define NULL 0
#endif
/** Null */
#define XCOMPONENT_IS_READY 0x11111111 /* component has been initialized */
#define XCOMPONENT_IS_STARTED 0x22222222 /* component has been started */
/* the following constants and declarations are for unit test purposes and are
* designed to be used in test applications.
*/
#define XTEST_PASSED 0
#define XTEST_FAILED 1
#define XASSERT_NONE 0
#define XASSERT_OCCURRED 1
extern unsigned int XAssertStatus;
extern void XAssert(char *, int);
/**************************** Type Definitions *******************************/
/** @name Primitive types
* These primitive types are created for transportability.
* They are dependent upon the target architecture.
* @{
*/
#include <linux/types.h>
typedef struct {
u32 Upper;
u32 Lower;
} Xuint64;
/* Xilinx's unsigned integer types */
typedef u32 Xuint32;
typedef u16 Xuint16;
typedef u8 Xuint8;
/* and signed integer types */
typedef s32 Xint32;
typedef s16 Xint16;
typedef s8 Xint8;
#ifndef NULL
#define NULL 0
#endif
typedef unsigned long Xboolean;
#define XNULL NULL
#define XTRUE 1
#define XFALSE 0
/*@}*/
/**
* This data type defines an interrupt handler for a device.
* The argument points to the instance of the component
*/
typedef void (*XInterruptHandler) (void *InstancePtr);
/**
* This data type defines a callback to be invoked when an
* assert occurs. The callback is invoked only when asserts are enabled
*/
typedef void (*XAssertCallback) (char *FilenamePtr, int LineNumber);
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
* Return the most significant half of the 64 bit data type.
*
* @param x is the 64 bit word.
*
* @return
*
* The upper 32 bits of the 64 bit word.
*
* @note
*
* None.
*
******************************************************************************/
#define XUINT64_MSW(x) ((x).Upper)
/*****************************************************************************/
/**
* Return the least significant half of the 64 bit data type.
*
* @param x is the 64 bit word.
*
* @return
*
* The lower 32 bits of the 64 bit word.
*
* @note
*
* None.
*
******************************************************************************/
#define XUINT64_LSW(x) ((x).Lower)
#ifndef NDEBUG
/*****************************************************************************/
/**
* This assert macro is to be used for functions that do not return anything
* (void). This in conjunction with the XWaitInAssert boolean can be used to
* accomodate tests so that asserts which fail allow execution to continue.
*
* @param expression is the expression to evaluate. If it evaluates to false,
* the assert occurs.
*
* @return
*
* Returns void unless the XWaitInAssert variable is true, in which case
* no return is made and an infinite loop is entered.
*
* @note
*
* None.
*
******************************************************************************/
#define XASSERT_VOID(expression) \
{ \
if (expression) { \
XAssertStatus = XASSERT_NONE; \
} else { \
XAssert(__FILE__, __LINE__); \
XAssertStatus = XASSERT_OCCURRED; \
return; \
} \
}
/*****************************************************************************/
/**
* This assert macro is to be used for functions that do return a value. This in
* conjunction with the XWaitInAssert boolean can be used to accomodate tests so
* that asserts which fail allow execution to continue.
*
* @param expression is the expression to evaluate. If it evaluates to false,
* the assert occurs.
*
* @return
*
* Returns 0 unless the XWaitInAssert variable is true, in which case
* no return is made and an infinite loop is entered.
*
* @note
*
* None.
*
******************************************************************************/
#define XASSERT_NONVOID(expression) \
{ \
if (expression) { \
XAssertStatus = XASSERT_NONE; \
} else { \
XAssert(__FILE__, __LINE__); \
XAssertStatus = XASSERT_OCCURRED; \
return 0; \
} \
}
/*****************************************************************************/
/**
* Always assert. This assert macro is to be used for functions that do not
* return anything (void). Use for instances where an assert should always
* occur.
*
* @return
*
* Returns void unless the XWaitInAssert variable is true, in which case
* no return is made and an infinite loop is entered.
*
* @note
*
* None.
*
******************************************************************************/
#define XASSERT_VOID_ALWAYS() \
{ \
XAssert(__FILE__, __LINE__); \
XAssertStatus = XASSERT_OCCURRED; \
return; \
}
/*****************************************************************************/
/**
* Always assert. This assert macro is to be used for functions that do return
* a value. Use for instances where an assert should always occur.
*
* @return
*
* Returns void unless the XWaitInAssert variable is true, in which case
* no return is made and an infinite loop is entered.
*
* @note
*
* None.
*
******************************************************************************/
#define XASSERT_NONVOID_ALWAYS() \
{ \
XAssert(__FILE__, __LINE__); \
XAssertStatus = XASSERT_OCCURRED; \
return 0; \
}
#else
#define XASSERT_VOID(expression)
#define XASSERT_VOID_ALWAYS()
#define XASSERT_NONVOID(expression)
#define XASSERT_NONVOID_ALWAYS()
#endif
/************************** Function Prototypes ******************************/
void XAssertSetCallback(XAssertCallback Routine);
#endif /* end of protection macro */

63
include/asm-microblaze/arch-microblaze/xio.h
View File

@ -1,63 +0,0 @@
/*
* xio.h
*
* Defines XIo functions for Xilinx OCP in terms of Linux primitives
*
* Author: MontaVista Software, Inc.
* source@mvista.com
*
* 2002 (c) MontaVista, Software, Inc. This file is licensed under the terms
* of the GNU General Public License version 2. This program is licensed
* "as is" without any warranty of any kind, whether express or implied.
*/
#ifndef XIO_H
#define XIO_H
#include "xbasic_types.h"
#include <asm/io.h>
typedef u32 XIo_Address;
extern inline u8
XIo_In8(XIo_Address InAddress)
{
return (u8) in_8((volatile unsigned char *) InAddress);
}
extern inline u16
XIo_In16(XIo_Address InAddress)
{
return (u16) in_be16((volatile unsigned short *) InAddress);
}
extern inline u32
XIo_In32(XIo_Address InAddress)
{
return (u32) in_be32((volatile unsigned *) InAddress);
}
extern inline void
XIo_Out8(XIo_Address OutAddress, u8 Value)
{
out_8((volatile unsigned char *) OutAddress, Value);
}
extern inline void
XIo_Out16(XIo_Address OutAddress, u16 Value)
{
out_be16((volatile unsigned short *) OutAddress, Value);
}
extern inline void
XIo_Out32(XIo_Address OutAddress, u32 Value)
{
out_be32((volatile unsigned *) OutAddress, Value);
}
#define XIo_ToLittleEndian16(s,d) (*(u16*)(d) = cpu_to_le16((u16)(s)))
#define XIo_ToLittleEndian32(s,d) (*(u32*)(d) = cpu_to_le32((u32)(s)))
#define XIo_ToBigEndian16(s,d) (*(u16*)(d) = cpu_to_be16((u16)(s)))
#define XIo_ToBigEndian32(s,d) (*(u32*)(d) = cpu_to_be32((u32)(s)))
#define XIo_FromLittleEndian16(s,d) (*(u16*)(d) = le16_to_cpu((u16)(s)))
#define XIo_FromLittleEndian32(s,d) (*(u32*)(d) = le32_to_cpu((u32)(s)))
#define XIo_FromBigEndian16(s,d) (*(u16*)(d) = be16_to_cpu((u16)(s)))
#define XIo_FromBigEndian32(s,d) (*(u32*)(d) = be32_to_cpu((u32)(s)))
#endif /* XIO_H */

256
include/asm-microblaze/arch-microblaze/xuartlite_l.h
View File

@ -1,256 +0,0 @@
/*****************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 Xilinx Inc.
* All rights reserved.
*
*****************************************************************************/
/****************************************************************************/
/**
*
* @file xuartlite_l.h
*
* This header file contains identifiers and low-level driver functions (or
* macros) that can be used to access the device. High-level driver functions
* are defined in xuartlite.h.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00b rpm 04/25/02 First release
* </pre>
*
*****************************************************************************/
#ifndef XUARTLITE_L_H /* prevent circular inclusions */
#define XUARTLITE_L_H /* by using protection macros */
/***************************** Include Files ********************************/
#include "xbasic_types.h"
#include "xio.h"
/************************** Constant Definitions ****************************/
/* UART Lite register offsets */
#define XUL_RX_FIFO_OFFSET 0 /* receive FIFO, read only */
#define XUL_TX_FIFO_OFFSET 4 /* transmit FIFO, write only */
#define XUL_STATUS_REG_OFFSET 8 /* status register, read only */
#define XUL_CONTROL_REG_OFFSET 12 /* control register, write only */
/* control register bit positions */
#define XUL_CR_ENABLE_INTR 0x10 /* enable interrupt */
#define XUL_CR_FIFO_RX_RESET 0x02 /* reset receive FIFO */
#define XUL_CR_FIFO_TX_RESET 0x01 /* reset transmit FIFO */
/* status register bit positions */
#define XUL_SR_PARITY_ERROR 0x80
#define XUL_SR_FRAMING_ERROR 0x40
#define XUL_SR_OVERRUN_ERROR 0x20
#define XUL_SR_INTR_ENABLED 0x10 /* interrupt enabled */
#define XUL_SR_TX_FIFO_FULL 0x08 /* transmit FIFO full */
#define XUL_SR_TX_FIFO_EMPTY 0x04 /* transmit FIFO empty */
#define XUL_SR_RX_FIFO_FULL 0x02 /* receive FIFO full */
#define XUL_SR_RX_FIFO_VALID_DATA 0x01 /* data in receive FIFO */
/* the following constant specifies the size of the FIFOs, the size of the
* FIFOs includes the transmitter and receiver such that it is the total number
* of bytes that the UART can buffer
*/
#define XUL_FIFO_SIZE 16
/* Stop bits are fixed at 1. Baud, parity, and data bits are fixed on a
* per instance basis
*/
#define XUL_STOP_BITS 1
/* Parity definitions
*/
#define XUL_PARITY_NONE 0
#define XUL_PARITY_ODD 1
#define XUL_PARITY_EVEN 2
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/*****************************************************************************
*
* Low-level driver macros and functions. The list below provides signatures
* to help the user use the macros.
*
* void XUartLite_mSetControlReg(u32 BaseAddress, u32 Mask)
* u32 XUartLite_mGetControlReg(u32 BaseAddress)
* u32 XUartLite_mGetStatusReg(u32 BaseAddress)
*
* Xboolean XUartLite_mIsReceiveEmpty(u32 BaseAddress)
* Xboolean XUartLite_mIsTransmitFull(u32 BaseAddress)
* Xboolean XUartLite_mIsIntrEnabled(u32 BaseAddress)
*
* void XUartLite_mEnableIntr(u32 BaseAddress)
* void XUartLite_mDisableIntr(u32 BaseAddress)
*
* void XUartLite_SendByte(u32 BaseAddress, u8 Data);
* u8 XUartLite_RecvByte(u32 BaseAddress);
*
*****************************************************************************/
/****************************************************************************/
/**
*
* Set the contents of the control register. Use the XUL_CR_* constants defined
* above to create the bit-mask to be written to the register.
*
* @param BaseAddress is the base address of the device
* @param Mask is the 32-bit value to write to the control register
*
* @return None.
*
* @note None.
*
*****************************************************************************/
#define XUartLite_mSetControlReg(BaseAddress, Mask) \
XIo_Out32((BaseAddress) + XUL_CONTROL_REG_OFFSET, (Mask))
/****************************************************************************/
/**
*
* Get the contents of the control register. Use the XUL_CR_* constants defined
* above to interpret the bit-mask returned.
*
* @param BaseAddress is the base address of the device
*
* @return A 32-bit value representing the contents of the control register.
*
* @note None.
*
*****************************************************************************/
#define XUartLite_mGetControlReg(BaseAddress) \
XIo_In32((BaseAddress) + XUL_CONTROL_REG_OFFSET)
/****************************************************************************/
/**
*
* Get the contents of the status register. Use the XUL_SR_* constants defined
* above to interpret the bit-mask returned.
*
* @param BaseAddress is the base address of the device
*
* @return A 32-bit value representing the contents of the status register.
*
* @note None.
*
*****************************************************************************/
#define XUartLite_mGetStatusReg(BaseAddress) \
XIo_In32((BaseAddress) + XUL_STATUS_REG_OFFSET)
/****************************************************************************/
/**
*
* Check to see if the receiver has data.
*
* @param BaseAddress is the base address of the device
*
* @return XTRUE if the receiver is empty, XFALSE if there is data present.
*
* @note None.
*
*****************************************************************************/
#define XUartLite_mIsReceiveEmpty(BaseAddress) \
(!(XUartLite_mGetStatusReg((BaseAddress)) & XUL_SR_RX_FIFO_VALID_DATA))
/****************************************************************************/
/**
*
* Check to see if the transmitter is full.
*
* @param BaseAddress is the base address of the device
*
* @return XTRUE if the transmitter is full, XFALSE otherwise.
*
* @note None.
*
*****************************************************************************/
#define XUartLite_mIsTransmitFull(BaseAddress) \
(XUartLite_mGetStatusReg((BaseAddress)) & XUL_SR_TX_FIFO_FULL)
/****************************************************************************/
/**
*
* Check to see if the interrupt is enabled.
*
* @param BaseAddress is the base address of the device
*
* @return XTRUE if the interrupt is enabled, XFALSE otherwise.
*
* @note None.
*
*****************************************************************************/
#define XUartLite_mIsIntrEnabled(BaseAddress) \
(XUartLite_mGetStatusReg((BaseAddress)) & XUL_SR_INTR_ENABLED)
/****************************************************************************/
/**
*
* Enable the device interrupt. Preserve the contents of the control register.
*
* @param BaseAddress is the base address of the device
*
* @return None.
*
* @note None.
*
*****************************************************************************/
#define XUartLite_mEnableIntr(BaseAddress) \
XUartLite_mSetControlReg((BaseAddress), \
XUartLite_mGetControlReg((BaseAddress)) | XUL_CR_ENABLE_INTR)
/****************************************************************************/
/**
*
* Disable the device interrupt. Preserve the contents of the control register.
*
* @param BaseAddress is the base address of the device
*
* @return None.
*
* @note None.
*
*****************************************************************************/
#define XUartLite_mDisableIntr(BaseAddress) \
XUartLite_mSetControlReg((BaseAddress), \
XUartLite_mGetControlReg((BaseAddress)) & ~XUL_CR_ENABLE_INTR)
/************************** Function Prototypes *****************************/
void XUartLite_SendByte(u32 BaseAddress, u8 Data);
u8 XUartLite_RecvByte(u32 BaseAddress);
#endif /* end of protection macro */

2
include/asm-microblaze/io.h
View File

@ -16,6 +16,8 @@
#ifndef __MICROBLAZE_IO_H__
#define __MICROBLAZE_IO_H__
#include <asm/types.h>
#define IO_SPACE_LIMIT 0xFFFFFFFF
#define readb(addr) \

25
include/asm-microblaze/serial_xuartlite.h
View File

@ -1,25 +0,0 @@
/*
* (C) Copyright 2004 Atmark Techno, Inc.
*
* Yasushi SHOJI <yashi@atmark-techno.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <asm/arch/xuartlite_l.h>

2
include/configs/EB+MCF-EV123.h
View File

@ -84,6 +84,8 @@
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_MCFTMR
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
# define CONFIG_NET_MULTI 1

4
include/configs/M5475EVB.h
View File

@ -303,9 +303,9 @@
#define CFG_CS0_CTRL 0x00101980
#ifdef CFG_NOR1SZ
#define CFG_CS1_BASE 0xF8000000
#define CFG_CS1_BASE 0xE0000000
#define CFG_CS1_MASK (((CFG_NOR1SZ << 20) - 1) & 0xFFFF0001)
#define CFG_CS1_CTRL 0x00000D80
#define CFG_CS1_CTRL 0x00101D80
#endif
#endif /* _M5475EVB_H */

4
include/configs/M5485EVB.h
View File

@ -289,9 +289,9 @@
#define CFG_CS0_CTRL 0x00101980
#ifdef CFG_NOR1SZ
#define CFG_CS1_BASE 0xF8000000
#define CFG_CS1_BASE 0xE0000000
#define CFG_CS1_MASK (((CFG_NOR1SZ << 20) - 1) & 0xFFFF0001)
#define CFG_CS1_CTRL 0x00000D80
#define CFG_CS1_CTRL 0x00101D80
#endif
#endif /* _M5485EVB_H */

1
include/configs/davinci_sffsdr.h
View File

@ -137,6 +137,7 @@
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_NAND
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF /* Needed to load Integrity kernel. */
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_SETGETDCR

4
include/configs/pxa255_idp.h
View File

@ -208,6 +208,10 @@
/* "protect off" */
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
/* #define CONFIG_INITRD_TAG 1 */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */

2
include/configs/sc520_spunk.h
View File

@ -144,7 +144,7 @@
#define CONFIG_SPI_EEPROM /* SPI EEPROMs such as AT25010 or AT25640 */
#define CONFIG_MW_EEPROM /* MicroWire EEPROMS such as AT93LC46 */
#define CONFIG_DS1722 /* Dallas DS1722 SPI Temperature probe */
#define CONFIG_DTT_DS1722 /* Dallas DS1722 SPI Temperature probe */
/* allow to overwrite serial and ethaddr */

1
include/dataflash.h
View File

@ -137,6 +137,7 @@ struct dataflash_addr {
/*-------------------------------------------------------------------------------------------------*/
#define AT45DB161 0x2c
#define AT45DB021 0x14
#define AT45DB321 0x34
#define AT45DB642 0x3c
#define AT45DB128 0x10

77
include/dtt.h
View File

@ -40,9 +40,11 @@
#define DTT_COMMERCIAL_MAX_TEMP 70 /* 0 - +70 C */
#define DTT_INDUSTRIAL_MAX_TEMP 85 /* -40 - +85 C */
#define DTT_AUTOMOTIVE_MAX_TEMP 105 /* -40 - +105 C */
#ifndef CFG_DTT_MAX_TEMP
#define CFG_DTT_MAX_TEMP DTT_COMMERCIAL_MAX_TEMP
#endif
#ifndef CFG_DTT_HYSTERESIS
#define CFG_DTT_HYSTERESIS 5 /* 5 C */
#endif
@ -54,79 +56,4 @@ extern int dtt_write(int sensor, int reg, int val);
extern int dtt_get_temp(int sensor);
#endif
#if defined(CONFIG_DTT_LM75)
#define DTT_READ_TEMP 0x0
#define DTT_CONFIG 0x1
#define DTT_TEMP_HYST 0x2
#define DTT_TEMP_SET 0x3
#endif
#if defined(CONFIG_DTT_LM81)
#define DTT_READ_TEMP 0x27
#define DTT_CONFIG_TEMP 0x4b
#define DTT_TEMP_MAX 0x39
#define DTT_TEMP_HYST 0x3a
#define DTT_CONFIG 0x40
#endif
#if defined(CONFIG_DTT_DS1621)
#define DTT_READ_TEMP 0xAA
#define DTT_READ_COUNTER 0xA8
#define DTT_READ_SLOPE 0xA9
#define DTT_WRITE_START_CONV 0xEE
#define DTT_WRITE_STOP_CONV 0x22
#define DTT_TEMP_HIGH 0xA1
#define DTT_TEMP_LOW 0xA2
#define DTT_CONFIG 0xAC
#endif
#if defined(CONFIG_DTT_DS1775)
#define DTT_READ_TEMP 0x0
#define DTT_CONFIG 0x1
#define DTT_TEMP_HYST 0x2
#define DTT_TEMP_OS 0x3
#endif
#if defined(CONFIG_DTT_ADM1021)
#define DTT_READ_LOC_VALUE 0x00
#define DTT_READ_REM_VALUE 0x01
#define DTT_READ_STATUS 0x02
#define DTT_READ_CONFIG 0x03
#define DTT_READ_CONVRATE 0x04
#define DTT_READ_LOC_HIGHLIM 0x05
#define DTT_READ_LOC_LOWLIM 0x06
#define DTT_READ_REM_HIGHLIM 0x07
#define DTT_READ_REM_LOWLIM 0x08
#define DTT_READ_DEVID 0xfe
#define DTT_WRITE_CONFIG 0x09
#define DTT_WRITE_CONVRATE 0x0a
#define DTT_WRITE_LOC_HIGHLIM 0x0b
#define DTT_WRITE_LOC_LOWLIM 0x0c
#define DTT_WRITE_REM_HIGHLIM 0x0d
#define DTT_WRITE_REM_LOWLIM 0x0e
#define DTT_WRITE_ONESHOT 0x0f
#define DTT_STATUS_BUSY 0x80 /* 1=ADC Converting */
#define DTT_STATUS_LHIGH 0x40 /* 1=Local High Temp Limit Tripped */
#define DTT_STATUS_LLOW 0x20 /* 1=Local Low Temp Limit Tripped */
#define DTT_STATUS_RHIGH 0x10 /* 1=Remote High Temp Limit Tripped */
#define DTT_STATUS_RLOW 0x08 /* 1=Remote Low Temp Limit Tripped */
#define DTT_STATUS_OPEN 0x04 /* 1=Remote Sensor Open-Circuit */
#define DTT_CONFIG_ALERT_MASKED 0x80 /* 0=ALERT Enabled, 1=ALERT Masked */
#define DTT_CONFIG_STANDBY 0x40 /* 0=Run, 1=Standby */
#define DTT_ADM1021_DEVID 0x41
#endif
#if defined(CONFIG_DTT_LM73)
#define DTT_READ_TEMP 0x0
#define DTT_CONFIG 0x1
#define DTT_TEMP_HIGH 0x2
#define DTT_TEMP_LOW 0x3
#define DTT_CONTROL 0x4
#define DTT_ID 0x7
#endif
#endif /* _DTT_H_ */

6
lib_m68k/board.c
View File

@ -176,7 +176,7 @@ typedef int (init_fnc_t) (void);
static int init_baudrate (void)
{
uchar tmp[64]; /* long enough for environment variables */
char tmp[64]; /* long enough for environment variables */
int i = getenv_r ("baudrate", tmp, sizeof (tmp));
gd->baudrate = (i > 0)
@ -267,7 +267,7 @@ board_init_f (ulong bootflag)
#ifdef CONFIG_PRAM
int i;
ulong reg;
uchar tmp[64]; /* long enough for environment variables */
char tmp[64]; /* long enough for environment variables */
#endif
/* Pointer is writable since we allocated a register for it */
@ -752,7 +752,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
*/
{
ulong pram;
uchar memsz[32];
char memsz[32];
#ifdef CONFIG_PRAM
char *s;

2
net/net.c
View File

@ -1390,7 +1390,7 @@ NetReceive(volatile uchar * inpkt, int len)
puts ("Got IP\n");
#endif
if (len < IP_HDR_SIZE) {
debug ("len bad %d < %d\n", len, IP_HDR_SIZE);
debug ("len bad %d < %ld\n", len, IP_HDR_SIZE);
return;
}
if (len < ntohs(ip->ip_len)) {

2
tools/gdb/Makefile
View File

@ -47,7 +47,7 @@ HOSTOS := $(shell uname -s | sed -e 's/\([Cc][Yy][Gg][Ww][Ii][Nn]\).*/cygwin/')
ifeq ($(HOSTOS),cygwin)
all:
.depend:
$(obj).depend:
else # ! CYGWIN