mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-29 08:00:26 +09:00
i2c: fti2c010: migrate to new i2c model
Replace the legacy i2c model with the new one. Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> Cc: Heiko Schocher <hs@denx.de>
This commit is contained in:
Kuo-Jung Su
Heiko Schocher
parent
e6d3ab8909
commit
49f4c762e4
@ -13,14 +13,14 @@
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#include "fti2c010.h"
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#ifndef CONFIG_HARD_I2C
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#error "fti2c010: CONFIG_HARD_I2C is not defined"
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#endif
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#ifndef CONFIG_SYS_I2C_SPEED
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#define CONFIG_SYS_I2C_SPEED 5000
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#endif
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#ifndef CONFIG_SYS_I2C_SLAVE
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#define CONFIG_SYS_I2C_SLAVE 0
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#endif
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#ifndef CONFIG_FTI2C010_CLOCK
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#define CONFIG_FTI2C010_CLOCK clk_get_rate("I2C")
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#endif
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@ -35,44 +35,54 @@
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struct fti2c010_chip {
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struct fti2c010_regs *regs;
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uint bus;
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uint speed;
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};
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static struct fti2c010_chip chip_list[] = {
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{
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.bus = 0,
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.regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE,
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},
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#ifdef CONFIG_I2C_MULTI_BUS
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# ifdef CONFIG_FTI2C010_BASE1
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#ifdef CONFIG_FTI2C010_BASE1
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{
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.bus = 1,
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.regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE1,
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},
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# endif
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# ifdef CONFIG_FTI2C010_BASE2
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#endif
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#ifdef CONFIG_FTI2C010_BASE2
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{
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.bus = 2,
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.regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE2,
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},
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# endif
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# ifdef CONFIG_FTI2C010_BASE3
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#endif
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#ifdef CONFIG_FTI2C010_BASE3
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{
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.bus = 3,
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.regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE3,
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},
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# endif
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#endif /* #ifdef CONFIG_I2C_MULTI_BUS */
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#endif
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};
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static struct fti2c010_chip *curr = chip_list;
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static int fti2c010_reset(struct fti2c010_chip *chip)
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{
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ulong ts;
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int ret = -1;
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struct fti2c010_regs *regs = chip->regs;
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static int fti2c010_wait(uint32_t mask)
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writel(CR_I2CRST, ®s->cr);
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for (ts = get_timer(0); get_timer(ts) < CONFIG_FTI2C010_TIMEOUT; ) {
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if (!(readl(®s->cr) & CR_I2CRST)) {
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ret = 0;
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break;
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}
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}
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if (ret)
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printf("fti2c010: reset timeout\n");
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return ret;
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}
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static int fti2c010_wait(struct fti2c010_chip *chip, uint32_t mask)
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{
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int ret = -1;
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uint32_t stat, ts;
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struct fti2c010_regs *regs = curr->regs;
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struct fti2c010_regs *regs = chip->regs;
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for (ts = get_timer(0); get_timer(ts) < CONFIG_FTI2C010_TIMEOUT; ) {
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stat = readl(®s->sr);
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@ -85,74 +95,97 @@ static int fti2c010_wait(uint32_t mask)
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return ret;
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}
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/*
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* u-boot I2C API
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*/
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static unsigned int set_i2c_bus_speed(struct fti2c010_chip *chip,
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unsigned int speed)
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{
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struct fti2c010_regs *regs = chip->regs;
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unsigned int clk = CONFIG_FTI2C010_CLOCK;
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unsigned int gsr = 0;
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unsigned int tsr = 32;
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unsigned int div, rate;
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for (div = 0; div < 0x3ffff; ++div) {
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/* SCLout = PCLK/(2*(COUNT + 2) + GSR) */
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rate = clk / (2 * (div + 2) + gsr);
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if (rate <= speed)
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break;
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}
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writel(TGSR_GSR(gsr) | TGSR_TSR(tsr), ®s->tgsr);
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writel(CDR_DIV(div), ®s->cdr);
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return rate;
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}
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/*
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* Initialization, must be called once on start up, may be called
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* repeatedly to change the speed and slave addresses.
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*/
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void i2c_init(int speed, int slaveaddr)
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static void fti2c010_init(struct i2c_adapter *adap, int speed, int slaveaddr)
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{
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if (speed || !curr->speed)
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i2c_set_bus_speed(speed);
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struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
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/* if slave mode disabled */
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if (!slaveaddr)
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if (adap->init_done)
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return;
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/*
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* TODO:
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* Implement slave mode, but is it really necessary?
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*/
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#ifdef CONFIG_SYS_I2C_INIT_BOARD
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/* Call board specific i2c bus reset routine before accessing the
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* environment, which might be in a chip on that bus. For details
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* about this problem see doc/I2C_Edge_Conditions.
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*/
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i2c_init_board();
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#endif
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/* master init */
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fti2c010_reset(chip);
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set_i2c_bus_speed(chip, speed);
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/* slave init, don't care */
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#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
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/* Call board specific i2c bus reset routine AFTER the bus has been
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* initialized. Use either this callpoint or i2c_init_board;
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* which is called before fti2c010_init operations.
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* For details about this problem see doc/I2C_Edge_Conditions.
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*/
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i2c_board_late_init();
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#endif
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}
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/*
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* Probe the given I2C chip address. Returns 0 if a chip responded,
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* not 0 on failure.
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*/
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int i2c_probe(uchar chip)
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static int fti2c010_probe(struct i2c_adapter *adap, u8 dev)
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{
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struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
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struct fti2c010_regs *regs = chip->regs;
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int ret;
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struct fti2c010_regs *regs = curr->regs;
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i2c_init(0, 0);
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/* 1. Select slave device (7bits Address + 1bit R/W) */
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writel(I2C_WR(chip), ®s->dr);
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writel(I2C_WR(dev), ®s->dr);
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writel(CR_ENABLE | CR_TBEN | CR_START, ®s->cr);
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ret = fti2c010_wait(SR_DT);
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ret = fti2c010_wait(chip, SR_DT);
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if (ret)
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return ret;
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/* 2. Select device register */
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writel(0, ®s->dr);
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writel(CR_ENABLE | CR_TBEN, ®s->cr);
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ret = fti2c010_wait(SR_DT);
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ret = fti2c010_wait(chip, SR_DT);
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return ret;
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}
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/*
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* Read/Write interface:
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* chip: I2C chip address, range 0..127
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* addr: Memory (register) address within the chip
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* alen: Number of bytes to use for addr (typically 1, 2 for larger
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* memories, 0 for register type devices with only one
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* register)
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* buffer: Where to read/write the data
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* len: How many bytes to read/write
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*
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* Returns: 0 on success, not 0 on failure
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*/
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int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
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static int fti2c010_read(struct i2c_adapter *adap,
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u8 dev, uint addr, int alen, uchar *buf, int len)
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{
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struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
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struct fti2c010_regs *regs = chip->regs;
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int ret, pos;
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uchar paddr[4];
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struct fti2c010_regs *regs = curr->regs;
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i2c_init(0, 0);
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paddr[0] = (addr >> 0) & 0xFF;
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paddr[1] = (addr >> 8) & 0xFF;
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@ -164,9 +197,9 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
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*/
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/* A.1 Select slave device (7bits Address + 1bit R/W) */
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writel(I2C_WR(chip), ®s->dr);
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writel(I2C_WR(dev), ®s->dr);
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writel(CR_ENABLE | CR_TBEN | CR_START, ®s->cr);
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ret = fti2c010_wait(SR_DT);
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ret = fti2c010_wait(chip, SR_DT);
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if (ret)
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return ret;
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@ -176,7 +209,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
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writel(paddr[pos], ®s->dr);
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writel(ctrl, ®s->cr);
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ret = fti2c010_wait(SR_DT);
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ret = fti2c010_wait(chip, SR_DT);
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if (ret)
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return ret;
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}
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@ -186,9 +219,9 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
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*/
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/* B.1 Select slave device (7bits Address + 1bit R/W) */
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writel(I2C_RD(chip), ®s->dr);
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writel(I2C_RD(dev), ®s->dr);
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writel(CR_ENABLE | CR_TBEN | CR_START, ®s->cr);
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ret = fti2c010_wait(SR_DT);
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ret = fti2c010_wait(chip, SR_DT);
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if (ret)
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return ret;
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@ -202,7 +235,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
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stat |= SR_ACK;
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}
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writel(ctrl, ®s->cr);
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ret = fti2c010_wait(stat);
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ret = fti2c010_wait(chip, stat);
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if (ret)
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break;
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buf[pos] = (uchar)(readl(®s->dr) & 0xFF);
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@ -211,25 +244,13 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
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return ret;
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}
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/*
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* Read/Write interface:
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* chip: I2C chip address, range 0..127
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* addr: Memory (register) address within the chip
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* alen: Number of bytes to use for addr (typically 1, 2 for larger
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* memories, 0 for register type devices with only one
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* register)
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* buffer: Where to read/write the data
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* len: How many bytes to read/write
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*
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* Returns: 0 on success, not 0 on failure
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*/
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int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
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static int fti2c010_write(struct i2c_adapter *adap,
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u8 dev, uint addr, int alen, u8 *buf, int len)
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{
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struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
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struct fti2c010_regs *regs = chip->regs;
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int ret, pos;
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uchar paddr[4];
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struct fti2c010_regs *regs = curr->regs;
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i2c_init(0, 0);
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paddr[0] = (addr >> 0) & 0xFF;
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paddr[1] = (addr >> 8) & 0xFF;
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@ -241,9 +262,9 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
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*
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* A.1 Select slave device (7bits Address + 1bit R/W)
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*/
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writel(I2C_WR(chip), ®s->dr);
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writel(I2C_WR(dev), ®s->dr);
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writel(CR_ENABLE | CR_TBEN | CR_START, ®s->cr);
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ret = fti2c010_wait(SR_DT);
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ret = fti2c010_wait(chip, SR_DT);
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if (ret)
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return ret;
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@ -253,7 +274,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
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writel(paddr[pos], ®s->dr);
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writel(ctrl, ®s->cr);
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ret = fti2c010_wait(SR_DT);
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ret = fti2c010_wait(chip, SR_DT);
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if (ret)
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return ret;
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}
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@ -268,7 +289,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
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ctrl |= CR_STOP;
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writel(buf[pos], ®s->dr);
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writel(ctrl, ®s->cr);
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ret = fti2c010_wait(SR_DT);
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ret = fti2c010_wait(chip, SR_DT);
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if (ret)
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break;
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}
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@ -276,94 +297,40 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
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return ret;
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}
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/*
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* Functions for setting the current I2C bus and its speed
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*/
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#ifdef CONFIG_I2C_MULTI_BUS
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/*
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* i2c_set_bus_num:
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*
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* Change the active I2C bus. Subsequent read/write calls will
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* go to this one.
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*
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* bus - bus index, zero based
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*
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* Returns: 0 on success, not 0 on failure
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*/
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int i2c_set_bus_num(uint bus)
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static unsigned int fti2c010_set_bus_speed(struct i2c_adapter *adap,
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unsigned int speed)
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{
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if (bus >= ARRAY_SIZE(chip_list))
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return -1;
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curr = chip_list + bus;
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i2c_init(0, 0);
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return 0;
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struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
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int ret;
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fti2c010_reset(chip);
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ret = set_i2c_bus_speed(chip, speed);
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return ret;
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}
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/*
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* i2c_get_bus_num:
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*
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* Returns index of currently active I2C bus. Zero-based.
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* Register i2c adapters
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*/
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uint i2c_get_bus_num(void)
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{
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return curr->bus;
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}
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#endif /* #ifdef CONFIG_I2C_MULTI_BUS */
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/*
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* i2c_set_bus_speed:
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*
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* Change the speed of the active I2C bus
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*
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* speed - bus speed in Hz
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*
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* Returns: 0 on success, not 0 on failure
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*/
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int i2c_set_bus_speed(uint speed)
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{
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struct fti2c010_regs *regs = curr->regs;
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uint clk = CONFIG_FTI2C010_CLOCK;
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uint gsr = 0, tsr = 32;
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uint spd, div;
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if (!speed)
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speed = CONFIG_SYS_I2C_SPEED;
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for (div = 0; div < 0x3ffff; ++div) {
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/* SCLout = PCLK/(2*(COUNT + 2) + GSR) */
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spd = clk / (2 * (div + 2) + gsr);
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if (spd <= speed)
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break;
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}
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if (curr->speed == spd)
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return 0;
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writel(CR_I2CRST, ®s->cr);
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mdelay(100);
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if (readl(®s->cr) & CR_I2CRST) {
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printf("fti2c010: reset timeout\n");
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return -1;
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}
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curr->speed = spd;
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writel(TGSR_GSR(gsr) | TGSR_TSR(tsr), ®s->tgsr);
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writel(CDR_DIV(div), ®s->cdr);
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return 0;
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}
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/*
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* i2c_get_bus_speed:
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*
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* Returns speed of currently active I2C bus in Hz
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*/
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uint i2c_get_bus_speed(void)
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{
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return curr->speed;
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}
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U_BOOT_I2C_ADAP_COMPLETE(i2c_0, fti2c010_init, fti2c010_probe, fti2c010_read,
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fti2c010_write, fti2c010_set_bus_speed,
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CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
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0)
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#ifdef CONFIG_FTI2C010_BASE1
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U_BOOT_I2C_ADAP_COMPLETE(i2c_1, fti2c010_init, fti2c010_probe, fti2c010_read,
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fti2c010_write, fti2c010_set_bus_speed,
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CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
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1)
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#endif
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#ifdef CONFIG_FTI2C010_BASE2
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U_BOOT_I2C_ADAP_COMPLETE(i2c_2, fti2c010_init, fti2c010_probe, fti2c010_read,
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fti2c010_write, fti2c010_set_bus_speed,
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CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
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2)
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#endif
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#ifdef CONFIG_FTI2C010_BASE3
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U_BOOT_I2C_ADAP_COMPLETE(i2c_3, fti2c010_init, fti2c010_probe, fti2c010_read,
|
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fti2c010_write, fti2c010_set_bus_speed,
|
||||
CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
|
||||
3)
|
||||
#endif
|
||||
|
||||
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Reference in New Issue
Block a user