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- MIPS: refactor cache init and setup in start.S
- MIPS: sync asm header files with Linux 5.7 - MIPS: add initial support for Marvell Octeon MIPS64 -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiQkHUH+J02LLC9InKPlOlyTyXBgFAl8S/pwACgkQKPlOlyTy XBjQ3g//aOU4k+pWkZoKH4uxLtkZrZ8UFI0K9eBJ9B6dcw0Rlm9WvAG5TbF2nDRY BnG54IO8KncLNyUNJal1gnMno8SFTFUqOwoY9f12WnIihYfugcqRiFfaWjOQCeJL tGoP9mpHZivtA9Jj1VmI0cpcP6LO3eXnGGa1SAMv/XiStrmCEFoRTHUiA2NF2Xl2 6rYsgq+7V1teRAE2ig9+B1Z6PYeQH1byF9gJ/6ATABrNUXRrfJfWfhkaEuBApedr NAN29zB4gwS/e0/DtxjLeNEb9cAEUnRS3ETblcCQPbTWqU6+rsRHuHpd8HofH71c iP0Z7l7a37xg7FnaiEH0FYR24fDHfsEi3a6K39GyhsimKPNSeAZcr/swMOueCKcY 4hkJ5qJ0mc8vAEMBg+aERlpvAKvfVFN35e26B8bqq6oNNdjUKVWLnkOrX2tnOGbe VfAitR2u5UYX6ZYEktcMtSxjq5CumyDKDhDFoSC3ic26H5efjpwZxgjn9G/j1HKM qld36iSKGWFP5r52QooDOi9uQ9qYc1tBbW9ck/uCZwZWOHrPg9c4uxdBw5egf9RN i3RuY6EZ/SaImA1ubl1y8E6Ey8oKdKqyMvRHCGq+WsICCkl4ydxU7zc4EpcGIqYA k+UtkJ7g2RWQeqTPQ65MskeuYDdgtSDIUrqgJgAMKxkyDRnieDA= =LpkC -----END PGP SIGNATURE----- Merge tag 'mips-pull-2020-07-18' of https://gitlab.denx.de/u-boot/custodians/u-boot-mips - MIPS: refactor cache init and setup in start.S - MIPS: sync asm header files with Linux 5.7 - MIPS: add initial support for Marvell Octeon MIPS64
This commit is contained in:
commit
49cf75101d
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@ -770,6 +770,13 @@ M: Ezequiel Garcia <ezequiel@collabora.com>
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||||||
S: Maintained
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S: Maintained
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||||||
F: arch/mips/mach-jz47xx/
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F: arch/mips/mach-jz47xx/
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MIPS Octeon
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M: Aaron Williams <awilliams@marvell.com>
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S: Maintained
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F: arch/mips/mach-octeon/
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F: arch/mips/include/asm/arch-octeon/
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F: arch/mips/dts/mrvl,cn73xx.dtsi
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MMC
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MMC
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M: Peng Fan <peng.fan@nxp.com>
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M: Peng Fan <peng.fan@nxp.com>
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S: Maintained
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S: Maintained
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||||||
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@ -106,6 +106,26 @@ config ARCH_JZ47XX
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select OF_CONTROL
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select OF_CONTROL
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select DM
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select DM
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config ARCH_OCTEON
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bool "Support Marvell Octeon CN7xxx platforms"
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select CPU_CAVIUM_OCTEON
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select DISPLAY_CPUINFO
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select DMA_ADDR_T_64BIT
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select DM
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select DM_SERIAL
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select DM_GPIO
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select DM_ETH
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select MIPS_L2_CACHE
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select MIPS_MACH_EARLY_INIT
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select MIPS_TUNE_OCTEON3
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select ROM_EXCEPTION_VECTORS
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select SUPPORTS_BIG_ENDIAN
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select SUPPORTS_CPU_MIPS64_OCTEON
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select PHYS_64BIT
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select OF_CONTROL
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select OF_LIVE
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imply CMD_DM
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config MACH_PIC32
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config MACH_PIC32
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bool "Support Microchip PIC32"
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bool "Support Microchip PIC32"
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select DM
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select DM
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@ -160,6 +180,7 @@ source "arch/mips/mach-bmips/Kconfig"
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source "arch/mips/mach-jz47xx/Kconfig"
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source "arch/mips/mach-jz47xx/Kconfig"
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source "arch/mips/mach-pic32/Kconfig"
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source "arch/mips/mach-pic32/Kconfig"
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source "arch/mips/mach-mtmips/Kconfig"
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source "arch/mips/mach-mtmips/Kconfig"
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source "arch/mips/mach-octeon/Kconfig"
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if MIPS
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if MIPS
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@ -233,6 +254,14 @@ config CPU_MIPS64_R6
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Choose this option to build a kernel for release 6 or later of the
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Choose this option to build a kernel for release 6 or later of the
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MIPS64 architecture.
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MIPS64 architecture.
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config CPU_MIPS64_OCTEON
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bool "Marvell Octeon series of CPUs"
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depends on SUPPORTS_CPU_MIPS64_OCTEON
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select 64BIT
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help
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Choose this option for Marvell Octeon CPUs. These CPUs are between
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MIPS64 R5 and R6 with other extensions.
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endchoice
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endchoice
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menu "General setup"
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menu "General setup"
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@ -270,6 +299,39 @@ config MIPS_CACHE_INDEX_BASE
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Normally this is CKSEG0. If the MIPS system needs to move this block
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Normally this is CKSEG0. If the MIPS system needs to move this block
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to some SRAM or ScratchPad RAM, adapt this option accordingly.
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to some SRAM or ScratchPad RAM, adapt this option accordingly.
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config MIPS_MACH_EARLY_INIT
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bool "Enable mach specific very early init code"
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help
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Use this to enable the call to mips_mach_early_init() very early
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from start.S. This function can be used e.g. to do some very early
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CPU / SoC intitialization or image copying. Its called very early
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and at this stage the PC might not match the linking address
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(CONFIG_TEXT_BASE) - no absolute jump done until this call.
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config MIPS_CACHE_SETUP
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bool "Allow generic start code to initialize and setup caches"
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default n if SKIP_LOWLEVEL_INIT
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default y
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help
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This allows the generic start code to invoke the generic initialization
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of the CPU caches. Disabling this can be useful for RAM boot scenarios
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(EJTAG, SPL payload) or for machines which don't need cache initialization
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or which want to provide their own cache implementation.
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If unsure, say yes.
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config MIPS_CACHE_DISABLE
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bool "Allow generic start code to initially disable caches"
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default n if SKIP_LOWLEVEL_INIT
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default y
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help
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This allows the generic start code to initially disable the CPU caches
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and run uncached until the caches are initialized and enabled. Disabling
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this can be useful on machines which don't need cache initialization or
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which want to provide their own cache implementation.
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If unsure, say yes.
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config MIPS_RELOCATION_TABLE_SIZE
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config MIPS_RELOCATION_TABLE_SIZE
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hex "Relocation table size"
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hex "Relocation table size"
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range 0x100 0x10000
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range 0x100 0x10000
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@ -398,6 +460,12 @@ config SUPPORTS_CPU_MIPS64_R2
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config SUPPORTS_CPU_MIPS64_R6
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config SUPPORTS_CPU_MIPS64_R6
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bool
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bool
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config SUPPORTS_CPU_MIPS64_OCTEON
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bool
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config CPU_CAVIUM_OCTEON
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bool
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config CPU_MIPS32
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config CPU_MIPS32
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bool
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bool
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default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
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default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
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@ -405,6 +473,7 @@ config CPU_MIPS32
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config CPU_MIPS64
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config CPU_MIPS64
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bool
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bool
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default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
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default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
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default y if CPU_MIPS64_OCTEON
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||||||
config MIPS_TUNE_4KC
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config MIPS_TUNE_4KC
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bool
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bool
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@ -421,6 +490,9 @@ config MIPS_TUNE_34KC
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config MIPS_TUNE_74KC
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config MIPS_TUNE_74KC
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bool
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bool
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config MIPS_TUNE_OCTEON3
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bool
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config 32BIT
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config 32BIT
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bool
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bool
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@ -453,6 +525,11 @@ config MIPS_SRAM_INIT
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before it can be used. If enabled, a function mips_sram_init() will
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before it can be used. If enabled, a function mips_sram_init() will
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be called just before setup_stack_gd.
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be called just before setup_stack_gd.
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||||||
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config DMA_ADDR_T_64BIT
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bool
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||||||
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help
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||||||
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Select this to enable 64-bit DMA addressing
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config SYS_DCACHE_SIZE
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config SYS_DCACHE_SIZE
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int
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int
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default 0
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default 0
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||||||
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|
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@ -17,6 +17,7 @@ machine-$(CONFIG_ARCH_JZ47XX) += jz47xx
|
||||||
machine-$(CONFIG_MACH_PIC32) += pic32
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machine-$(CONFIG_MACH_PIC32) += pic32
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||||||
machine-$(CONFIG_ARCH_MTMIPS) += mtmips
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machine-$(CONFIG_ARCH_MTMIPS) += mtmips
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||||||
machine-$(CONFIG_ARCH_MSCC) += mscc
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machine-$(CONFIG_ARCH_MSCC) += mscc
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machine-${CONFIG_ARCH_OCTEON} += octeon
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||||||
machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
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machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
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libs-y += $(machdirs)
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libs-y += $(machdirs)
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@ -30,6 +31,7 @@ arch-$(CONFIG_CPU_MIPS32_R6) += -march=mips32r6 -Wa,-mips32r6
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arch-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,-mips64
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arch-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,-mips64
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||||||
arch-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2
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arch-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2
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arch-$(CONFIG_CPU_MIPS64_R6) += -march=mips64r6 -Wa,-mips64r6
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arch-$(CONFIG_CPU_MIPS64_R6) += -march=mips64r6 -Wa,-mips64r6
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||||||
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arch-${CONFIG_CPU_MIPS64_OCTEON} += -march=octeon2
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||||||
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||||||
# Allow extra optimization for specific CPUs/SoCs
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# Allow extra optimization for specific CPUs/SoCs
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tune-$(CONFIG_MIPS_TUNE_4KC) += -mtune=4kc
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tune-$(CONFIG_MIPS_TUNE_4KC) += -mtune=4kc
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@ -37,6 +39,7 @@ tune-$(CONFIG_MIPS_TUNE_14KC) += -mtune=14kc
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tune-$(CONFIG_MIPS_TUNE_24KC) += -mtune=24kc
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tune-$(CONFIG_MIPS_TUNE_24KC) += -mtune=24kc
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tune-$(CONFIG_MIPS_TUNE_34KC) += -mtune=34kc
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tune-$(CONFIG_MIPS_TUNE_34KC) += -mtune=34kc
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tune-$(CONFIG_MIPS_TUNE_74KC) += -mtune=74kc
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tune-$(CONFIG_MIPS_TUNE_74KC) += -mtune=74kc
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tune-${CONFIG_MIPS_TUNE_OCTEON3} += -mtune=octeon2
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|
|
||||||
# Include default header files
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# Include default header files
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cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic
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cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic
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|
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@ -17,19 +17,10 @@
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#endif
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#endif
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|
|
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#ifdef CONFIG_32BIT
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#ifdef CONFIG_32BIT
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# define MIPS_RELOC 3
|
|
||||||
# define STATUS_SET 0
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# define STATUS_SET 0
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_64BIT
|
#ifdef CONFIG_64BIT
|
||||||
# ifdef CONFIG_SYS_LITTLE_ENDIAN
|
|
||||||
# define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
|
|
||||||
(((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym))
|
|
||||||
# else
|
|
||||||
# define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
|
|
||||||
((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24)
|
|
||||||
# endif
|
|
||||||
# define MIPS_RELOC MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03)
|
|
||||||
# define STATUS_SET ST0_KX
|
# define STATUS_SET ST0_KX
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -147,7 +138,7 @@ reset:
|
||||||
and t0, t0, (1 << 31)
|
and t0, t0, (1 << 31)
|
||||||
#else
|
#else
|
||||||
1: mfc0 t0, CP0_EBASE
|
1: mfc0 t0, CP0_EBASE
|
||||||
and t0, t0, EBASE_CPUNUM
|
and t0, t0, MIPS_EBASE_CPUNUM
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* Hang if this isn't the first CPU in the system */
|
/* Hang if this isn't the first CPU in the system */
|
||||||
|
@ -204,12 +195,11 @@ wr_done:
|
||||||
/* Clear timer interrupt (CP0_COUNT cleared on branch to 'reset') */
|
/* Clear timer interrupt (CP0_COUNT cleared on branch to 'reset') */
|
||||||
mtc0 zero, CP0_COMPARE
|
mtc0 zero, CP0_COMPARE
|
||||||
|
|
||||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
#ifdef CONFIG_MIPS_CACHE_DISABLE
|
||||||
mfc0 t0, CP0_CONFIG
|
/* Disable caches */
|
||||||
and t0, t0, MIPS_CONF_IMPL
|
PTR_LA t9, mips_cache_disable
|
||||||
or t0, t0, CONF_CM_UNCACHED
|
jalr t9
|
||||||
mtc0 t0, CP0_CONFIG
|
nop
|
||||||
ehb
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_MIPS_CM
|
#ifdef CONFIG_MIPS_CM
|
||||||
|
@ -244,12 +234,21 @@ wr_done:
|
||||||
jalr t9
|
jalr t9
|
||||||
nop
|
nop
|
||||||
# endif
|
# endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_MIPS_MACH_EARLY_INIT
|
||||||
|
bal mips_mach_early_init
|
||||||
|
nop
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_MIPS_CACHE_SETUP
|
||||||
/* Initialize caches... */
|
/* Initialize caches... */
|
||||||
PTR_LA t9, mips_cache_reset
|
PTR_LA t9, mips_cache_reset
|
||||||
jalr t9
|
jalr t9
|
||||||
nop
|
nop
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||||
# ifndef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
|
# ifndef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
|
||||||
/* Initialize any external memory */
|
/* Initialize any external memory */
|
||||||
PTR_LA t9, lowlevel_init
|
PTR_LA t9, lowlevel_init
|
||||||
|
|
|
@ -13,7 +13,9 @@ unsigned long notrace timer_read_counter(void)
|
||||||
return read_c0_count();
|
return read_c0_count();
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#if defined(CONFIG_SYS_MIPS_TIMER_FREQ)
|
||||||
ulong notrace __weak get_tbclk(void)
|
ulong notrace __weak get_tbclk(void)
|
||||||
{
|
{
|
||||||
return CONFIG_SYS_MIPS_TIMER_FREQ;
|
return CONFIG_SYS_MIPS_TIMER_FREQ;
|
||||||
}
|
}
|
||||||
|
#endif
|
||||||
|
|
|
@ -18,6 +18,7 @@ dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb
|
||||||
dtb-$(CONFIG_BOARD_COMTREND_WAP5813N) += comtrend,wap-5813n.dtb
|
dtb-$(CONFIG_BOARD_COMTREND_WAP5813N) += comtrend,wap-5813n.dtb
|
||||||
dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
|
dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
|
||||||
dtb-$(CONFIG_BOARD_MT7628_RFB) += mediatek,mt7628-rfb.dtb
|
dtb-$(CONFIG_BOARD_MT7628_RFB) += mediatek,mt7628-rfb.dtb
|
||||||
|
dtb-$(CONFIG_TARGET_OCTEON_EBB7304) += mrvl,octeon-ebb7304.dtb
|
||||||
dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb
|
dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb
|
||||||
dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb
|
dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb
|
||||||
dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb
|
dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb
|
||||||
|
|
64
arch/mips/dts/mrvl,cn73xx.dtsi
Normal file
64
arch/mips/dts/mrvl,cn73xx.dtsi
Normal file
|
@ -0,0 +1,64 @@
|
||||||
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
|
/*
|
||||||
|
* Marvell / Cavium Inc. CN73xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
/ {
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
|
||||||
|
soc0: soc@0 {
|
||||||
|
interrupt-parent = <&ciu3>;
|
||||||
|
compatible = "simple-bus";
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
ranges; /* Direct mapping */
|
||||||
|
|
||||||
|
ciu3: interrupt-controller@1010000000000 {
|
||||||
|
compatible = "cavium,octeon-7890-ciu3";
|
||||||
|
interrupt-controller;
|
||||||
|
/*
|
||||||
|
* Interrupts are specified by two parts:
|
||||||
|
* 1) Source number (20 significant bits)
|
||||||
|
* 2) Trigger type: (4 == level, 1 == edge)
|
||||||
|
*/
|
||||||
|
#address-cells = <0>;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
reg = <0x10100 0x00000000 0x0 0xb0000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
bootbus: bootbus@1180000000000 {
|
||||||
|
compatible = "cavium,octeon-3860-bootbus","simple-bus";
|
||||||
|
reg = <0x11800 0x00000000 0x0 0x200>;
|
||||||
|
/* The chip select number and offset */
|
||||||
|
#address-cells = <2>;
|
||||||
|
/* The size of the chip select region */
|
||||||
|
#size-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
reset: reset@1180006001600 {
|
||||||
|
compatible = "mrvl,cn7xxx-rst";
|
||||||
|
reg = <0x11800 0x06001600 0x0 0x200>;
|
||||||
|
};
|
||||||
|
|
||||||
|
uart0: serial@1180000000800 {
|
||||||
|
compatible = "cavium,octeon-3860-uart","ns16550";
|
||||||
|
reg = <0x11800 0x00000800 0x0 0x400>;
|
||||||
|
clock-frequency = <0>;
|
||||||
|
current-speed = <115200>;
|
||||||
|
reg-shift = <3>;
|
||||||
|
interrupts = <0x08000 4>;
|
||||||
|
};
|
||||||
|
|
||||||
|
uart1: serial@1180000000c00 {
|
||||||
|
compatible = "cavium,octeon-3860-uart","ns16550";
|
||||||
|
reg = <0x11800 0x00000c00 0x0 0x400>;
|
||||||
|
clock-frequency = <0>;
|
||||||
|
current-speed = <115200>;
|
||||||
|
reg-shift = <3>;
|
||||||
|
interrupts = <0x08040 4>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
96
arch/mips/dts/mrvl,octeon-ebb7304.dts
Normal file
96
arch/mips/dts/mrvl,octeon-ebb7304.dts
Normal file
|
@ -0,0 +1,96 @@
|
||||||
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
|
/*
|
||||||
|
* Marvell / Cavium Inc. EVB CN7300
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
/include/ "mrvl,cn73xx.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "cavium,ebb7304";
|
||||||
|
compatible = "cavium,ebb7304";
|
||||||
|
|
||||||
|
aliases {
|
||||||
|
serial0 = &uart0;
|
||||||
|
};
|
||||||
|
|
||||||
|
chosen {
|
||||||
|
stdout-path = &uart0;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&bootbus {
|
||||||
|
/*
|
||||||
|
* bootbus CS0 for CFI flash is remapped (0x1fc0.0000 -> 1f40.0000)
|
||||||
|
* as the initial size is too small for the 8MiB flash device
|
||||||
|
*/
|
||||||
|
ranges = <0 0 0 0x1f400000 0xc00000>,
|
||||||
|
<1 0 0x10000 0x10000000 0>,
|
||||||
|
<2 0 0x10000 0x20000000 0>,
|
||||||
|
<3 0 0x10000 0x30000000 0>,
|
||||||
|
<4 0 0 0x1d020000 0x10000>,
|
||||||
|
<5 0 0x10000 0x50000000 0>,
|
||||||
|
<6 0 0x10000 0x60000000 0>,
|
||||||
|
<7 0 0x10000 0x70000000 0>;
|
||||||
|
|
||||||
|
cavium,cs-config@0 {
|
||||||
|
compatible = "cavium,octeon-3860-bootbus-config";
|
||||||
|
cavium,cs-index = <0>;
|
||||||
|
cavium,t-adr = <10>;
|
||||||
|
cavium,t-ce = <50>;
|
||||||
|
cavium,t-oe = <50>;
|
||||||
|
cavium,t-we = <35>;
|
||||||
|
cavium,t-rd-hld = <25>;
|
||||||
|
cavium,t-wr-hld = <35>;
|
||||||
|
cavium,t-pause = <0>;
|
||||||
|
cavium,t-wait = <50>;
|
||||||
|
cavium,t-page = <30>;
|
||||||
|
cavium,t-rd-dly = <0>;
|
||||||
|
cavium,page-mode = <1>;
|
||||||
|
cavium,pages = <8>;
|
||||||
|
cavium,bus-width = <8>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cavium,cs-config@4 {
|
||||||
|
compatible = "cavium,octeon-3860-bootbus-config";
|
||||||
|
cavium,cs-index = <4>;
|
||||||
|
cavium,t-adr = <10>;
|
||||||
|
cavium,t-ce = <10>;
|
||||||
|
cavium,t-oe = <160>;
|
||||||
|
cavium,t-we = <100>;
|
||||||
|
cavium,t-rd-hld = <10>;
|
||||||
|
cavium,t-wr-hld = <0>;
|
||||||
|
cavium,t-pause = <50>;
|
||||||
|
cavium,t-wait = <50>;
|
||||||
|
cavium,t-page = <10>;
|
||||||
|
cavium,t-rd-dly = <10>;
|
||||||
|
cavium,pages = <0>;
|
||||||
|
cavium,bus-width = <8>;
|
||||||
|
};
|
||||||
|
|
||||||
|
flash0: nor@0,0 {
|
||||||
|
compatible = "cfi-flash";
|
||||||
|
reg = <0 0 0x800000>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
partition@0 {
|
||||||
|
label = "bootloader";
|
||||||
|
reg = <0 0x340000>;
|
||||||
|
read-only;
|
||||||
|
};
|
||||||
|
partition@300000 {
|
||||||
|
label = "storage";
|
||||||
|
reg = <0x340000 0x4be000>;
|
||||||
|
};
|
||||||
|
partition@7fe000 {
|
||||||
|
label = "environment";
|
||||||
|
reg = <0x7fe000 0x2000>;
|
||||||
|
read-only;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&uart0 {
|
||||||
|
clock-frequency = <1200000000>;
|
||||||
|
};
|
|
@ -42,7 +42,7 @@
|
||||||
/*
|
/*
|
||||||
* Returns the kernel segment base of a given address
|
* Returns the kernel segment base of a given address
|
||||||
*/
|
*/
|
||||||
#define KSEGX(a) ((_ACAST32_ (a)) & 0xe0000000)
|
#define KSEGX(a) ((_ACAST32_(a)) & _ACAST32_(0xe0000000))
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Returns the physical address of a CKSEGx / XKPHYS address
|
* Returns the physical address of a CKSEGx / XKPHYS address
|
||||||
|
@ -123,21 +123,7 @@
|
||||||
#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p))
|
#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p))
|
||||||
#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p))
|
#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p))
|
||||||
#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK)
|
#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK)
|
||||||
#define PHYS_TO_XKPHYS(cm, a) (_CONST64_(0x8000000000000000) | \
|
#define PHYS_TO_XKPHYS(cm, a) (XKPHYS | (_ACAST64_(cm) << 59) | (a))
|
||||||
(_CONST64_(cm) << 59) | (a))
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Returns the uncached address of a sdram address
|
|
||||||
*/
|
|
||||||
#ifndef __ASSEMBLY__
|
|
||||||
#if defined(CONFIG_TB0229)
|
|
||||||
/* We use a 36 bit physical address map here and
|
|
||||||
cannot access physical memory directly from core */
|
|
||||||
#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
|
|
||||||
#else /* !CONFIG_TB0229 */
|
|
||||||
#define UNCACHED_SDRAM(a) CKSEG1ADDR(a)
|
|
||||||
#endif /* CONFIG_TB0229 */
|
|
||||||
#endif /* __ASSEMBLY__ */
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting
|
* The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting
|
||||||
|
@ -146,18 +132,9 @@
|
||||||
*/
|
*/
|
||||||
#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */
|
#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */
|
||||||
|
|
||||||
#ifndef CONFIG_CPU_R8000
|
|
||||||
|
|
||||||
/*
|
|
||||||
* The R8000 doesn't have the 32-bit compat spaces so we don't define them
|
|
||||||
* in order to catch bugs in the source code.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define COMPAT_K1BASE32 _CONST64_(0xffffffffa0000000)
|
#define COMPAT_K1BASE32 _CONST64_(0xffffffffa0000000)
|
||||||
#define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */
|
#define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK)
|
#define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK)
|
||||||
#define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE)
|
#define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE)
|
||||||
|
|
||||||
|
|
|
@ -16,37 +16,12 @@
|
||||||
|
|
||||||
#include <asm/sgidefs.h>
|
#include <asm/sgidefs.h>
|
||||||
|
|
||||||
#ifndef CAT
|
|
||||||
#ifdef __STDC__
|
|
||||||
#define __CAT(str1, str2) str1##str2
|
|
||||||
#else
|
|
||||||
#define __CAT(str1, str2) str1/**/str2
|
|
||||||
#endif
|
|
||||||
#define CAT(str1, str2) __CAT(str1, str2)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*
|
|
||||||
* PIC specific declarations
|
|
||||||
* Not used for the kernel but here seems to be the right place.
|
|
||||||
*/
|
|
||||||
#ifdef __PIC__
|
|
||||||
#define CPRESTORE(register) \
|
|
||||||
.cprestore register
|
|
||||||
#define CPADD(register) \
|
|
||||||
.cpadd register
|
|
||||||
#define CPLOAD(register) \
|
|
||||||
.cpload register
|
|
||||||
#else
|
|
||||||
#define CPRESTORE(register)
|
|
||||||
#define CPADD(register)
|
|
||||||
#define CPLOAD(register)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define ENTRY(symbol) \
|
#define ENTRY(symbol) \
|
||||||
.globl symbol; \
|
.globl symbol; \
|
||||||
.type symbol, @function; \
|
.type symbol, @function; \
|
||||||
.ent symbol, 0; \
|
.ent symbol, 0; \
|
||||||
symbol:
|
symbol: .cfi_startproc; \
|
||||||
|
.insn
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* LEAF - declare leaf routine
|
* LEAF - declare leaf routine
|
||||||
|
@ -57,7 +32,9 @@ symbol:
|
||||||
.type symbol, @function; \
|
.type symbol, @function; \
|
||||||
.ent symbol, 0; \
|
.ent symbol, 0; \
|
||||||
.section .text.symbol, "x"; \
|
.section .text.symbol, "x"; \
|
||||||
symbol: .frame sp, 0, ra
|
symbol: .frame sp, 0, ra; \
|
||||||
|
.cfi_startproc; \
|
||||||
|
.insn
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* NESTED - declare nested routine entry point
|
* NESTED - declare nested routine entry point
|
||||||
|
@ -68,12 +45,15 @@ symbol: .frame sp, 0, ra
|
||||||
.type symbol, @function; \
|
.type symbol, @function; \
|
||||||
.ent symbol, 0; \
|
.ent symbol, 0; \
|
||||||
.section .text.symbol, "x"; \
|
.section .text.symbol, "x"; \
|
||||||
symbol: .frame sp, framesize, rpc
|
symbol: .frame sp, framesize, rpc; \
|
||||||
|
.cfi_startproc; \
|
||||||
|
.insn
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* END - mark end of function
|
* END - mark end of function
|
||||||
*/
|
*/
|
||||||
#define END(function) \
|
#define END(function) \
|
||||||
|
.cfi_endproc; \
|
||||||
.end function; \
|
.end function; \
|
||||||
.size function, .-function
|
.size function, .-function
|
||||||
|
|
||||||
|
@ -90,7 +70,7 @@ symbol:
|
||||||
#define FEXPORT(symbol) \
|
#define FEXPORT(symbol) \
|
||||||
.globl symbol; \
|
.globl symbol; \
|
||||||
.type symbol, @function; \
|
.type symbol, @function; \
|
||||||
symbol:
|
symbol: .insn
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* ABS - export absolute symbol
|
* ABS - export absolute symbol
|
||||||
|
@ -128,96 +108,6 @@ symbol = value
|
||||||
8: .asciiz msg; \
|
8: .asciiz msg; \
|
||||||
.popsection;
|
.popsection;
|
||||||
|
|
||||||
/*
|
|
||||||
* Build text tables
|
|
||||||
*/
|
|
||||||
#define TTABLE(string) \
|
|
||||||
.pushsection .text; \
|
|
||||||
.word 1f; \
|
|
||||||
.popsection \
|
|
||||||
.pushsection .data; \
|
|
||||||
1: .asciiz string; \
|
|
||||||
.popsection
|
|
||||||
|
|
||||||
/*
|
|
||||||
* MIPS IV pref instruction.
|
|
||||||
* Use with .set noreorder only!
|
|
||||||
*
|
|
||||||
* MIPS IV implementations are free to treat this as a nop. The R5000
|
|
||||||
* is one of them. So we should have an option not to use this instruction.
|
|
||||||
*/
|
|
||||||
#ifdef CONFIG_CPU_HAS_PREFETCH
|
|
||||||
|
|
||||||
#define PREF(hint, addr) \
|
|
||||||
.set push; \
|
|
||||||
.set arch=r5000; \
|
|
||||||
pref hint, addr; \
|
|
||||||
.set pop
|
|
||||||
|
|
||||||
#define PREFE(hint, addr) \
|
|
||||||
.set push; \
|
|
||||||
.set mips0; \
|
|
||||||
.set eva; \
|
|
||||||
prefe hint, addr; \
|
|
||||||
.set pop
|
|
||||||
|
|
||||||
#define PREFX(hint, addr) \
|
|
||||||
.set push; \
|
|
||||||
.set arch=r5000; \
|
|
||||||
prefx hint, addr; \
|
|
||||||
.set pop
|
|
||||||
|
|
||||||
#else /* !CONFIG_CPU_HAS_PREFETCH */
|
|
||||||
|
|
||||||
#define PREF(hint, addr)
|
|
||||||
#define PREFE(hint, addr)
|
|
||||||
#define PREFX(hint, addr)
|
|
||||||
|
|
||||||
#endif /* !CONFIG_CPU_HAS_PREFETCH */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
|
|
||||||
*/
|
|
||||||
#if (_MIPS_ISA == _MIPS_ISA_MIPS1)
|
|
||||||
#define MOVN(rd, rs, rt) \
|
|
||||||
.set push; \
|
|
||||||
.set reorder; \
|
|
||||||
beqz rt, 9f; \
|
|
||||||
move rd, rs; \
|
|
||||||
.set pop; \
|
|
||||||
9:
|
|
||||||
#define MOVZ(rd, rs, rt) \
|
|
||||||
.set push; \
|
|
||||||
.set reorder; \
|
|
||||||
bnez rt, 9f; \
|
|
||||||
move rd, rs; \
|
|
||||||
.set pop; \
|
|
||||||
9:
|
|
||||||
#endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */
|
|
||||||
#if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3)
|
|
||||||
#define MOVN(rd, rs, rt) \
|
|
||||||
.set push; \
|
|
||||||
.set noreorder; \
|
|
||||||
bnezl rt, 9f; \
|
|
||||||
move rd, rs; \
|
|
||||||
.set pop; \
|
|
||||||
9:
|
|
||||||
#define MOVZ(rd, rs, rt) \
|
|
||||||
.set push; \
|
|
||||||
.set noreorder; \
|
|
||||||
beqzl rt, 9f; \
|
|
||||||
move rd, rs; \
|
|
||||||
.set pop; \
|
|
||||||
9:
|
|
||||||
#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
|
|
||||||
#if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
|
|
||||||
(_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
|
|
||||||
#define MOVN(rd, rs, rt) \
|
|
||||||
movn rd, rs, rt
|
|
||||||
#define MOVZ(rd, rs, rt) \
|
|
||||||
movz rd, rs, rt
|
|
||||||
#endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Stack alignment
|
* Stack alignment
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -41,6 +41,7 @@
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
#include <linux/bitops.h>
|
#include <linux/bitops.h>
|
||||||
|
|
||||||
|
#if CONFIG_IS_ENABLED(MIPS_CM)
|
||||||
static inline void *mips_cm_base(void)
|
static inline void *mips_cm_base(void)
|
||||||
{
|
{
|
||||||
return (void *)CKSEG1ADDR(CONFIG_MIPS_CM_BASE);
|
return (void *)CKSEG1ADDR(CONFIG_MIPS_CM_BASE);
|
||||||
|
@ -56,6 +57,17 @@ static inline unsigned long mips_cm_l2_line_size(void)
|
||||||
line_sz &= GENMASK(GCR_L2_CONFIG_LINESZ_BITS - 1, 0);
|
line_sz &= GENMASK(GCR_L2_CONFIG_LINESZ_BITS - 1, 0);
|
||||||
return line_sz ? (2 << line_sz) : 0;
|
return line_sz ? (2 << line_sz) : 0;
|
||||||
}
|
}
|
||||||
|
#else
|
||||||
|
static inline void *mips_cm_base(void)
|
||||||
|
{
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline unsigned long mips_cm_l2_line_size(void)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
#endif /* !__ASSEMBLY__ */
|
#endif /* !__ASSEMBLY__ */
|
||||||
|
|
||||||
|
|
69
arch/mips/include/asm/compiler.h
Normal file
69
arch/mips/include/asm/compiler.h
Normal file
|
@ -0,0 +1,69 @@
|
||||||
|
/* SPDX-License-Identifier: GPL-2.0 */
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2004, 2007 Maciej W. Rozycki
|
||||||
|
*
|
||||||
|
* This file is subject to the terms and conditions of the GNU General Public
|
||||||
|
* License. See the file "COPYING" in the main directory of this archive
|
||||||
|
* for more details.
|
||||||
|
*/
|
||||||
|
#ifndef _ASM_COMPILER_H
|
||||||
|
#define _ASM_COMPILER_H
|
||||||
|
|
||||||
|
/*
|
||||||
|
* With GCC 4.5 onwards we can use __builtin_unreachable to indicate to the
|
||||||
|
* compiler that a particular code path will never be hit. This allows it to be
|
||||||
|
* optimised out of the generated binary.
|
||||||
|
*
|
||||||
|
* Unfortunately at least GCC 4.6.3 through 7.3.0 inclusive suffer from a bug
|
||||||
|
* that can lead to instructions from beyond an unreachable statement being
|
||||||
|
* incorrectly reordered into earlier delay slots if the unreachable statement
|
||||||
|
* is the only content of a case in a switch statement. This can lead to
|
||||||
|
* seemingly random behaviour, such as invalid memory accesses from incorrectly
|
||||||
|
* reordered loads or stores. See this potential GCC fix for details:
|
||||||
|
*
|
||||||
|
* https://gcc.gnu.org/ml/gcc-patches/2015-09/msg00360.html
|
||||||
|
*
|
||||||
|
* It is unclear whether GCC 8 onwards suffer from the same issue - nothing
|
||||||
|
* relevant is mentioned in GCC 8 release notes and nothing obviously relevant
|
||||||
|
* stands out in GCC commit logs, but these newer GCC versions generate very
|
||||||
|
* different code for the testcase which doesn't exhibit the bug.
|
||||||
|
*
|
||||||
|
* GCC also handles stack allocation suboptimally when calling noreturn
|
||||||
|
* functions or calling __builtin_unreachable():
|
||||||
|
*
|
||||||
|
* https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82365
|
||||||
|
*
|
||||||
|
* We work around both of these issues by placing a volatile asm statement,
|
||||||
|
* which GCC is prevented from reordering past, prior to __builtin_unreachable
|
||||||
|
* calls.
|
||||||
|
*
|
||||||
|
* The .insn statement is required to ensure that any branches to the
|
||||||
|
* statement, which sadly must be kept due to the asm statement, are known to
|
||||||
|
* be branches to code and satisfy linker requirements for microMIPS kernels.
|
||||||
|
*/
|
||||||
|
#undef barrier_before_unreachable
|
||||||
|
#define barrier_before_unreachable() asm volatile(".insn")
|
||||||
|
|
||||||
|
#if !defined(CONFIG_CC_IS_GCC) || \
|
||||||
|
(__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 9)
|
||||||
|
# define GCC_OFF_SMALL_ASM() "ZC"
|
||||||
|
#elif defined(CONFIG_CPU_MICROMIPS)
|
||||||
|
# error "microMIPS compilation unsupported with GCC older than 4.9"
|
||||||
|
#else
|
||||||
|
# define GCC_OFF_SMALL_ASM() "R"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_CPU_MIPSR6
|
||||||
|
#define MIPS_ISA_LEVEL "mips64r6"
|
||||||
|
#define MIPS_ISA_ARCH_LEVEL MIPS_ISA_LEVEL
|
||||||
|
#define MIPS_ISA_LEVEL_RAW mips64r6
|
||||||
|
#define MIPS_ISA_ARCH_LEVEL_RAW MIPS_ISA_LEVEL_RAW
|
||||||
|
#else
|
||||||
|
/* MIPS64 is a superset of MIPS32 */
|
||||||
|
#define MIPS_ISA_LEVEL "mips64r2"
|
||||||
|
#define MIPS_ISA_ARCH_LEVEL "arch=r4000"
|
||||||
|
#define MIPS_ISA_LEVEL_RAW mips64r2
|
||||||
|
#define MIPS_ISA_ARCH_LEVEL_RAW MIPS_ISA_LEVEL_RAW
|
||||||
|
#endif /* CONFIG_CPU_MIPSR6 */
|
||||||
|
|
||||||
|
#endif /* _ASM_COMPILER_H */
|
24
arch/mips/include/asm/isa-rev.h
Normal file
24
arch/mips/include/asm/isa-rev.h
Normal file
|
@ -0,0 +1,24 @@
|
||||||
|
/* SPDX-License-Identifier: GPL-2.0 */
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2018 MIPS Tech, LLC
|
||||||
|
* Author: Matt Redfearn <matt.redfearn@mips.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __MIPS_ASM_ISA_REV_H__
|
||||||
|
#define __MIPS_ASM_ISA_REV_H__
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The ISA revision level. This is 0 for MIPS I to V and N for
|
||||||
|
* MIPS{32,64}rN.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* If the compiler has defined __mips_isa_rev, believe it. */
|
||||||
|
#ifdef __mips_isa_rev
|
||||||
|
#define MIPS_ISA_REV __mips_isa_rev
|
||||||
|
#else
|
||||||
|
/* The compiler hasn't defined the isa rev so assume it's MIPS I - V (0) */
|
||||||
|
#define MIPS_ISA_REV 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* __MIPS_ASM_ISA_REV_H__ */
|
File diff suppressed because it is too large
Load Diff
|
@ -8,7 +8,7 @@
|
||||||
#ifndef __ASM_MIPS_RELOCS_H__
|
#ifndef __ASM_MIPS_RELOCS_H__
|
||||||
#define __ASM_MIPS_RELOCS_H__
|
#define __ASM_MIPS_RELOCS_H__
|
||||||
|
|
||||||
#define R_MIPS_NONE 0
|
#define R_MIPS_NONE 0xbeef7531
|
||||||
#define R_MIPS_32 2
|
#define R_MIPS_32 2
|
||||||
#define R_MIPS_26 4
|
#define R_MIPS_26 4
|
||||||
#define R_MIPS_HI16 5
|
#define R_MIPS_HI16 5
|
||||||
|
|
|
@ -51,7 +51,7 @@ void arch_lmb_reserve(struct lmb *lmb)
|
||||||
static void linux_cmdline_init(void)
|
static void linux_cmdline_init(void)
|
||||||
{
|
{
|
||||||
linux_argc = 1;
|
linux_argc = 1;
|
||||||
linux_argv = (char **)UNCACHED_SDRAM(gd->bd->bi_boot_params);
|
linux_argv = (char **)CKSEG1ADDR(gd->bd->bi_boot_params);
|
||||||
linux_argv[0] = 0;
|
linux_argv[0] = 0;
|
||||||
linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS);
|
linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS);
|
||||||
}
|
}
|
||||||
|
@ -186,7 +186,7 @@ static void linux_env_legacy(bootm_headers_t *images)
|
||||||
(ulong)(gd->ram_size >> 20));
|
(ulong)(gd->ram_size >> 20));
|
||||||
}
|
}
|
||||||
|
|
||||||
rd_start = UNCACHED_SDRAM(images->initrd_start);
|
rd_start = CKSEG1ADDR(images->initrd_start);
|
||||||
rd_size = images->initrd_end - images->initrd_start;
|
rd_size = images->initrd_end - images->initrd_start;
|
||||||
|
|
||||||
linux_env_init();
|
linux_env_init();
|
||||||
|
|
|
@ -8,9 +8,7 @@
|
||||||
#include <cpu_func.h>
|
#include <cpu_func.h>
|
||||||
#include <asm/cache.h>
|
#include <asm/cache.h>
|
||||||
#include <asm/cacheops.h>
|
#include <asm/cacheops.h>
|
||||||
#ifdef CONFIG_MIPS_L2_CACHE
|
|
||||||
#include <asm/cm.h>
|
#include <asm/cm.h>
|
||||||
#endif
|
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
#include <asm/mipsregs.h>
|
#include <asm/mipsregs.h>
|
||||||
#include <asm/system.h>
|
#include <asm/system.h>
|
||||||
|
@ -109,7 +107,7 @@ static inline unsigned long scache_line_size(void)
|
||||||
} \
|
} \
|
||||||
} while (0)
|
} while (0)
|
||||||
|
|
||||||
void flush_cache(ulong start_addr, ulong size)
|
void __weak flush_cache(ulong start_addr, ulong size)
|
||||||
{
|
{
|
||||||
unsigned long ilsize = icache_line_size();
|
unsigned long ilsize = icache_line_size();
|
||||||
unsigned long dlsize = dcache_line_size();
|
unsigned long dlsize = dcache_line_size();
|
||||||
|
@ -161,7 +159,7 @@ void __weak flush_dcache_range(ulong start_addr, ulong stop)
|
||||||
sync();
|
sync();
|
||||||
}
|
}
|
||||||
|
|
||||||
void invalidate_dcache_range(ulong start_addr, ulong stop)
|
void __weak invalidate_dcache_range(ulong start_addr, ulong stop)
|
||||||
{
|
{
|
||||||
unsigned long lsize = dcache_line_size();
|
unsigned long lsize = dcache_line_size();
|
||||||
unsigned long slsize = scache_line_size();
|
unsigned long slsize = scache_line_size();
|
||||||
|
|
|
@ -79,6 +79,21 @@
|
||||||
.set pop
|
.set pop
|
||||||
.endm
|
.endm
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The changing of Kernel mode cacheability must be done from KSEG1.
|
||||||
|
* If the code is executing from KSEG0, jump to KSEG1 during the execution
|
||||||
|
* of change_k0_cca. change_k0_cca itself clears all hazards when returning.
|
||||||
|
*/
|
||||||
|
.macro change_k0_cca_kseg1 mode
|
||||||
|
PTR_LA t0, change_k0_cca
|
||||||
|
li t1, CPHYSADDR(~0)
|
||||||
|
and t0, t0, t1
|
||||||
|
PTR_LI t1, CKSEG1
|
||||||
|
or t0, t0, t1
|
||||||
|
li a0, \mode
|
||||||
|
jalr t0
|
||||||
|
.endm
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* mips_cache_reset - low level initialisation of the primary caches
|
* mips_cache_reset - low level initialisation of the primary caches
|
||||||
*
|
*
|
||||||
|
@ -317,18 +332,9 @@ l1_init:
|
||||||
sync
|
sync
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Enable use of the I-cache by setting Config.K0. The code for this
|
* Enable use of the I-cache by setting Config.K0.
|
||||||
* must be executed from KSEG1. Jump from KSEG0 to KSEG1 to do this.
|
|
||||||
* Jump back to KSEG0 after caches are enabled and insert an
|
|
||||||
* instruction hazard barrier.
|
|
||||||
*/
|
*/
|
||||||
PTR_LA t0, change_k0_cca
|
change_k0_cca_kseg1 CONF_CM_CACHABLE_NONCOHERENT
|
||||||
li t1, CPHYSADDR(~0)
|
|
||||||
and t0, t0, t1
|
|
||||||
PTR_LI t1, CKSEG1
|
|
||||||
or t0, t0, t1
|
|
||||||
li a0, CONF_CM_CACHABLE_NONCOHERENT
|
|
||||||
jalr.hb t0
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* then initialize D-cache.
|
* then initialize D-cache.
|
||||||
|
@ -388,9 +394,7 @@ l2_unbypass:
|
||||||
beqz t0, 2f
|
beqz t0, 2f
|
||||||
|
|
||||||
/* Change Config.K0 to a coherent CCA */
|
/* Change Config.K0 to a coherent CCA */
|
||||||
PTR_LA t0, change_k0_cca
|
change_k0_cca_kseg1 CONF_CM_CACHABLE_COW
|
||||||
li a0, CONF_CM_CACHABLE_COW
|
|
||||||
jalr t0
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Join the coherent domain such that the caches of this core are kept
|
* Join the coherent domain such that the caches of this core are kept
|
||||||
|
@ -414,6 +418,12 @@ return:
|
||||||
jr R_RETURN
|
jr R_RETURN
|
||||||
END(mips_cache_reset)
|
END(mips_cache_reset)
|
||||||
|
|
||||||
|
LEAF(mips_cache_disable)
|
||||||
|
move R_RETURN, ra
|
||||||
|
change_k0_cca_kseg1 CONF_CM_UNCACHED
|
||||||
|
jr R_RETURN
|
||||||
|
END(mips_cache_disable)
|
||||||
|
|
||||||
LEAF(change_k0_cca)
|
LEAF(change_k0_cca)
|
||||||
mfc0 t0, CP0_CONFIG
|
mfc0 t0, CP0_CONFIG
|
||||||
#if __mips_isa_rev >= 2
|
#if __mips_isa_rev >= 2
|
||||||
|
|
|
@ -67,7 +67,7 @@ static unsigned long read_uint(uint8_t **buf)
|
||||||
* intentionally simple, and does the bare minimum needed to fixup the
|
* intentionally simple, and does the bare minimum needed to fixup the
|
||||||
* relocated U-Boot - in particular, it does not check for overflows.
|
* relocated U-Boot - in particular, it does not check for overflows.
|
||||||
*/
|
*/
|
||||||
static void apply_reloc(unsigned int type, void *addr, long off)
|
static void apply_reloc(unsigned int type, void *addr, long off, uint8_t *buf)
|
||||||
{
|
{
|
||||||
uint32_t u32;
|
uint32_t u32;
|
||||||
|
|
||||||
|
@ -92,7 +92,8 @@ static void apply_reloc(unsigned int type, void *addr, long off)
|
||||||
break;
|
break;
|
||||||
|
|
||||||
default:
|
default:
|
||||||
panic("Unhandled reloc type %u\n", type);
|
panic("Unhandled reloc type %u (@ %p), bss used before relocation?\n",
|
||||||
|
type, buf);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -137,7 +138,7 @@ void relocate_code(ulong start_addr_sp, gd_t *new_gd, ulong relocaddr)
|
||||||
break;
|
break;
|
||||||
|
|
||||||
addr += read_uint(&buf) << 2;
|
addr += read_uint(&buf) << 2;
|
||||||
apply_reloc(type, (void *)addr, off);
|
apply_reloc(type, (void *)addr, off, buf);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Ensure the icache is coherent */
|
/* Ensure the icache is coherent */
|
||||||
|
|
|
@ -108,6 +108,10 @@ void trap_init(ulong reloc_addr)
|
||||||
|
|
||||||
saved_ebase = read_c0_ebase() & 0xfffff000;
|
saved_ebase = read_c0_ebase() & 0xfffff000;
|
||||||
|
|
||||||
|
/* Set WG bit on Octeon to enable writing to bits 63:30 */
|
||||||
|
if (IS_ENABLED(CONFIG_ARCH_OCTEON))
|
||||||
|
ebase |= MIPS_EBASE_WG;
|
||||||
|
|
||||||
write_c0_ebase(ebase);
|
write_c0_ebase(ebase);
|
||||||
clear_c0_status(ST0_BEV);
|
clear_c0_status(ST0_BEV);
|
||||||
execution_hazard_barrier();
|
execution_hazard_barrier();
|
||||||
|
|
60
arch/mips/mach-octeon/Kconfig
Normal file
60
arch/mips/mach-octeon/Kconfig
Normal file
|
@ -0,0 +1,60 @@
|
||||||
|
menu "Octeon platforms"
|
||||||
|
depends on ARCH_OCTEON
|
||||||
|
|
||||||
|
config SYS_SOC
|
||||||
|
string
|
||||||
|
default "octeon"
|
||||||
|
|
||||||
|
config OCTEON_CN7XXX
|
||||||
|
bool "Octeon CN7XXX SoC"
|
||||||
|
|
||||||
|
config OCTEON_CN70XX
|
||||||
|
bool "Octeon CN70XX SoC"
|
||||||
|
select OCTEON_CN7XXX
|
||||||
|
|
||||||
|
config OCTEON_CN73XX
|
||||||
|
bool "Octeon CN73XX SoC"
|
||||||
|
select OCTEON_CN7XXX
|
||||||
|
|
||||||
|
config OCTEON_CN78XX
|
||||||
|
bool "Octeon CN78XX SoC"
|
||||||
|
select OCTEON_CN7XXX
|
||||||
|
|
||||||
|
choice
|
||||||
|
prompt "Octeon MIPS family select"
|
||||||
|
|
||||||
|
config SOC_OCTEON3
|
||||||
|
bool "Octeon III family"
|
||||||
|
help
|
||||||
|
This selects the Octeon III SoC family CN70xx, CN73XX, CN78xx
|
||||||
|
and CNF75XX.
|
||||||
|
|
||||||
|
endchoice
|
||||||
|
|
||||||
|
choice
|
||||||
|
prompt "Octeon 3 board select"
|
||||||
|
default TARGET_OCTEON_EBB7304
|
||||||
|
|
||||||
|
config TARGET_OCTEON_EBB7304
|
||||||
|
bool "Marvell Octeon EBB7304"
|
||||||
|
select OCTEON_CN73XX
|
||||||
|
help
|
||||||
|
Choose this for the Octeon EBB7304 board
|
||||||
|
|
||||||
|
endchoice
|
||||||
|
|
||||||
|
config SYS_DCACHE_SIZE
|
||||||
|
default 32768
|
||||||
|
|
||||||
|
config SYS_DCACHE_LINE_SIZE
|
||||||
|
default 128
|
||||||
|
|
||||||
|
config SYS_ICACHE_SIZE
|
||||||
|
default 79872
|
||||||
|
|
||||||
|
config SYS_ICACHE_LINE_SIZE
|
||||||
|
default 128
|
||||||
|
|
||||||
|
source "board/Marvell/octeon_ebb7304/Kconfig"
|
||||||
|
|
||||||
|
endmenu
|
10
arch/mips/mach-octeon/Makefile
Normal file
10
arch/mips/mach-octeon/Makefile
Normal file
|
@ -0,0 +1,10 @@
|
||||||
|
# (C) Copyright 2019 Marvell, Inc.
|
||||||
|
#
|
||||||
|
# SPDX-License-Identifier: GPL-2.0+
|
||||||
|
#
|
||||||
|
|
||||||
|
obj-y += lowlevel_init.o
|
||||||
|
obj-y += cache.o
|
||||||
|
obj-y += clock.o
|
||||||
|
obj-y += cpu.o
|
||||||
|
obj-y += dram.o
|
24
arch/mips/mach-octeon/cache.c
Normal file
24
arch/mips/mach-octeon/cache.c
Normal file
|
@ -0,0 +1,24 @@
|
||||||
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2020 Marvell International Ltd.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <cpu_func.h>
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The Octeon platform is cache coherent and cache flushes and invalidates
|
||||||
|
* are not needed. Define some platform specific empty flush_foo()
|
||||||
|
* functions here to overwrite the _weak common function as a no-op.
|
||||||
|
* This effectively disables all cache operations.
|
||||||
|
*/
|
||||||
|
void flush_dcache_range(ulong start_addr, ulong stop)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
void flush_cache(ulong start_addr, ulong size)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
void invalidate_dcache_range(ulong start_addr, ulong stop)
|
||||||
|
{
|
||||||
|
}
|
14
arch/mips/mach-octeon/clock.c
Normal file
14
arch/mips/mach-octeon/clock.c
Normal file
|
@ -0,0 +1,14 @@
|
||||||
|
// SPDX-License-Identifier: GPL-2.0
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2018, 2019 Marvell International Ltd.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <asm/global_data.h>
|
||||||
|
#include <mach/clock.h>
|
||||||
|
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
|
ulong notrace get_tbclk(void)
|
||||||
|
{
|
||||||
|
return gd->cpu_clk;
|
||||||
|
}
|
66
arch/mips/mach-octeon/cpu.c
Normal file
66
arch/mips/mach-octeon/cpu.c
Normal file
|
@ -0,0 +1,66 @@
|
||||||
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2020 Marvell International Ltd.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <asm/global_data.h>
|
||||||
|
#include <linux/bitfield.h>
|
||||||
|
#include <linux/bitops.h>
|
||||||
|
#include <linux/compat.h>
|
||||||
|
#include <linux/io.h>
|
||||||
|
#include <mach/clock.h>
|
||||||
|
#include <mach/cavm-reg.h>
|
||||||
|
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
|
static int get_clocks(void)
|
||||||
|
{
|
||||||
|
const u64 ref_clock = PLL_REF_CLK;
|
||||||
|
void __iomem *rst_boot;
|
||||||
|
u64 val;
|
||||||
|
|
||||||
|
rst_boot = ioremap(CAVM_RST_BOOT, 0);
|
||||||
|
val = ioread64(rst_boot);
|
||||||
|
gd->cpu_clk = ref_clock * FIELD_GET(RST_BOOT_C_MUL, val);
|
||||||
|
gd->bus_clk = ref_clock * FIELD_GET(RST_BOOT_PNR_MUL, val);
|
||||||
|
|
||||||
|
debug("%s: cpu: %lu, bus: %lu\n", __func__, gd->cpu_clk, gd->bus_clk);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Early mach init code run from flash */
|
||||||
|
int mach_cpu_init(void)
|
||||||
|
{
|
||||||
|
void __iomem *mio_boot_reg_cfg0;
|
||||||
|
|
||||||
|
/* Remap boot-bus 0x1fc0.0000 -> 0x1f40.0000 */
|
||||||
|
/* ToDo: Move this to an early running bus (bootbus) DM driver */
|
||||||
|
mio_boot_reg_cfg0 = ioremap(CAVM_MIO_BOOT_REG_CFG0, 0);
|
||||||
|
clrsetbits_be64(mio_boot_reg_cfg0, 0xffff, 0x1f40);
|
||||||
|
|
||||||
|
/* Get clocks and store them in GD */
|
||||||
|
get_clocks();
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Returns number of cores
|
||||||
|
*
|
||||||
|
* @return number of CPU cores for the specified node
|
||||||
|
*/
|
||||||
|
static int cavm_octeon_num_cores(void)
|
||||||
|
{
|
||||||
|
void __iomem *ciu_fuse;
|
||||||
|
|
||||||
|
ciu_fuse = ioremap(CAVM_CIU_FUSE, 0);
|
||||||
|
return fls64(ioread64(ciu_fuse) & 0xffffffffffff);
|
||||||
|
}
|
||||||
|
|
||||||
|
int print_cpuinfo(void)
|
||||||
|
{
|
||||||
|
printf("SoC: Octeon CN73xx (%d cores)\n", cavm_octeon_num_cores());
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
28
arch/mips/mach-octeon/dram.c
Normal file
28
arch/mips/mach-octeon/dram.c
Normal file
|
@ -0,0 +1,28 @@
|
||||||
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
|
/*
|
||||||
|
* Copyright (C) Stefan Roese <sr@denx.de>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <dm.h>
|
||||||
|
#include <ram.h>
|
||||||
|
#include <asm/global_data.h>
|
||||||
|
#include <linux/compat.h>
|
||||||
|
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
|
int dram_init(void)
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
* No DDR init yet -> run in L2 cache
|
||||||
|
*/
|
||||||
|
gd->ram_size = (4 << 20);
|
||||||
|
gd->bd->bi_dram[0].size = gd->ram_size;
|
||||||
|
gd->bd->bi_dram[1].size = 0;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
ulong board_get_usable_ram_top(ulong total_size)
|
||||||
|
{
|
||||||
|
return gd->ram_top;
|
||||||
|
}
|
30
arch/mips/mach-octeon/include/ioremap.h
Normal file
30
arch/mips/mach-octeon/include/ioremap.h
Normal file
|
@ -0,0 +1,30 @@
|
||||||
|
/* SPDX-License-Identifier: GPL-2.0 */
|
||||||
|
#ifndef __ASM_MACH_OCTEON_IOREMAP_H
|
||||||
|
#define __ASM_MACH_OCTEON_IOREMAP_H
|
||||||
|
|
||||||
|
#include <linux/types.h>
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Allow physical addresses to be fixed up to help peripherals located
|
||||||
|
* outside the low 32-bit range -- generic pass-through version.
|
||||||
|
*/
|
||||||
|
static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr,
|
||||||
|
phys_addr_t size)
|
||||||
|
{
|
||||||
|
return phys_addr;
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
|
||||||
|
unsigned long flags)
|
||||||
|
{
|
||||||
|
return (void __iomem *)(XKPHYS | offset);
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline int plat_iounmap(const volatile void __iomem *addr)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
#define _page_cachable_default _CACHE_CACHABLE_NONCOHERENT
|
||||||
|
|
||||||
|
#endif /* __ASM_MACH_OCTEON_IOREMAP_H */
|
17
arch/mips/mach-octeon/include/mach/cavm-reg.h
Normal file
17
arch/mips/mach-octeon/include/mach/cavm-reg.h
Normal file
|
@ -0,0 +1,17 @@
|
||||||
|
/* SPDX-License-Identifier: GPL-2.0 */
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2020 Marvell International Ltd.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CAVM_REG_H__
|
||||||
|
|
||||||
|
/* Register offsets */
|
||||||
|
#define CAVM_CIU_FUSE 0x00010100000001a0
|
||||||
|
#define CAVM_MIO_BOOT_REG_CFG0 0x0001180000000000
|
||||||
|
#define CAVM_RST_BOOT 0x0001180006001600
|
||||||
|
|
||||||
|
/* Register bits */
|
||||||
|
#define RST_BOOT_C_MUL GENMASK_ULL(36, 30)
|
||||||
|
#define RST_BOOT_PNR_MUL GENMASK_ULL(29, 24)
|
||||||
|
|
||||||
|
#endif /* __CAVM_REG_H__ */
|
12
arch/mips/mach-octeon/include/mach/clock.h
Normal file
12
arch/mips/mach-octeon/include/mach/clock.h
Normal file
|
@ -0,0 +1,12 @@
|
||||||
|
/* SPDX-License-Identifier: GPL-2.0 */
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2018, 2019 Marvell International Ltd.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CLOCK_H__
|
||||||
|
|
||||||
|
/** System PLL reference clock */
|
||||||
|
#define PLL_REF_CLK 50000000 /* 50 MHz */
|
||||||
|
#define NS_PER_REF_CLK_TICK (1000000000 / PLL_REF_CLK)
|
||||||
|
|
||||||
|
#endif /* __CLOCK_H__ */
|
69
arch/mips/mach-octeon/lowlevel_init.S
Normal file
69
arch/mips/mach-octeon/lowlevel_init.S
Normal file
|
@ -0,0 +1,69 @@
|
||||||
|
/* SPDX-License-Identifier: GPL-2.0 */
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2020 Stefan Roese <sr@denx.de>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <config.h>
|
||||||
|
#include <asm-offsets.h>
|
||||||
|
#include <asm/cacheops.h>
|
||||||
|
#include <asm/regdef.h>
|
||||||
|
#include <asm/mipsregs.h>
|
||||||
|
#include <asm/addrspace.h>
|
||||||
|
#include <asm/asm.h>
|
||||||
|
|
||||||
|
.set noreorder
|
||||||
|
|
||||||
|
LEAF(lowlevel_init)
|
||||||
|
jr ra
|
||||||
|
nop
|
||||||
|
END(lowlevel_init)
|
||||||
|
|
||||||
|
LEAF(mips_mach_early_init)
|
||||||
|
|
||||||
|
move s0, ra
|
||||||
|
|
||||||
|
bal __dummy
|
||||||
|
nop
|
||||||
|
|
||||||
|
__dummy:
|
||||||
|
/* Get the actual address that we are running at */
|
||||||
|
PTR_LA a7, __dummy
|
||||||
|
dsubu t3, ra, a7 /* t3 now has reloc offset */
|
||||||
|
|
||||||
|
PTR_LA t1, _start
|
||||||
|
daddu t0, t1, t3 /* t0 now has actual address of _start */
|
||||||
|
|
||||||
|
/* Calculate end address of copy loop */
|
||||||
|
PTR_LA t2, _end
|
||||||
|
daddiu t2, t2, 0x4000 /* Increase size to include appended DTB */
|
||||||
|
daddiu t2, t2, 127
|
||||||
|
ins t2, zero, 0, 7 /* Round up to cache line for memcpy */
|
||||||
|
|
||||||
|
/* Copy ourself to the L2 cache from flash, 32 bytes at a time */
|
||||||
|
1:
|
||||||
|
ld a0, 0(t0)
|
||||||
|
ld a1, 8(t0)
|
||||||
|
ld a2, 16(t0)
|
||||||
|
ld a3, 24(t0)
|
||||||
|
sd a0, 0(t1)
|
||||||
|
sd a1, 8(t1)
|
||||||
|
sd a2, 16(t1)
|
||||||
|
sd a3, 24(t1)
|
||||||
|
addiu t0, 32
|
||||||
|
addiu t1, 32
|
||||||
|
bne t1, t2, 1b
|
||||||
|
nop
|
||||||
|
|
||||||
|
sync
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Return to start.S now running from TEXT_BASE, which points
|
||||||
|
* to DRAM address space, which effectively is L2 cache now.
|
||||||
|
* This speeds up the init process extremely, especially the
|
||||||
|
* DDR init code.
|
||||||
|
*/
|
||||||
|
dsubu s0, s0, t3 /* Fixup return address with reloc offset */
|
||||||
|
jr.hb s0 /* Jump back with hazard barrier */
|
||||||
|
nop
|
||||||
|
|
||||||
|
END(mips_mach_early_init)
|
19
board/Marvell/octeon_ebb7304/Kconfig
Normal file
19
board/Marvell/octeon_ebb7304/Kconfig
Normal file
|
@ -0,0 +1,19 @@
|
||||||
|
if TARGET_OCTEON_EBB7304
|
||||||
|
|
||||||
|
config SYS_BOARD
|
||||||
|
string
|
||||||
|
default "octeon_ebb7304"
|
||||||
|
|
||||||
|
config SYS_VENDOR
|
||||||
|
string
|
||||||
|
default "Marvell"
|
||||||
|
|
||||||
|
config SYS_CONFIG_NAME
|
||||||
|
string
|
||||||
|
default "octeon_ebb7304"
|
||||||
|
|
||||||
|
config DEFAULT_DEVICE_TREE
|
||||||
|
string
|
||||||
|
default "mrvl,octeon-ebb7304"
|
||||||
|
|
||||||
|
endif
|
7
board/Marvell/octeon_ebb7304/MAINTAINERS
Normal file
7
board/Marvell/octeon_ebb7304/MAINTAINERS
Normal file
|
@ -0,0 +1,7 @@
|
||||||
|
OCTEON_EBB7304 BOARD
|
||||||
|
M: Aaron Williams <awilliams@marvell.com>
|
||||||
|
S: Maintained
|
||||||
|
F: board/Marvell/octeon_ebb7304/*
|
||||||
|
F: configs/octeon_ebb7304_defconfig
|
||||||
|
F: include/configs/octeon_ebb7304.h
|
||||||
|
F: arch/mips/dts/mrvl,octeon-ebb7304.dts
|
8
board/Marvell/octeon_ebb7304/Makefile
Normal file
8
board/Marvell/octeon_ebb7304/Makefile
Normal file
|
@ -0,0 +1,8 @@
|
||||||
|
#
|
||||||
|
# Copyright (C) 2020 Stefan Roese <sr@denx.de>
|
||||||
|
# Copyright (C) 2019-2020 Marvell International Ltd.
|
||||||
|
#
|
||||||
|
# SPDX-License-Identifier: GPL-2.0+
|
||||||
|
#
|
||||||
|
|
||||||
|
obj-y := board.o
|
9
board/Marvell/octeon_ebb7304/board.c
Normal file
9
board/Marvell/octeon_ebb7304/board.c
Normal file
|
@ -0,0 +1,9 @@
|
||||||
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2020 Stefan Roese <sr@denx.de>
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Nothing included right now. Code will be added in follow-up
|
||||||
|
* patches.
|
||||||
|
*/
|
38
configs/octeon_ebb7304_defconfig
Normal file
38
configs/octeon_ebb7304_defconfig
Normal file
|
@ -0,0 +1,38 @@
|
||||||
|
CONFIG_MIPS=y
|
||||||
|
CONFIG_SYS_TEXT_BASE=0xffffffff80000000
|
||||||
|
CONFIG_SYS_MALLOC_F_LEN=0x4000
|
||||||
|
CONFIG_ENV_SIZE=0x2000
|
||||||
|
CONFIG_ENV_SECT_SIZE=0x10000
|
||||||
|
CONFIG_NR_DRAM_BANKS=2
|
||||||
|
CONFIG_DEBUG_UART_BASE=0x8001180000000800
|
||||||
|
CONFIG_DEBUG_UART_CLOCK=1200000000
|
||||||
|
CONFIG_ARCH_OCTEON=y
|
||||||
|
# CONFIG_MIPS_CACHE_SETUP is not set
|
||||||
|
# CONFIG_MIPS_CACHE_DISABLE is not set
|
||||||
|
CONFIG_DEBUG_UART=y
|
||||||
|
CONFIG_SYS_CONSOLE_INFO_QUIET=y
|
||||||
|
CONFIG_HUSH_PARSER=y
|
||||||
|
CONFIG_CMD_MTD=y
|
||||||
|
CONFIG_CMD_PCI=y
|
||||||
|
CONFIG_CMD_DHCP=y
|
||||||
|
CONFIG_CMD_PING=y
|
||||||
|
CONFIG_CMD_TIME=y
|
||||||
|
CONFIG_ENV_IS_IN_FLASH=y
|
||||||
|
CONFIG_ENV_ADDR=0x1FBFE000
|
||||||
|
CONFIG_CLK=y
|
||||||
|
# CONFIG_INPUT is not set
|
||||||
|
CONFIG_MTD=y
|
||||||
|
CONFIG_DM_MTD=y
|
||||||
|
CONFIG_MTD_NOR_FLASH=y
|
||||||
|
CONFIG_FLASH_CFI_DRIVER=y
|
||||||
|
CONFIG_CFI_FLASH=y
|
||||||
|
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||||
|
CONFIG_FLASH_CFI_MTD=y
|
||||||
|
CONFIG_SYS_FLASH_CFI=y
|
||||||
|
# CONFIG_NETDEVICES is not set
|
||||||
|
CONFIG_DEBUG_UART_SHIFT=3
|
||||||
|
CONFIG_DEBUG_UART_ANNOUNCE=y
|
||||||
|
CONFIG_SYS_NS16550=y
|
||||||
|
CONFIG_SYSRESET=y
|
||||||
|
CONFIG_SYSRESET_OCTEON=y
|
||||||
|
CONFIG_HEXDUMP=y
|
|
@ -57,6 +57,13 @@ config SYSRESET_MICROBLAZE
|
||||||
help
|
help
|
||||||
This is soft reset on Microblaze which does jump to 0x0 address.
|
This is soft reset on Microblaze which does jump to 0x0 address.
|
||||||
|
|
||||||
|
config SYSRESET_OCTEON
|
||||||
|
bool "Enable support for Marvell Octeon SoC family"
|
||||||
|
depends on ARCH_OCTEON
|
||||||
|
help
|
||||||
|
This enables the system reset driver support for Marvell Octeon
|
||||||
|
SoCs.
|
||||||
|
|
||||||
config SYSRESET_PSCI
|
config SYSRESET_PSCI
|
||||||
bool "Enable support for PSCI System Reset"
|
bool "Enable support for PSCI System Reset"
|
||||||
depends on ARM_PSCI_FW
|
depends on ARM_PSCI_FW
|
||||||
|
|
|
@ -10,6 +10,7 @@ obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
|
||||||
obj-$(CONFIG_SYSRESET_GPIO) += sysreset_gpio.o
|
obj-$(CONFIG_SYSRESET_GPIO) += sysreset_gpio.o
|
||||||
obj-$(CONFIG_SYSRESET_MPC83XX) += sysreset_mpc83xx.o
|
obj-$(CONFIG_SYSRESET_MPC83XX) += sysreset_mpc83xx.o
|
||||||
obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o
|
obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o
|
||||||
|
obj-$(CONFIG_SYSRESET_OCTEON) += sysreset_octeon.o
|
||||||
obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
|
obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
|
||||||
obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o
|
obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o
|
||||||
obj-$(CONFIG_SYSRESET_SOCFPGA_S10) += sysreset_socfpga_s10.o
|
obj-$(CONFIG_SYSRESET_SOCFPGA_S10) += sysreset_socfpga_s10.o
|
||||||
|
|
52
drivers/sysreset/sysreset_octeon.c
Normal file
52
drivers/sysreset/sysreset_octeon.c
Normal file
|
@ -0,0 +1,52 @@
|
||||||
|
// SPDX-License-Identifier: GPL-2.0
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2020 Stefan Roese <sr@denx.de>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
#include <dm.h>
|
||||||
|
#include <errno.h>
|
||||||
|
#include <sysreset.h>
|
||||||
|
#include <asm/io.h>
|
||||||
|
|
||||||
|
#define RST_SOFT_RST 0x0080
|
||||||
|
|
||||||
|
struct octeon_sysreset_data {
|
||||||
|
void __iomem *base;
|
||||||
|
};
|
||||||
|
|
||||||
|
static int octeon_sysreset_request(struct udevice *dev, enum sysreset_t type)
|
||||||
|
{
|
||||||
|
struct octeon_sysreset_data *data = dev_get_priv(dev);
|
||||||
|
|
||||||
|
writeq(1, data->base + RST_SOFT_RST);
|
||||||
|
|
||||||
|
return -EINPROGRESS;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int octeon_sysreset_probe(struct udevice *dev)
|
||||||
|
{
|
||||||
|
struct octeon_sysreset_data *data = dev_get_priv(dev);
|
||||||
|
|
||||||
|
data->base = dev_remap_addr(dev);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct sysreset_ops octeon_sysreset = {
|
||||||
|
.request = octeon_sysreset_request,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct udevice_id octeon_sysreset_ids[] = {
|
||||||
|
{ .compatible = "mrvl,cn7xxx-rst" },
|
||||||
|
{ }
|
||||||
|
};
|
||||||
|
|
||||||
|
U_BOOT_DRIVER(sysreset_octeon) = {
|
||||||
|
.id = UCLASS_SYSRESET,
|
||||||
|
.name = "octeon_sysreset",
|
||||||
|
.priv_auto_alloc_size = sizeof(struct octeon_sysreset_data),
|
||||||
|
.ops = &octeon_sysreset,
|
||||||
|
.probe = octeon_sysreset_probe,
|
||||||
|
.of_match = octeon_sysreset_ids,
|
||||||
|
};
|
19
include/configs/octeon_common.h
Normal file
19
include/configs/octeon_common.h
Normal file
|
@ -0,0 +1,19 @@
|
||||||
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2019-2020
|
||||||
|
* Marvell <www.marvell.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __OCTEON_COMMON_H__
|
||||||
|
#define __OCTEON_COMMON_H__
|
||||||
|
|
||||||
|
/* No DDR init yet -> run in L2 cache with limited resources */
|
||||||
|
#define CONFIG_SYS_MALLOC_LEN (256 << 10)
|
||||||
|
#define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000
|
||||||
|
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||||
|
|
||||||
|
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + (1 << 20))
|
||||||
|
|
||||||
|
#define CONFIG_SYS_INIT_SP_OFFSET 0x180000
|
||||||
|
|
||||||
|
#endif /* __OCTEON_COMMON_H__ */
|
20
include/configs/octeon_ebb7304.h
Normal file
20
include/configs/octeon_ebb7304.h
Normal file
|
@ -0,0 +1,20 @@
|
||||||
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2019-2020
|
||||||
|
* Marvell <www.marvell.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CONFIG_H__
|
||||||
|
#define __CONFIG_H__
|
||||||
|
|
||||||
|
#include "octeon_common.h"
|
||||||
|
|
||||||
|
/*
|
||||||
|
* CFI flash
|
||||||
|
*/
|
||||||
|
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
||||||
|
#define CONFIG_SYS_MAX_FLASH_SECT 256
|
||||||
|
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
|
||||||
|
#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
|
||||||
|
|
||||||
|
#endif /* __CONFIG_H__ */
|
|
@ -228,7 +228,6 @@ CONFIG_CPLD_BR_PRELIM
|
||||||
CONFIG_CPLD_OR_PRELIM
|
CONFIG_CPLD_OR_PRELIM
|
||||||
CONFIG_CPM2
|
CONFIG_CPM2
|
||||||
CONFIG_CPU_ARMV8
|
CONFIG_CPU_ARMV8
|
||||||
CONFIG_CPU_CAVIUM_OCTEON
|
|
||||||
CONFIG_CPU_FREQ_HZ
|
CONFIG_CPU_FREQ_HZ
|
||||||
CONFIG_CPU_HAS_LLSC
|
CONFIG_CPU_HAS_LLSC
|
||||||
CONFIG_CPU_HAS_PREFETCH
|
CONFIG_CPU_HAS_PREFETCH
|
||||||
|
|
Loading…
Reference in New Issue
Block a user