From 2c8811b75719b6b2c0dd071be1269b4ffcc776d6 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 8 Jan 2019 16:17:43 +0200 Subject: [PATCH 1/7] x86: edison: Switch to CONFIG_OF_SEPARATE There is no need for Intel Edison to have CONFIG_OF_EMBED to be enabled. Replace it with CONFIG_OF_SEPARATE. There is no functional change since u-boot.bin always contains DTB either embedded or attached. Signed-off-by: Andy Shevchenko Reviewed-by: Simon Glass Tested-by: Ferry Toth --- configs/edison_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/edison_defconfig b/configs/edison_defconfig index 234dbac4e8..8b6df817ed 100644 --- a/configs/edison_defconfig +++ b/configs/edison_defconfig @@ -25,7 +25,7 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y -CONFIG_OF_EMBED=y +CONFIG_OF_SEPARATE=y CONFIG_DEFAULT_DEVICE_TREE="edison" CONFIG_ENV_IS_IN_MMC=y CONFIG_CPU=y From 2436396a11a0b74742f3df330b4056b6a112bf01 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 8 Jan 2019 16:17:42 +0200 Subject: [PATCH 2/7] doc: Fix CONFIG_OF_SEPARATE description CONFIG_OF_SEPARATE description is not in align with actual code in Makefile and thus has misleading instructions and explanation. Make it aligned with the actual code. Signed-off-by: Andy Shevchenko Reviewed-by: Simon Glass --- doc/README.fdt-control | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/doc/README.fdt-control b/doc/README.fdt-control index 446401c9e9..e53cf51875 100644 --- a/doc/README.fdt-control +++ b/doc/README.fdt-control @@ -122,13 +122,14 @@ the U-Boot image (including u-boot.bin). This is suitable for debugging and development only and is not recommended for production devices. If CONFIG_OF_SEPARATE is defined, then it will be built and placed in -a u-boot.dtb file alongside u-boot.bin. A common approach is then to +a u-boot.dtb file alongside u-boot-nodtb.bin. A common approach is then to join the two: - cat u-boot.bin u-boot.dtb >image.bin + cat u-boot-nodtb.bin u-boot.dtb >image.bin and then flash image.bin onto your board. Note that U-Boot creates -u-boot-dtb.bin which does the above step for you also. If you are using +u-boot-dtb.bin which does the above step for you also. Resulting +u-boot.bin is a copy of u-boot-dtb.bin in this case. If you are using CONFIG_SPL_FRAMEWORK, then u-boot.img will be built to include the device tree binary. From ca7db866fead1d01ecf018343a99e3cd0d095d51 Mon Sep 17 00:00:00 2001 From: Bernhard Messerklinger Date: Mon, 7 Jan 2019 12:14:40 +0100 Subject: [PATCH 3/7] x86: tsc: Add support for native calibration of TSC freq Add native tsc calibration function. Calibrate the tsc timer the same way as linux does in arch/x86/kernel/tsc.c. Fixes booting for Apollo Lake processors. Signed-off-by: Bernhard Messerklinger Reviewed-by: Andy Shevchenko Reviewed-by: Bin Meng --- drivers/timer/tsc_timer.c | 55 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c index ba940ebf1c..919caba8a1 100644 --- a/drivers/timer/tsc_timer.c +++ b/drivers/timer/tsc_timer.c @@ -19,8 +19,59 @@ #define MAX_NUM_FREQS 9 +#define INTEL_FAM6_SKYLAKE_MOBILE 0x4E +#define INTEL_FAM6_ATOM_GOLDMONT 0x5C /* Apollo Lake */ +#define INTEL_FAM6_SKYLAKE_DESKTOP 0x5E +#define INTEL_FAM6_ATOM_GOLDMONT_X 0x5F /* Denverton */ +#define INTEL_FAM6_KABYLAKE_MOBILE 0x8E +#define INTEL_FAM6_KABYLAKE_DESKTOP 0x9E + DECLARE_GLOBAL_DATA_PTR; +/* + * native_calibrate_tsc + * Determine TSC frequency via CPUID, else return 0. + */ +static unsigned long native_calibrate_tsc(void) +{ + struct cpuid_result tsc_info; + unsigned int crystal_freq; + + if (gd->arch.x86_vendor != X86_VENDOR_INTEL) + return 0; + + if (cpuid_eax(0) < 0x15) + return 0; + + tsc_info = cpuid(0x15); + + if (tsc_info.ebx == 0 || tsc_info.eax == 0) + return 0; + + crystal_freq = tsc_info.ecx / 1000; + + if (!crystal_freq) { + switch (gd->arch.x86_model) { + case INTEL_FAM6_SKYLAKE_MOBILE: + case INTEL_FAM6_SKYLAKE_DESKTOP: + case INTEL_FAM6_KABYLAKE_MOBILE: + case INTEL_FAM6_KABYLAKE_DESKTOP: + crystal_freq = 24000; /* 24.0 MHz */ + break; + case INTEL_FAM6_ATOM_GOLDMONT_X: + crystal_freq = 25000; /* 25.0 MHz */ + break; + case INTEL_FAM6_ATOM_GOLDMONT: + crystal_freq = 19200; /* 19.2 MHz */ + break; + default: + return 0; + } + } + + return (crystal_freq * tsc_info.ebx / tsc_info.eax) / 1000; +} + static unsigned long cpu_mhz_from_cpuid(void) { if (gd->arch.x86_vendor != X86_VENDOR_INTEL) @@ -350,6 +401,10 @@ static void tsc_timer_ensure_setup(bool early) if (!gd->arch.clock_rate) { unsigned long fast_calibrate; + fast_calibrate = native_calibrate_tsc(); + if (fast_calibrate) + goto done; + fast_calibrate = cpu_mhz_from_cpuid(); if (fast_calibrate) goto done; From dbb0696ba05b6e201341805e0df0f5095bc43a78 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 31 Jan 2019 08:22:12 -0800 Subject: [PATCH 4/7] x86: Change 4-level page table base address to low memory At present the 4-level page table base address for 64-bit U-Boot proper is assigned an address that conflicts with CONFIG_LOADADDR. Change it to an address within the low memory range instead. Fixes crashes seen when 'dhcp' on QEMU x86_64 with "-net nic -net user,tftp=.,bootfile=u-boot". Reported-by: Alexander Graf Signed-off-by: Bin Meng Tested-by: Heinrich Schuchardt Reviewed-by: Simon Glass --- arch/x86/cpu/i386/cpu.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c index 208ef08562..af42431f45 100644 --- a/arch/x86/cpu/i386/cpu.c +++ b/arch/x86/cpu/i386/cpu.c @@ -462,6 +462,7 @@ int cpu_has_64bit(void) has_long_mode(); } +#define PAGETABLE_BASE 0x80000 #define PAGETABLE_SIZE (6 * 4096) /** @@ -523,10 +524,7 @@ int cpu_jump_to_64bit_uboot(ulong target) uint32_t *pgtable; func_t func; - /* TODO(sjg@chromium.org): Find a better place for this */ - pgtable = (uint32_t *)0x1000000; - if (!pgtable) - return -ENOMEM; + pgtable = (uint32_t *)PAGETABLE_BASE; build_pagetable(pgtable); From 916832603762847afcf112152473d305f7c502e3 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 31 Jan 2019 08:22:13 -0800 Subject: [PATCH 5/7] x86: Don't copy the cpu_call64() function to a hardcoded address Before jumping to 64-bit U-Boot proper, SPL copies the cpu_call64() function to a hardcoded address 0x3000000. This can have potential conflicts with application usage. Switch the destination address to be allocated from the heap to avoid such risk. Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- arch/x86/cpu/i386/call64.S | 4 ++++ arch/x86/cpu/i386/cpu.c | 11 ++++++++--- 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/x86/cpu/i386/call64.S b/arch/x86/cpu/i386/call64.S index 8f86728d42..275063c4af 100644 --- a/arch/x86/cpu/i386/call64.S +++ b/arch/x86/cpu/i386/call64.S @@ -79,6 +79,10 @@ lret_target: mov %eax, %eax /* Clear bits 63:32 */ jmp *%eax /* Jump to the 64-bit target */ +.globl call64_stub_size +call64_stub_size: + .long . - cpu_call64 + .data .align 16 .globl gdt64 diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c index af42431f45..e4b551452d 100644 --- a/arch/x86/cpu/i386/cpu.c +++ b/arch/x86/cpu/i386/cpu.c @@ -523,18 +523,23 @@ int cpu_jump_to_64bit_uboot(ulong target) typedef void (*func_t)(ulong pgtable, ulong setup_base, ulong target); uint32_t *pgtable; func_t func; + char *ptr; pgtable = (uint32_t *)PAGETABLE_BASE; build_pagetable(pgtable); - /* TODO(sjg@chromium.org): Find a better place for this */ - char *ptr = (char *)0x3000000; + extern long call64_stub_size; + ptr = malloc(call64_stub_size); + if (!ptr) { + printf("Failed to allocate the cpu_call64 stub\n"); + return -ENOMEM; + } char *gdt = (char *)0x3100000; extern char gdt64[]; - memcpy(ptr, cpu_call64, 0x1000); + memcpy(ptr, cpu_call64, call64_stub_size); memcpy(gdt, gdt64, 0x100); /* From bc1a8f0d7a57fbc1b0c03f323412a56761c82240 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 31 Jan 2019 08:22:14 -0800 Subject: [PATCH 6/7] x86: Use the existing GDT in the ROM for 64-bit U-Boot proper It is unnecessary to use a RAM version GDT for 64-bit U-Boot proper. In fact we can just use the ROM version directly, which not only eliminates the risk of being overwritten by application, but also removes the complexity of patching the cpu_call64(). Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- arch/x86/cpu/i386/cpu.c | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c index e4b551452d..3bde44ebf5 100644 --- a/arch/x86/cpu/i386/cpu.c +++ b/arch/x86/cpu/i386/cpu.c @@ -535,23 +535,9 @@ int cpu_jump_to_64bit_uboot(ulong target) printf("Failed to allocate the cpu_call64 stub\n"); return -ENOMEM; } - char *gdt = (char *)0x3100000; - - extern char gdt64[]; - memcpy(ptr, cpu_call64, call64_stub_size); - memcpy(gdt, gdt64, 0x100); - /* - * TODO(sjg@chromium.org): This manually inserts the pointers into - * the code. Tidy this up to avoid this. - */ func = (func_t)ptr; - ulong ofs = (ulong)cpu_call64 - (ulong)ptr; - *(ulong *)(ptr + 7) = (ulong)gdt; - *(ulong *)(ptr + 0xc) = (ulong)gdt + 2; - *(ulong *)(ptr + 0x13) = (ulong)gdt; - *(ulong *)(ptr + 0x117 - 0xd4) -= ofs; /* * Copy U-Boot from ROM From 24b56e2bf369ac003ccaac37d8bb80e08b743e16 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 5 Feb 2019 13:06:57 +0200 Subject: [PATCH 7/7] x86: tangier: Add initial ACPI support for PMIC device Basin Cove PMIC is connected to I2C0 bus which is hidden from the OS and access is going via SCU device, enumerated via PCI. For now, we add just a minimum support of PMIC device to allow enabling, e.g. USB OTG, in the OS. Signed-off-by: Andy Shevchenko Acked-by: Bin Meng --- .../asm/arch-tangier/acpi/southcluster.asl | 87 +++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl index e166e510cb..baad98b1c7 100644 --- a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl +++ b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl @@ -320,6 +320,93 @@ Device (PCI0) }) } } + + Device (IPC1) + { + Name (_ADR, 0x00130000) + + Method (_STA, 0, NotSerialized) + { + Return (STA_VISIBLE) + } + + Device (PMIC) + { + Name (_ADR, Zero) + Name (_HID, "INTC100E") + Name (_CID, "INTC100E") + Name (_DDN, "Basin Cove PMIC") + Name (_DEP, Package () + { + IPC1 + }) + + Method (_STA, 0, NotSerialized) + { + Return (STA_VISIBLE) + } + + Method (_CRS, 0, Serialized) + { + Name (RBUF, ResourceTemplate() + { + /* + * Shadow registers in SRAM for PMIC: + * SRAM PMIC register + * -------------------- + * 0x00- Unknown + * 0x03 THRMIRQ (0x04) + * 0x04 BCUIRQ (0x05) + * 0x05 ADCIRQ (0x06) + * 0x06 CHGRIRQ0 (0x07) + * 0x07 CHGRIRQ1 (0x08) + * 0x08- Unknown + * 0x0a PBSTATUS (0x27) + * 0x0b- Unknown + */ + Memory32Fixed(ReadWrite, 0xFFFFF610, 0x00000010) + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 30 } + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 23 } + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 52 } + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 51 } + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 50 } + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 27 } + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 49 } + }) + Return (RBUF) + } + + OperationRegion (PMOP, 0x8D, Zero, 0x0100) + Field (PMOP, DWordAcc, NoLock, Preserve) + { + SEL1, 32, + SEL2, 32, + VCCL, 32, + VNNL, 32, + AONL, 32, + CNTC, 32, + CNTN, 32, + AONN, 32, + CNT1, 32, + CNT2, 32, + CNT3, 32, + FLEX, 32, + PRG1, 32, + PRG2, 32, + PRG3, 32, + VLDO, 32, + } + + Name (AVBL, Zero) + Method (_REG, 2, NotSerialized) + { + If ((Arg0 == 0x8D)) + { + AVBL = Arg1 + } + } + } + } } Device (FLIS)