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https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
board: ti: K2G FC SoC 1GHz and DDR3 1066 MT/s support
Added support for K2G EVM with FlipChip SoC of which ARM/DDR3 runs at 1GHz/1066 MT/s. The patch is also backward compatible with old revision EVM and EVM with WireBond SoC. Their ARM/DDR3 run at 600MHz/800 MT/s. The new SoC supports 2 different speeds at 1GHz and 600MHz. Modyfied the CPU Name to show which SoC is used in the EVM. Modified the DDR3 configuration to reflect New SoC supports 2 different CPU and DDR3 speeds, 1GHz/1066MT and 600MHz/800MT. Added new inline function board_it_k2g_g1() for the new FlipChip 1GHz, and set the u-boot env variable board_name accordingly. Modified findfdt script in u-boot environment variable to include new k2g board type. Signed-off-by: Rex Chang <rchang@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
Rex Chang
Tom Rini
parent
19f3feaed1
commit
4849d95407
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@ -326,6 +326,9 @@ typedef volatile unsigned int *dv_reg_p;
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#define CPU_66AK2Lx 0xb9a7
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#define CPU_66AK2Gx 0xbb06
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/* Variant definitions */
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#define CPU_66AK2G1x 0x08
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/* DEVSPEED register */
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#define DEVSPEED_DEVSPEED_SHIFT 16
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#define DEVSPEED_DEVSPEED_MASK (0xfff << 16)
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@ -229,7 +229,19 @@ int print_cpuinfo(void)
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puts("66AK2Ex SR");
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break;
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case CPU_66AK2Gx:
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puts("66AK2Gx SR");
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puts("66AK2Gx");
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#ifdef CONFIG_SOC_K2G
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{
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int speed = get_max_arm_speed(speeds);
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if (speed == SPD1000)
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puts("-100 ");
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else if (speed == SPD600)
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puts("-60 ");
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else
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puts("-xx ");
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}
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#endif
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puts("SR");
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break;
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default:
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puts("Unknown\n");
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@ -241,7 +253,8 @@ int print_cpuinfo(void)
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puts("1.1\n");
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else if (rev == 0)
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puts("1.0\n");
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else if (rev == 8)
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puts("1.0\n");
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return 0;
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}
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#endif
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@ -20,6 +20,10 @@ static inline int board_is_k2g_gp(void)
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{
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return board_ti_is("66AK2GGP");
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}
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static inline int board_is_k2g_g1(void)
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{
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return board_ti_is("66AK2GG1");
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}
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static inline int board_is_k2g_ice(void)
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{
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return board_ti_is("66AK2GIC");
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@ -55,7 +55,7 @@ unsigned int get_external_clk(u32 clk)
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return clk_freq;
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}
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static int arm_speeds[DEVSPEED_NUMSPDS] = {
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int speeds[DEVSPEED_NUMSPDS] = {
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SPD400,
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SPD600,
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SPD800,
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@ -159,13 +159,20 @@ static struct pll_init_data nss_pll_config[MAX_SYSCLK] = {
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[SYSCLK_26MHz] = {NSS_PLL, 1000, 13, 2},
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};
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static struct pll_init_data ddr3_pll_config[MAX_SYSCLK] = {
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static struct pll_init_data ddr3_pll_config_800[MAX_SYSCLK] = {
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[SYSCLK_19MHz] = {DDR3A_PLL, 167, 1, 16},
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[SYSCLK_24MHz] = {DDR3A_PLL, 133, 1, 16},
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[SYSCLK_25MHz] = {DDR3A_PLL, 128, 1, 16},
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[SYSCLK_26MHz] = {DDR3A_PLL, 123, 1, 16},
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};
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static struct pll_init_data ddr3_pll_config_1066[MAX_SYSCLK] = {
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[SYSCLK_19MHz] = {DDR3A_PLL, 194, 1, 14},
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[SYSCLK_24MHz] = {DDR3A_PLL, 156, 1, 14},
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[SYSCLK_25MHz] = {DDR3A_PLL, 149, 1, 14},
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[SYSCLK_26MHz] = {DDR3A_PLL, 144, 1, 14},
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};
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struct pll_init_data *get_pll_init_data(int pll)
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{
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int speed;
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@ -178,7 +185,7 @@ struct pll_init_data *get_pll_init_data(int pll)
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data = &main_pll_config[sysclk_index][speed];
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break;
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case TETRIS_PLL:
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speed = get_max_arm_speed(arm_speeds);
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speed = get_max_arm_speed(speeds);
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data = &tetris_pll_config[sysclk_index][speed];
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break;
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case NSS_PLL:
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@ -188,7 +195,15 @@ struct pll_init_data *get_pll_init_data(int pll)
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data = &uart_pll_config[sysclk_index];
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break;
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case DDR3_PLL:
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data = &ddr3_pll_config[sysclk_index];
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if (cpu_revision() & CPU_66AK2G1x) {
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speed = get_max_arm_speed(speeds);
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if (speed == SPD1000)
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data = &ddr3_pll_config_1066[sysclk_index];
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else
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data = &ddr3_pll_config_800[sysclk_index];
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} else {
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data = &ddr3_pll_config_800[sysclk_index];
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}
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break;
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default:
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data = NULL;
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@ -209,7 +224,7 @@ int board_mmc_init(bd_t *bis)
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return -1;
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}
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if (board_is_k2g_gp())
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if (board_is_k2g_gp() || board_is_k2g_g1())
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omap_mmc_init(0, 0, 0, -1, -1);
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omap_mmc_init(1, 0, 0, -1, -1);
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@ -224,7 +239,8 @@ int board_fit_config_name_match(const char *name)
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if (!strcmp(name, "keystone-k2g-generic") && !eeprom_read)
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return 0;
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else if (!strcmp(name, "keystone-k2g-evm") && board_ti_is("66AK2GGP"))
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else if (!strcmp(name, "keystone-k2g-evm") &&
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(board_ti_is("66AK2GGP") || board_ti_is("66AK2GG1")))
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return 0;
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else if (!strcmp(name, "keystone-k2g-ice") && board_ti_is("66AK2GIC"))
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return 0;
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@ -283,7 +299,7 @@ int embedded_dtb_select(void)
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k2g_reset_mux_config();
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if (board_is_k2g_gp()) {
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if (board_is_k2g_gp() || board_is_k2g_g1()) {
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/* deassert FLASH_HOLD */
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clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
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BIT(9));
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@ -312,6 +328,8 @@ int board_late_init(void)
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#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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if (board_is_k2g_gp())
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env_set("board_name", "66AK2GGP\0");
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else if (board_is_k2g_g1())
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env_set("board_name", "66AK2GG1\0");
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else if (board_is_k2g_ice())
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env_set("board_name", "66AK2GIC\0");
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#endif
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@ -10,6 +10,7 @@
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#include <common.h>
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#include "ddr3_cfg.h"
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#include <asm/arch/ddr3.h>
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#include <asm/arch/hardware.h>
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#include "board.h"
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/* K2G GP EVM DDR3 Configuration */
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@ -53,6 +54,46 @@ struct ddr3_phy_config ddr3phy_800_2g = {
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.pir_v2 = 0x00000F81ul,
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};
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static struct ddr3_phy_config ddr3phy_1066_2g = {
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.pllcr = 0x000DC000ul,
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.pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
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.pgcr1_val = ((1 << 2) | (2 << 7) | (1 << 23)),
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.ptr0 = 0x42C21590ul,
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.ptr1 = 0xD05612C0ul,
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.ptr2 = 0,
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.ptr3 = 0x0904111Dul,
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.ptr4 = 0x0859A072ul,
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.dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
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.dcr_val = ((1 << 10)),
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.dtpr0 = 0x6D147744ul,
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.dtpr1 = 0x32845A80ul,
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.dtpr2 = 0x50023600ul,
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.mr0 = 0x00001830ul,
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.mr1 = 0x00000006ul,
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.mr2 = 0x00000000ul,
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.dtcr = 0x710035C7ul,
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.pgcr2 = 0x00F05159ul,
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.zq0cr1 = 0x0001005Dul,
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.zq1cr1 = 0x0001005Bul,
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.zq2cr1 = 0x0001005Bul,
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.pir_v1 = 0x00000033ul,
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.datx8_2_mask = 0,
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.datx8_2_val = 0,
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.datx8_3_mask = 0,
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.datx8_3_val = 0,
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.datx8_4_mask = 0,
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.datx8_4_val = ((1 << 0)),
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.datx8_5_mask = DXEN_MASK,
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.datx8_5_val = 0,
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.datx8_6_mask = DXEN_MASK,
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.datx8_6_val = 0,
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.datx8_7_mask = DXEN_MASK,
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.datx8_7_val = 0,
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.datx8_8_mask = DXEN_MASK,
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.datx8_8_val = 0,
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.pir_v2 = 0x00000F81ul,
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};
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struct ddr3_emif_config ddr3_800_2g = {
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.sdcfg = 0x62005662ul,
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.sdtim1 = 0x0A385033ul,
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@ -63,6 +104,16 @@ struct ddr3_emif_config ddr3_800_2g = {
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.sdrfc = 0x00000C34ul,
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};
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struct ddr3_emif_config ddr3_1066_2g = {
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.sdcfg = 0x62005662ul,
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.sdtim1 = 0x0E4C6843ul,
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.sdtim2 = 0x00001CC6ul,
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.sdtim3 = 0x323DFF32ul,
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.sdtim4 = 0x533F08AFul,
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.zqcfg = 0x70073200ul,
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.sdrfc = 0x00001044ul,
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};
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/* K2G ICE evm DDR3 Configuration */
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struct ddr3_phy_config ddr3phy_800_512mb = {
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.pllcr = 0x000DC000ul,
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@ -118,8 +169,10 @@ u32 ddr3_init(void)
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{
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/* Reset DDR3 PHY after PLL enabled */
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ddr3_reset_ddrphy();
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if (board_is_k2g_gp()) {
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if (board_is_k2g_g1()) {
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ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1066_2g);
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ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1066_2g);
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} else if (board_is_k2g_gp()) {
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ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_2g);
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ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_2g);
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} else if (board_is_k2g_ice()) {
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@ -345,7 +345,7 @@ void k2g_mux_config(void)
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{
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if (!board_ti_was_eeprom_read()) {
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configure_pin_mux(k2g_generic_pin_cfg);
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} else if (board_is_k2g_gp()) {
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} else if (board_is_k2g_gp() || board_is_k2g_g1()) {
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configure_pin_mux(k2g_evm_pin_cfg);
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} else if (board_is_k2g_ice()) {
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configure_pin_mux(k2g_ice_evm_pin_cfg);
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@ -34,11 +34,13 @@
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"findfdt="\
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"if test $board_name = 66AK2GGP; then " \
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"setenv name_fdt keystone-k2g-evm.dtb; " \
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"else if test $board_name = 66AK2GG1; then " \
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"setenv name_fdt keystone-k2g-evm.dtb; " \
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"else if test $board_name = 66AK2GIC; then " \
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"setenv name_fdt keystone-k2g-ice.dtb; " \
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"else if test $name_fdt = undefined; then " \
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"echo WARNING: Could not determine device tree to use;"\
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"fi;fi;fi; setenv fdtfile ${name_fdt}\0" \
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"fi;fi;fi;fi; setenv fdtfile ${name_fdt}\0" \
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"name_mon=skern-k2g.bin\0" \
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"name_ubi=k2g-evm-ubifs.ubi\0" \
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"name_uboot=u-boot-spi-k2g-evm.gph\0" \
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