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https://github.com/brain-hackers/u-boot-brain
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mips: octeon: cpu.c: Add arch_misc_init() for pci-console & pci-bootcmd
This patch adds the necessary platform infrastructure code, so that the MIPS Octeon drivers "serial_octeon_pcie_console" & "serial_bootcmd" can be used. This is e.g. the bootmem initialization in a compatible way to the Marvell 2013 U-Boot, so that the exisiting PC remote tools like "oct-remote-console" & "oct-remote-load" can be used. This is be done in the newly introduced arch_misc_init(), which calls the necessary init functions when enabled. These patches are in preparation for the MIPS Octeon NIC23 board support, which is a desktop PCIe target board enabling these features. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This commit is contained in:
Stefan Roese
parent
737c3de099
commit
47dedfb5b9
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@ -3,6 +3,10 @@
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* Copyright (C) 2020 Marvell International Ltd.
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*/
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#include <dm.h>
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#include <dm/uclass.h>
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#include <env.h>
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#include <iomux.h>
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#include <asm/global_data.h>
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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@ -10,9 +14,24 @@
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#include <linux/io.h>
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#include <mach/clock.h>
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#include <mach/cavm-reg.h>
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#include <mach/cvmx-bootmem.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Important:
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* This address cannot be changed as the PCI console tool relies on exactly
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* this value!
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*/
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#define BOOTLOADER_BOOTMEM_DESC_ADDR 0x6c100
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#define BOOTLOADER_BOOTMEM_DESC_SPACE (BOOTLOADER_BOOTMEM_DESC_ADDR + 0x8)
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#define OCTEON_RESERVED_LOW_BOOT_MEM_SIZE (1024 * 1024)
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#define BOOTCMD_NAME "pci-bootcmd"
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#define CONSOLE_NAME "pci-console@0"
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#define OCTEON_BOOTLOADER_LOAD_MEM_NAME "__tmp_load"
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/*
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* TRUE for devices having registers with little-endian byte
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* order, FALSE for registers with native-endian byte order.
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@ -85,3 +104,311 @@ int print_cpuinfo(void)
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return 0;
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}
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static int octeon_bootmem_init(void)
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{
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int ret;
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/* Call old single-node func: it uses only gd->ram_size */
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ret = cvmx_bootmem_phy_mem_list_init(gd->ram_size,
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OCTEON_RESERVED_LOW_BOOT_MEM_SIZE,
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(void *)CKSEG0ADDR(BOOTLOADER_BOOTMEM_DESC_SPACE));
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if (!ret) {
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printf("FATAL: Error initializing bootmem list\n");
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return -ENOSPC;
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}
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/*
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* Put bootmem descriptor address in known location for host.
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* Make sure it is not in kseg0, as we want physical address
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*/
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writeq((u64)__cvmx_bootmem_internal_get_desc_ptr() & 0x7fffffffull,
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(void *)CKSEG0ADDR(BOOTLOADER_BOOTMEM_DESC_ADDR));
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debug("Reserving first 1MB of memory\n");
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ret = cvmx_bootmem_reserve_memory(0, OCTEON_RESERVED_LOW_BOOT_MEM_SIZE,
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"__low_reserved", 0);
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if (!ret)
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puts("Error reserving low 1MB of memory\n");
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#ifdef DEBUG
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cvmx_bootmem_phy_list_print();
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#endif
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return 0;
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}
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static int octeon_configure_load_memory(void)
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{
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char *eptr;
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u32 addr;
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u32 size;
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int ret;
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eptr = env_get("octeon_reserved_mem_load_size");
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if (!eptr || !strcmp("auto", eptr)) {
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/*
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* Pick a size that we think is appropriate.
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* Please note that for small memory boards this guess
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* will likely not be ideal.
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* Please pick a specific size for boards/applications
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* that require it.
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*/
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if (gd->ram_size <= (256 << 20)) {
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size = min_t(u64, (128 << 20),
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((gd->ram_size * 2) / 5) & ~0xFFFFF);
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} else {
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size = min_t(u64, (256 << 20),
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((gd->ram_size - (256 << 20)) / 3) & ~0xFFFFF);
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}
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} else {
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size = simple_strtol(eptr, NULL, 16);
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debug("octeon_reserved_mem_load_size=0x%08x\n", size);
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}
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if (size) {
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debug("Linux reserved load size 0x%08x\n", size);
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eptr = env_get("octeon_reserved_mem_load_base");
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if (!eptr || !strcmp("auto", eptr)) {
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u64 mem_top;
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/*
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* Leave some room for previous allocations that
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* are made starting at the top of the low
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* 256 Mbytes of DRAM
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*/
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int adjust = (1 << 20);
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if (gd->ram_size <= (512 << 20))
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adjust = (17 << 20);
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/* Put block at the top of DDR0, or bottom of DDR2 */
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if ((gd->ram_size <= (256 << 20)) ||
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(size > (gd->ram_size - (256 << 20)))) {
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mem_top = min_t(u64, gd->ram_size - adjust,
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(256 << 20) - adjust);
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} else if ((gd->ram_size <= (512 << 20)) ||
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(size > (gd->ram_size - (512 << 20)))) {
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mem_top = min_t(u64, gd->ram_size - adjust,
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(512 << 20) - adjust);
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} else {
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/*
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* We have enough room, so set
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* mem_top so that the block is
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* at the base of the DDR2
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* segment
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*/
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mem_top = (512 << 20) + size;
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}
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/*
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* Adjust for boot bus memory hole on OCTEON II
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* and later.
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*/
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if ((gd->ram_size > (256 << 20)))
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mem_top += (256 << 20);
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debug("Adjusted memory top is 0x%llx\n", mem_top);
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addr = mem_top - size;
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if (addr > (512 << 20))
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addr = (512 << 20);
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if ((addr >= (256 << 20)) && addr < (512 << 20)) {
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/*
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* The address landed in the boot-bus
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* memory hole. Dig it out of the hole.
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*/
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addr = (512 << 20);
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}
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} else {
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addr = simple_strtol(eptr, NULL, 16);
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}
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ret = cvmx_bootmem_phy_named_block_alloc(size, addr,
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addr + size, 0,
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OCTEON_BOOTLOADER_LOAD_MEM_NAME,
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0);
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if (ret < 0) {
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printf("ERROR: Unable to allocate bootloader reserved memory (addr: 0x%x, size: 0x%x).\n",
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addr, size);
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} else {
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/*
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* Set default load address to base of memory
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* reserved for loading. The setting of the
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* env. variable also sets the load_addr global
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* variable.
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* This environment variable is overridden each
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* boot if a reserved block is created.
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*/
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char str[20];
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snprintf(str, sizeof(str), "0x%x", addr);
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env_set("loadaddr", str);
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debug("Setting load address to 0x%08x, size 0x%x\n",
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addr, size);
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}
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return 0;
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}
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printf("WARNING: No reserved memory for image loading.\n");
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return -1;
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}
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static int init_pcie_console(void)
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{
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char *stdinname = env_get("stdin");
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char *stdoutname = env_get("stdout");
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char *stderrname = env_get("stderr");
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struct udevice *pcie_console_dev = NULL;
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bool stdin_set, stdout_set, stderr_set;
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char iomux_name[128];
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int ret = 0;
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debug("%s: stdin: %s, stdout: %s, stderr: %s\n", __func__, stdinname,
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stdoutname, stderrname);
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if (!stdinname) {
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env_set("stdin", "serial");
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stdinname = env_get("stdin");
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}
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if (!stdoutname) {
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env_set("stdout", "serial");
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stdoutname = env_get("stdout");
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}
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if (!stderrname) {
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env_set("stderr", "serial");
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stderrname = env_get("stderr");
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}
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if (!stdinname || !stdoutname || !stderrname) {
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printf("%s: Error setting environment variables for serial\n",
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__func__);
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return -1;
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}
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stdin_set = !!strstr(stdinname, CONSOLE_NAME);
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stdout_set = !!strstr(stdoutname, CONSOLE_NAME);
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stderr_set = !!strstr(stderrname, CONSOLE_NAME);
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log_debug("stdin: %d, \"%s\", stdout: %d, \"%s\", stderr: %d, \"%s\"\n",
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stdin_set, stdinname, stdout_set, stdoutname,
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stderr_set, stderrname);
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ret = uclass_get_device_by_name(UCLASS_SERIAL, CONSOLE_NAME,
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&pcie_console_dev);
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if (ret || !pcie_console_dev) {
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debug("%s: No PCI console device %s found\n", __func__,
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CONSOLE_NAME);
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return 0;
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}
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if (stdin_set)
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strncpy(iomux_name, stdinname, sizeof(iomux_name));
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else
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snprintf(iomux_name, sizeof(iomux_name), "%s,%s",
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stdinname, pcie_console_dev->name);
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ret = iomux_doenv(stdin, iomux_name);
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if (ret) {
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log_err("%s: Error setting I/O stdin MUX to %s\n",
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__func__, iomux_name);
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return ret;
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}
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if (!stdin_set)
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env_set("stdin", iomux_name);
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if (stdout_set)
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strncpy(iomux_name, stdoutname, sizeof(iomux_name));
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else
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snprintf(iomux_name, sizeof(iomux_name), "%s,%s", stdoutname,
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pcie_console_dev->name);
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ret = iomux_doenv(stdout, iomux_name);
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if (ret) {
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log_err("%s: Error setting I/O stdout MUX to %s\n",
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__func__, iomux_name);
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return ret;
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}
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if (!stdout_set)
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env_set("stdout", iomux_name);
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if (stderr_set)
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strncpy(iomux_name, stderrname, sizeof(iomux_name));
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else
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snprintf(iomux_name, sizeof(iomux_name), "%s,%s", stderrname,
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pcie_console_dev->name);
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ret = iomux_doenv(stderr, iomux_name);
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if (ret) {
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log_err("%s: Error setting I/O stderr MUX to %s\n",
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__func__, iomux_name);
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return ret;
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}
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if (!stderr_set)
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env_set("stderr", iomux_name);
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debug("%s: stdin: %s, stdout: %s, stderr: %s, ret: %d\n",
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__func__, env_get("stdin"), env_get("stdout"),
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env_get("stderr"), ret);
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return ret;
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}
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static int init_bootcmd_console(void)
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{
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char *stdinname = env_get("stdin");
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struct udevice *bootcmd_dev = NULL;
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bool stdin_set;
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char iomux_name[128];
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int ret = 0;
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debug("%s: stdin before: %s\n", __func__,
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stdinname ? stdinname : "NONE");
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if (!stdinname) {
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env_set("stdin", "serial");
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stdinname = env_get("stdin");
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}
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stdin_set = !!strstr(stdinname, BOOTCMD_NAME);
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ret = uclass_get_device_by_driver(UCLASS_SERIAL,
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DM_DRIVER_GET(octeon_bootcmd),
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&bootcmd_dev);
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if (ret) {
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log_err("%s: Error getting %s serial class\n", __func__,
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BOOTCMD_NAME);
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} else if (bootcmd_dev) {
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if (stdin_set)
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strncpy(iomux_name, stdinname, sizeof(iomux_name));
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else
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snprintf(iomux_name, sizeof(iomux_name), "%s,%s",
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stdinname, bootcmd_dev->name);
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ret = iomux_doenv(stdin, iomux_name);
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if (ret)
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log_err("%s: Error %d enabling the PCI bootcmd input console \"%s\"\n",
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__func__, ret, iomux_name);
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if (!stdin_set)
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env_set("stdin", iomux_name);
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}
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debug("%s: Set iomux and stdin to %s (ret: %d)\n",
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__func__, iomux_name, ret);
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return ret;
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}
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int arch_misc_init(void)
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{
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int ret;
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ret = octeon_bootmem_init();
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if (ret)
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return ret;
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ret = octeon_configure_load_memory();
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if (ret)
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return ret;
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if (CONFIG_IS_ENABLED(OCTEON_SERIAL_PCIE_CONSOLE))
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init_pcie_console();
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if (CONFIG_IS_ENABLED(OCTEON_SERIAL_BOOTCMD))
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init_bootcmd_console();
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return 0;
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}
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