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net: mscc: serval: Add ethernet nodes for Serval 

Add ethernet nodes for Serval SoCs family. There are 2 pcb in this
family: pcb105 and pcb106.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
This commit is contained in:
Horatiu Vultur 2019-04-11 14:11:34 +02:00 committed by Daniel Schwierzeck
parent d2691b4af2
commit 4788704dd8
4 changed files with 165 additions and 0 deletions
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58
arch/mips/dts/mscc,serval.dtsi
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@ -145,5 +145,63 @@
#gpio-cells = <2>;
gpio-ranges = <&sgpio 0 0 64>;
};
switch: switch@011e0000 {
compatible = "mscc,vsc7418-switch";
reg = <0x011e0000 0x0100>, // VTSS_TO_DEV0
<0x011f0000 0x0100>, // VTSS_TO_DEV1
<0x01200000 0x0100>, // VTSS_TO_DEV2
<0x01210000 0x0100>, // VTSS_TO_DEV3
<0x01220000 0x0100>, // VTSS_TO_DEV4
<0x01230000 0x0100>, // VTSS_TO_DEV5
<0x01240000 0x0100>, // VTSS_TO_DEV6
<0x01250000 0x0100>, // VTSS_TO_DEV7
<0x01260000 0x0100>, // VTSS_TO_DEV8
<0x01270000 0x0100>, // VTSS_TO_DEV9
<0x01280000 0x0100>, // VTSS_TO_DEV10
<0x01900000 0x100000>, // ANA
<0x01080000 0x20000>, // QS
<0x01800000 0x100000>, // QSYS
<0x01030000 0x10000>, // REW
<0x01010000 0x20000>, // SYS
<0x010a0000 0x10000>; // HSIO
reg-names = "port0", "port1", "port2", "port3",
"port4", "port5", "port6", "port7",
"port8", "port9", "port10",
"ana", "qs", "qsys", "rew", "sys",
"hsio";
status = "okay";
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
};
};
mdio0: mdio@0107005c {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mscc,serval-miim";
reg = <0x0107005c 0x24>;
status = "disabled";
};
mdio1: mdio@01070080 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mscc,serval-miim";
reg = <0x01070080 0x24>;
status = "disabled";
};
hsio: syscon@10d0000 {
compatible = "mscc,serval-hsio", "syscon", "simple-mfd";
reg = <0x10a0000 0x10000>;
serdes_hsio: serdes_hsio {
compatible = "mscc,vsc7418-serdes";
#phy-cells = <3>;
};
};
};
};

44
arch/mips/dts/serval_pcb105.dts
View File

@ -5,6 +5,7 @@
/dts-v1/;
#include "mscc,serval.dtsi"
#include <dt-bindings/mscc/serval_data.h>
/ {
model = "Serval PCB105 Reference Board";
@ -54,3 +55,46 @@
status = "okay";
sgpio-ports = <0x00FFFFFF>;
};
&mdio1 {
status = "okay";
phy16: ethernet-phy@16 {
reg = <16>;
};
phy17: ethernet-phy@17 {
reg = <17>;
};
phy18: ethernet-phy@18 {
reg = <18>;
};
phy19: ethernet-phy@19 {
reg = <19>;
};
};
&switch {
ethernet-ports {
port0: port@0 {
reg = <7>;
phy-handle = <&phy16>;
phys = <&serdes_hsio 7 SERDES1G(7) PHY_MODE_SGMII>;
};
port1: port@1 {
reg = <6>;
phy-handle = <&phy17>;
phys = <&serdes_hsio 6 SERDES1G(6) PHY_MODE_SGMII>;
};
port2: port@2 {
reg = <5>;
phy-handle = <&phy18>;
phys = <&serdes_hsio 5 SERDES1G(5) PHY_MODE_SGMII>;
};
port3: port@3 {
reg = <4>;
phy-handle = <&phy19>;
phys = <&serdes_hsio 4 SERDES1G(4) PHY_MODE_SGMII>;
};
};
};

44
arch/mips/dts/serval_pcb106.dts
View File

@ -5,6 +5,7 @@
/dts-v1/;
#include "mscc,serval.dtsi"
#include <dt-bindings/mscc/serval_data.h>
/ {
model = "Serval PCB106 Reference Board";
@ -54,3 +55,46 @@
status = "okay";
sgpio-ports = <0x00FFFFFF>;
};
&mdio1 {
status = "okay";
phy16: ethernet-phy@16 {
reg = <16>;
};
phy17: ethernet-phy@17 {
reg = <17>;
};
phy18: ethernet-phy@18 {
reg = <18>;
};
phy19: ethernet-phy@19 {
reg = <19>;
};
};
&switch {
ethernet-ports {
port0: port@0 {
reg = <7>;
phy-handle = <&phy16>;
phys = <&serdes_hsio 7 SERDES1G(7) PHY_MODE_SGMII>;
};
port1: port@1 {
reg = <6>;
phy-handle = <&phy17>;
phys = <&serdes_hsio 6 SERDES1G(6) PHY_MODE_SGMII>;
};
port2: port@2 {
reg = <5>;
phy-handle = <&phy18>;
phys = <&serdes_hsio 5 SERDES1G(5) PHY_MODE_SGMII>;
};
port3: port@3 {
reg = <4>;
phy-handle = <&phy19>;
phys = <&serdes_hsio 4 SERDES1G(4) PHY_MODE_SGMII>;
};
};
};

19
include/dt-bindings/mscc/serval_data.h Normal file
View File

@ -0,0 +1,19 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (c) 2018 Microsemi Corporation
*/
#ifndef _SERVAL_DATA_H_
#define _SERVAL_DATA_H_
#define SERDES1G(x) (x)
#define SERDES1G_MAX SERDES1G(9)
#define SERDES6G(x) (SERDES1G_MAX + 1 + (x))
#define SERDES6G_MAX SERDES6G(11)
#define SERDES_MAX (SERDES6G_MAX + 1)
/* similar with phy_interface_t */
#define PHY_MODE_SGMII 2
#define PHY_MODE_QSGMII 4
#endif