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mips: ath79: Add support for ungating ethernet on ar933x and ar934x
Add code to ungate the ethernet controller on ar933x and ar934x . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wills Wang <wills.wang@live.com>
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@ -622,6 +622,7 @@
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#define AR933X_RESET_GE1_MAC BIT(13)
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#define AR933X_RESET_GE1_MAC BIT(13)
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#define AR933X_RESET_WMAC BIT(11)
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#define AR933X_RESET_WMAC BIT(11)
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#define AR933X_RESET_GE0_MAC BIT(9)
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#define AR933X_RESET_GE0_MAC BIT(9)
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#define AR933X_RESET_ETH_SWITCH BIT(8)
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#define AR933X_RESET_USB_HOST BIT(5)
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#define AR933X_RESET_USB_HOST BIT(5)
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#define AR933X_RESET_USB_PHY BIT(4)
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#define AR933X_RESET_USB_PHY BIT(4)
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#define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
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#define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
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@ -140,6 +140,7 @@ static inline int soc_is_qca956x(void)
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return soc_is_tp9343() || soc_is_qca9561();
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return soc_is_tp9343() || soc_is_qca9561();
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}
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}
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int ath79_eth_reset(void);
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int ath79_usb_reset(void);
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int ath79_usb_reset(void);
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#endif /* __ASM_MACH_ATH79_H */
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#endif /* __ASM_MACH_ATH79_H */
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@ -71,6 +71,84 @@ u32 get_bootstrap(void)
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return 0;
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return 0;
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}
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}
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static int eth_init_ar933x(void)
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{
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void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
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MAP_NOCACHE);
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void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
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MAP_NOCACHE);
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void __iomem *gregs = map_physmem(AR933X_GMAC_BASE, AR933X_GMAC_SIZE,
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MAP_NOCACHE);
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const u32 mask = AR933X_RESET_GE0_MAC | AR933X_RESET_GE0_MDIO |
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AR933X_RESET_GE1_MAC | AR933X_RESET_GE1_MDIO |
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AR933X_RESET_ETH_SWITCH;
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/* Clear MDIO slave EN bit. */
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clrbits_be32(rregs + AR933X_RESET_REG_BOOTSTRAP, BIT(17));
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mdelay(10);
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/* Get Atheros S26 PHY out of reset. */
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clrsetbits_be32(pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG,
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0x1f, 0x10);
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mdelay(10);
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setbits_be32(rregs + AR933X_RESET_REG_RESET_MODULE, mask);
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mdelay(10);
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clrbits_be32(rregs + AR933X_RESET_REG_RESET_MODULE, mask);
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mdelay(10);
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/* Configure AR93xx GMAC register. */
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clrsetbits_be32(gregs + AR933X_GMAC_REG_ETH_CFG,
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AR933X_ETH_CFG_MII_GE0_MASTER |
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AR933X_ETH_CFG_MII_GE0_SLAVE,
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AR933X_ETH_CFG_MII_GE0_SLAVE);
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return 0;
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}
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static int eth_init_ar934x(void)
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{
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void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
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MAP_NOCACHE);
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void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
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MAP_NOCACHE);
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void __iomem *gregs = map_physmem(AR934X_GMAC_BASE, AR934X_GMAC_SIZE,
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MAP_NOCACHE);
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const u32 mask = AR934X_RESET_GE0_MAC | AR934X_RESET_GE0_MDIO |
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AR934X_RESET_GE1_MAC | AR934X_RESET_GE1_MDIO |
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AR934X_RESET_ETH_SWITCH_ANALOG;
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u32 reg;
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reg = readl(rregs + AR934X_RESET_REG_BOOTSTRAP);
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if (reg & AR934X_BOOTSTRAP_REF_CLK_40)
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writel(0x570, pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
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else
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writel(0x271, pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
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writel(BIT(26) | BIT(25), pregs + AR934X_PLL_ETH_XMII_CONTROL_REG);
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setbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
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mdelay(1);
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clrbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
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mdelay(1);
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/* Configure AR934x GMAC register. */
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writel(AR934X_ETH_CFG_RGMII_GMAC0, gregs + AR934X_GMAC_REG_ETH_CFG);
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return 0;
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}
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int ath79_eth_reset(void)
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{
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/*
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* Un-reset ethernet. DM still doesn't have any notion of reset
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* framework, so we do it by hand here.
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*/
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if (soc_is_ar933x())
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return eth_init_ar933x();
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if (soc_is_ar934x())
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return eth_init_ar934x();
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return -EINVAL;
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}
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static int usb_reset_ar933x(void __iomem *reset_regs)
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static int usb_reset_ar933x(void __iomem *reset_regs)
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{
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{
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/* Ungate the USB block */
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/* Ungate the USB block */
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