From 19c6b8cf8bea6d3634594bcb6a26768ecf4e9b96 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Date: Sat, 13 Feb 2021 16:59:01 +0100 Subject: [PATCH 01/17] odroid-go2: remove setting SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Using a non-default SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR setting makes the resulting u-boot-rockchip.bin unbootable, as it gets stuck after SPL. Removing the setting from the defconfig allows U-Boot to load successfully. Signed-off-by: Roger Pau Monné Reviewed-by: Kever Yang --- configs/odroid-go2_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig index 853890901a..5632b15611 100644 --- a/configs/odroid-go2_defconfig +++ b/configs/odroid-go2_defconfig @@ -33,7 +33,6 @@ CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y # CONFIG_TPL_BANNER_PRINT is not set -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200 CONFIG_SPL_CRC32_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_POWER_SUPPORT=y From a062144518afd72d2e96bf44bad72037ac39a57e Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 9 Feb 2021 14:47:03 +0100 Subject: [PATCH 02/17] rockchip: rk3368: adjust CONFIG_SYS_LOAD_ADDR CONFIG_SYS_LOAD_ADDR currently is at 0x00280000 which is only 512KB behind the area where we load u-boot to, which depending on u-boot size may overlap at some point. So for safety just pick the same value rk3399 has and set CONFIG_SYS_LOAD_ADDR to 0x00800800 on rk3368 as well. Signed-off-by: Heiko Stuebner Reviewed-by: Kever Yang --- include/configs/rk3368_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index f178a06945..86498b4c82 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -24,7 +24,7 @@ #define CONFIG_IRAM_BASE 0xff8c0000 #define CONFIG_SYS_INIT_SP_ADDR 0x00300000 -#define CONFIG_SYS_LOAD_ADDR 0x00280000 +#define CONFIG_SYS_LOAD_ADDR 0x00800800 #define CONFIG_SPL_MAX_SIZE 0x40000 #define CONFIG_SPL_BSS_START_ADDR 0x400000 From e436c499dc99d4b768eb6a9a99ce06dc7a81cb3a Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 9 Feb 2021 14:47:04 +0100 Subject: [PATCH 03/17] rockchip: rk3368: set CONFIG_SYS_BOOTM_LEN to 64MB Mimicing for example the rk3399, set the SYS_BOOTM_LEN to 64MB so that regular kernel images can get loaded without problems. Signed-off-by: Heiko Stuebner Reviewed-by: Kever Yang --- include/configs/rk3368_common.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index 86498b4c82..fbbb8cf267 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -31,6 +31,8 @@ #define CONFIG_SPL_BSS_MAX_SIZE 0x20000 #define CONFIG_SPL_STACK 0x00188000 +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ + #ifndef CONFIG_SPL_BUILD #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00500000\0" \ From 53e14aa734b12154a5dd88621a5bfce2c5bdc901 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 9 Feb 2021 14:47:05 +0100 Subject: [PATCH 04/17] rockchip: rk3368: increase SYS_MALLOC_F_LEN to 0x4000 To prevent running out of memory, increase SYS_MALLOC_F_LEN to 0x4000 similar to what rk3399 uses. Signed-off-by: Heiko Stuebner Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/rk3368/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig index d6ca5f1d24..c31915e7dc 100644 --- a/arch/arm/mach-rockchip/rk3368/Kconfig +++ b/arch/arm/mach-rockchip/rk3368/Kconfig @@ -49,7 +49,7 @@ config SYS_SOC default "rk3368" config SYS_MALLOC_F_LEN - default 0x2000 + default 0x4000 config SPL_LIBCOMMON_SUPPORT default y From ca7bb9dde7a22003fc08fb135803ae33c94a2ac7 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 9 Feb 2021 14:47:06 +0100 Subject: [PATCH 05/17] rockchip: rk3368: move STACK_R_ADDR address and into Kconfig With the STACK_R_ADDR at 0x600000 (6MB) we're competing with with the loading address of either u-boot or atf parts, so move that away to 0x4000000 (64MB) similar to rk3399. Only lion currently sets that at all but not sheep the second rk3368 board, so just move that to the Kconfig for rk3368 similar to rk3399 as well. Signed-off-by: Heiko Stuebner Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/rk3368/Kconfig | 3 +++ configs/lion-rk3368_defconfig | 1 - 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig index c31915e7dc..78eb96df3d 100644 --- a/arch/arm/mach-rockchip/rk3368/Kconfig +++ b/arch/arm/mach-rockchip/rk3368/Kconfig @@ -65,6 +65,9 @@ source "board/rockchip/evb_px5/Kconfig" config SPL_LDSCRIPT default "arch/arm/cpu/armv8/u-boot-spl.lds" +config SPL_STACK_R_ADDR + default 0x04000000 + config TPL_MAX_SIZE default 28672 diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig index 583dd44da3..b409715060 100644 --- a/configs/lion-rk3368_defconfig +++ b/configs/lion-rk3368_defconfig @@ -9,7 +9,6 @@ CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0 CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xFF180000 CONFIG_DEBUG_UART_CLOCK=24000000 From 1ebf106f400934a3aa7895552d639a7441b326c3 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 9 Feb 2021 14:47:07 +0100 Subject: [PATCH 06/17] rockchip: rk3368: sync clock dt-binding header from Linux This is the state as of v5.10 in Linux. Signed-off-by: Heiko Stuebner Reviewed-by: Kever Yang --- include/dt-bindings/clock/rk3368-cru.h | 31 ++++++++++++-------------- 1 file changed, 14 insertions(+), 17 deletions(-) diff --git a/include/dt-bindings/clock/rk3368-cru.h b/include/dt-bindings/clock/rk3368-cru.h index 9c5dd9ba2f..0a06c5f514 100644 --- a/include/dt-bindings/clock/rk3368-cru.h +++ b/include/dt-bindings/clock/rk3368-cru.h @@ -1,15 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (c) 2015 Heiko Stuebner - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H @@ -44,13 +35,12 @@ #define SCLK_I2S_8CH 82 #define SCLK_SPDIF_8CH 83 #define SCLK_I2S_2CH 84 -#define SCLK_TIMER0 85 -#define SCLK_TIMER1 86 -#define SCLK_TIMER2 87 -#define SCLK_TIMER3 88 -#define SCLK_TIMER4 89 -#define SCLK_TIMER5 90 -#define SCLK_TIMER6 91 +#define SCLK_TIMER00 85 +#define SCLK_TIMER01 86 +#define SCLK_TIMER02 87 +#define SCLK_TIMER03 88 +#define SCLK_TIMER04 89 +#define SCLK_TIMER05 90 #define SCLK_OTGPHY0 93 #define SCLK_OTG_ADP 96 #define SCLK_HSICPHY480M 97 @@ -82,6 +72,12 @@ #define SCLK_SFC 126 #define SCLK_MAC 127 #define SCLK_MACREF_OUT 128 +#define SCLK_TIMER10 133 +#define SCLK_TIMER11 134 +#define SCLK_TIMER12 135 +#define SCLK_TIMER13 136 +#define SCLK_TIMER14 137 +#define SCLK_TIMER15 138 #define DCLK_VOP 190 #define MCLK_CRYPTO 191 @@ -151,6 +147,7 @@ #define PCLK_ISP 366 #define PCLK_VIP 367 #define PCLK_WDT 368 +#define PCLK_EFUSE256 369 /* hclk gates */ #define HCLK_SFC 448 From 5aefa4af2915fe660c97fcd157544dcf108fe101 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 9 Feb 2021 14:47:08 +0100 Subject: [PATCH 07/17] rockchip: rk3368: sync main rk3368 dtsi from Linux This is the state as of v5.10 + the recently added timer0 phandle targetted at the 5.12 merge window. With this the non-mainline nodes like the dmc move to a separate rk3368-u-boot.dtsi that is included from the board-specific -u-boot.dtsi files, similar to how rk3399 does this. Signed-off-by: Heiko Stuebner Reviewed-by: Kever Yang --- arch/arm/dts/rk3368-geekbox-u-boot.dtsi | 2 + arch/arm/dts/rk3368-lion-u-boot.dtsi | 2 + arch/arm/dts/rk3368-px5-evb-u-boot.dtsi | 3 + arch/arm/dts/rk3368-sheep-u-boot.dtsi | 2 + arch/arm/dts/rk3368-u-boot.dtsi | 27 ++ arch/arm/dts/rk3368.dtsi | 578 ++++++++++++++---------- 6 files changed, 383 insertions(+), 231 deletions(-) create mode 100644 arch/arm/dts/rk3368-u-boot.dtsi diff --git a/arch/arm/dts/rk3368-geekbox-u-boot.dtsi b/arch/arm/dts/rk3368-geekbox-u-boot.dtsi index 30ea9e433a..0b724fa45f 100644 --- a/arch/arm/dts/rk3368-geekbox-u-boot.dtsi +++ b/arch/arm/dts/rk3368-geekbox-u-boot.dtsi @@ -3,6 +3,8 @@ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH */ +#include "rk3368-u-boot.dtsi" + &pinctrl { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/rk3368-lion-u-boot.dtsi b/arch/arm/dts/rk3368-lion-u-boot.dtsi index 6d54214de9..9bd6352755 100644 --- a/arch/arm/dts/rk3368-lion-u-boot.dtsi +++ b/arch/arm/dts/rk3368-lion-u-boot.dtsi @@ -3,6 +3,8 @@ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH */ +#include "rk3368-u-boot.dtsi" + / { config { u-boot,spl-payload-offset = <0x40000>; /* @ 256KB */ diff --git a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi index 936ce55727..264fb7adf0 100644 --- a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi @@ -2,6 +2,9 @@ /* * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH */ + +#include "rk3368-u-boot.dtsi" + / { chosen { u-boot,spl-boot-order = &emmc; diff --git a/arch/arm/dts/rk3368-sheep-u-boot.dtsi b/arch/arm/dts/rk3368-sheep-u-boot.dtsi index 30ea9e433a..0b724fa45f 100644 --- a/arch/arm/dts/rk3368-sheep-u-boot.dtsi +++ b/arch/arm/dts/rk3368-sheep-u-boot.dtsi @@ -3,6 +3,8 @@ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH */ +#include "rk3368-u-boot.dtsi" + &pinctrl { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/rk3368-u-boot.dtsi b/arch/arm/dts/rk3368-u-boot.dtsi new file mode 100644 index 0000000000..2767c2678d --- /dev/null +++ b/arch/arm/dts/rk3368-u-boot.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH + */ + +#include + +/ { + dmc: dmc@ff610000 { + compatible = "rockchip,rk3368-dmc", "syscon"; + rockchip,cru = <&cru>; + rockchip,grf = <&grf>; + rockchip,msch = <&service_msch>; + reg = <0 0xff610000 0 0x400 + 0 0xff620000 0 0x400>; + }; + + service_msch: syscon@ffac0000 { + compatible = "rockchip,rk3368-msch", "syscon"; + reg = <0x0 0xffac0000 0x0 0x2000>; + }; + + sgrf: syscon@ff740000 { + compatible = "rockchip,rk3368-sgrf", "syscon"; + reg = <0x0 0xff740000 0x0 0x1000>; + }; +}; diff --git a/arch/arm/dts/rk3368.dtsi b/arch/arm/dts/rk3368.dtsi index b4f4f6139d..cd2c322071 100644 --- a/arch/arm/dts/rk3368.dtsi +++ b/arch/arm/dts/rk3368.dtsi @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2015 Heiko Stuebner - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include @@ -45,8 +8,8 @@ #include #include #include +#include #include -#include / { compatible = "rockchip,rk3368"; @@ -108,84 +71,99 @@ }; }; - idle-states { - entry-method = "psci"; - - cpu_sleep: cpu-sleep-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x1010000>; - entry-latency-us = <0x3fffffff>; - exit-latency-us = <0x40000000>; - min-residency-us = <0xffffffff>; - }; - }; - cpu_l0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x0>; - cpu-idle-states = <&cpu_sleep>; enable-method = "psci"; - #cooling-cells = <2>; /* min followed by max */ }; cpu_l1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x1>; - cpu-idle-states = <&cpu_sleep>; enable-method = "psci"; + #cooling-cells = <2>; /* min followed by max */ }; cpu_l2: cpu@2 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x2>; - cpu-idle-states = <&cpu_sleep>; enable-method = "psci"; + #cooling-cells = <2>; /* min followed by max */ }; cpu_l3: cpu@3 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x3>; - cpu-idle-states = <&cpu_sleep>; enable-method = "psci"; + #cooling-cells = <2>; /* min followed by max */ }; cpu_b0: cpu@100 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x100>; - cpu-idle-states = <&cpu_sleep>; enable-method = "psci"; - #cooling-cells = <2>; /* min followed by max */ }; cpu_b1: cpu@101 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x101>; - cpu-idle-states = <&cpu_sleep>; enable-method = "psci"; + #cooling-cells = <2>; /* min followed by max */ }; cpu_b2: cpu@102 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x102>; - cpu-idle-states = <&cpu_sleep>; enable-method = "psci"; + #cooling-cells = <2>; /* min followed by max */ }; cpu_b3: cpu@103 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x103>; - cpu-idle-states = <&cpu_sleep>; enable-method = "psci"; + #cooling-cells = <2>; /* min followed by max */ + }; + }; + + amba: bus { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dmac_peri: dma-controller@ff250000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff250000 0x0 0x4000>; + interrupts = , + ; + #dma-cells = <1>; + arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC_PERI>; + clock-names = "apb_pclk"; + }; + + dmac_bus: dma-controller@ff600000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff600000 0x0 0x4000>; + interrupts = , + ; + #dma-cells = <1>; + arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC_BUS>; + clock-names = "apb_pclk"; }; }; @@ -228,54 +206,45 @@ #clock-cells = <0>; }; - dmc: dmc@ff610000 { - compatible = "rockchip,rk3368-dmc", "syscon"; - rockchip,cru = <&cru>; - rockchip,grf = <&grf>; - rockchip,msch = <&service_msch>; - reg = <0 0xff610000 0 0x400 - 0 0xff620000 0 0x400>; - }; - - service_msch: syscon@ffac0000 { - compatible = "rockchip,rk3368-msch", "syscon"; - reg = <0x0 0xffac0000 0x0 0x2000>; - status = "okay"; - }; - - sdmmc: dwmmc@ff0c0000 { + sdmmc: mmc@ff0c0000 { compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff0c0000 0x0 0x4000>; - clock-freq-min-max = <400000 150000000>; + max-frequency = <150000000>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; interrupts = ; + resets = <&cru SRST_MMC0>; + reset-names = "reset"; status = "disabled"; }; - sdio0: dwmmc@ff0d0000 { + sdio0: mmc@ff0d0000 { compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff0d0000 0x0 0x4000>; - clock-freq-min-max = <400000 150000000>; + max-frequency = <150000000>; clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; - clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; interrupts = ; + resets = <&cru SRST_SDIO0>; + reset-names = "reset"; status = "disabled"; }; - emmc: dwmmc@ff0f0000 { + emmc: mmc@ff0f0000 { compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff0f0000 0x0 0x4000>; - clock-freq-min-max = <400000 150000000>; + max-frequency = <150000000>; clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; interrupts = ; + resets = <&cru SRST_EMMC>; + reset-names = "reset"; status = "disabled"; }; @@ -286,6 +255,8 @@ #io-channel-cells = <1>; clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_SARADC>; + reset-names = "saradc-apb"; status = "disabled"; }; @@ -328,16 +299,16 @@ status = "disabled"; }; - i2c1: i2c@ff140000 { + i2c2: i2c@ff140000 { compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; reg = <0x0 0xff140000 0x0 0x1000>; interrupts = ; #address-cells = <1>; #size-cells = <0>; clock-names = "i2c"; - clocks = <&cru PCLK_I2C1>; + clocks = <&cru PCLK_I2C2>; pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; + pinctrl-0 = <&i2c2_xfer>; status = "disabled"; }; @@ -389,8 +360,6 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer>; status = "disabled"; }; @@ -403,8 +372,6 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-1 = <&uart0_xfer>; status = "disabled"; }; @@ -417,8 +384,6 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_xfer>; status = "disabled"; }; @@ -431,8 +396,6 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart4_xfer>; status = "disabled"; }; @@ -465,12 +428,18 @@ map0 { trip = <&cpu_alert0>; cooling-device = - <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu_alert1>; cooling-device = - <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -498,7 +467,10 @@ map0 { trip = <&gpu_alert0>; cooling-device = - <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -513,9 +485,9 @@ resets = <&cru SRST_TSADC>; reset-names = "tsadc-apb"; pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&otp_gpio>; + pinctrl-0 = <&otp_pin>; pinctrl-1 = <&otp_out>; - pinctrl-2 = <&otp_gpio>; + pinctrl-2 = <&otp_pin>; #thermal-sensor-cells = <1>; rockchip,hw-tshut-temp = <95000>; status = "disabled"; @@ -543,7 +515,6 @@ reg = <0x0 0xff500000 0x0 0x100>; interrupts = ; clocks = <&cru HCLK_HOST0>; - clock-names = "usbhost"; status = "disabled"; }; @@ -558,7 +529,6 @@ g-np-tx-fifo-size = <16>; g-rx-fifo-size = <275>; g-tx-fifo-size = <256 128 128 64 64 32>; - g-use-dma; status = "disabled"; }; @@ -575,16 +545,16 @@ status = "disabled"; }; - i2c2: i2c@ff660000 { + i2c1: i2c@ff660000 { compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; reg = <0x0 0xff660000 0x0 0x1000>; interrupts = ; #address-cells = <1>; #size-cells = <0>; clock-names = "i2c"; - clocks = <&cru PCLK_I2C2>; + clocks = <&cru PCLK_I2C1>; pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; + pinctrl-0 = <&i2c1_xfer>; status = "disabled"; }; @@ -633,7 +603,6 @@ uart2: serial@ff690000 { compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; reg = <0x0 0xff690000 0x0 0x100>; - clock-frequency = <24000000>; clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clock-names = "baudclk", "apb_pclk"; interrupts = ; @@ -654,16 +623,26 @@ clocks = <&cru PCLK_MAILBOX>; clock-names = "pclk_mailbox"; #mbox-cells = <1>; + status = "disabled"; }; pmugrf: syscon@ff738000 { - compatible = "rockchip,rk3368-pmugrf", "syscon"; + compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd"; reg = <0x0 0xff738000 0x0 0x1000>; - }; - sgrf: syscon@ff740000 { - compatible = "rockchip,rk3368-sgrf", "syscon"; - reg = <0x0 0xff740000 0x0 0x1000>; + pmu_io_domains: io-domains { + compatible = "rockchip,rk3368-pmu-io-voltage-domain"; + status = "disabled"; + }; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x200>; + mode-normal = ; + mode-recovery = ; + mode-bootloader = ; + mode-loader = ; + }; }; cru: clock-controller@ff760000 { @@ -675,8 +654,13 @@ }; grf: syscon@ff770000 { - compatible = "rockchip,rk3368-grf", "syscon"; + compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd"; reg = <0x0 0xff770000 0x0 0x1000>; + + io_domains: io-domains { + compatible = "rockchip,rk3368-io-voltage-domain"; + status = "disabled"; + }; }; wdt: watchdog@ff800000 { @@ -693,6 +677,118 @@ interrupts = ; }; + spdif: spdif@ff880000 { + compatible = "rockchip,rk3368-spdif"; + reg = <0x0 0xff880000 0x0 0x1000>; + interrupts = ; + clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; + clock-names = "mclk", "hclk"; + dmas = <&dmac_bus 3>; + dma-names = "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx>; + status = "disabled"; + }; + + i2s_2ch: i2s-2ch@ff890000 { + compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff890000 0x0 0x1000>; + interrupts = ; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>; + dmas = <&dmac_bus 6>, <&dmac_bus 7>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2s_8ch: i2s-8ch@ff898000 { + compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff898000 0x0 0x1000>; + interrupts = ; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>; + dmas = <&dmac_bus 0>, <&dmac_bus 1>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_bus>; + status = "disabled"; + }; + + iep_mmu: iommu@ff900800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff900800 0x0 0x100>; + interrupts = ; + interrupt-names = "iep_mmu"; + clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + status = "disabled"; + }; + + isp_mmu: iommu@ff914000 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff914000 0x0 0x100>, + <0x0 0xff915000 0x0 0x100>; + interrupts = ; + interrupt-names = "isp_mmu"; + clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + rockchip,disable-mmu-reset; + status = "disabled"; + }; + + vop_mmu: iommu@ff930300 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff930300 0x0 0x100>; + interrupts = ; + interrupt-names = "vop_mmu"; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + status = "disabled"; + }; + + hevc_mmu: iommu@ff9a0440 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff9a0440 0x0 0x40>, + <0x0 0xff9a0480 0x0 0x40>; + interrupts = ; + interrupt-names = "hevc_mmu"; + clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + status = "disabled"; + }; + + vpu_mmu: iommu@ff9a0800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff9a0800 0x0 0x100>; + interrupts = , + ; + interrupt-names = "vepu_mmu", "vdpu_mmu"; + clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + status = "disabled"; + }; + + efuse256: efuse@ffb00000 { + compatible = "rockchip,rk3368-efuse"; + reg = <0x0 0xffb00000 0x0 0x20>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru PCLK_EFUSE256>; + clock-names = "pclk_efuse"; + + cpu_leakage: cpu-leakage@17 { + reg = <0x17 0x1>; + }; + temp_adjust: temp-adjust@1f { + reg = <0x1f 0x1>; + }; + }; + gic: interrupt-controller@ffb71000 { compatible = "arm,gic-400"; interrupt-controller; @@ -700,7 +796,7 @@ #address-cells = <0>; reg = <0x0 0xffb71000 0x0 0x1000>, - <0x0 0xffb72000 0x0 0x1000>, + <0x0 0xffb72000 0x0 0x2000>, <0x0 0xffb74000 0x0 0x2000>, <0x0 0xffb76000 0x0 0x2000>; interrupts = ; + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; }; emmc_cmd: emmc-cmd { - rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>; }; emmc_pwr: emmc-pwr { - rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>; }; emmc_bus1: emmc-bus1 { - rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>; }; emmc_bus4: emmc-bus4 { - rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>, - <1 19 RK_FUNC_2 &pcfg_pull_up>, - <1 20 RK_FUNC_2 &pcfg_pull_up>, - <1 21 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>, + <1 RK_PC3 2 &pcfg_pull_up>, + <1 RK_PC4 2 &pcfg_pull_up>, + <1 RK_PC5 2 &pcfg_pull_up>; }; emmc_bus8: emmc-bus8 { - rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>, - <1 19 RK_FUNC_2 &pcfg_pull_up>, - <1 20 RK_FUNC_2 &pcfg_pull_up>, - <1 21 RK_FUNC_2 &pcfg_pull_up>, - <1 22 RK_FUNC_2 &pcfg_pull_up>, - <1 23 RK_FUNC_2 &pcfg_pull_up>, - <1 24 RK_FUNC_2 &pcfg_pull_up>, - <1 25 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>, + <1 RK_PC3 2 &pcfg_pull_up>, + <1 RK_PC4 2 &pcfg_pull_up>, + <1 RK_PC5 2 &pcfg_pull_up>, + <1 RK_PC6 2 &pcfg_pull_up>, + <1 RK_PC7 2 &pcfg_pull_up>, + <1 RK_PD0 2 &pcfg_pull_up>, + <1 RK_PD1 2 &pcfg_pull_up>; }; }; gmac { rgmii_pins: rgmii-pins { - rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>, - <3 24 RK_FUNC_1 &pcfg_pull_none>, - <3 19 RK_FUNC_1 &pcfg_pull_none>, - <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>, - <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>, - <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>, - <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>, - <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>, - <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>, - <3 15 RK_FUNC_1 &pcfg_pull_none>, - <3 16 RK_FUNC_1 &pcfg_pull_none>, - <3 17 RK_FUNC_1 &pcfg_pull_none>, - <3 18 RK_FUNC_1 &pcfg_pull_none>, - <3 25 RK_FUNC_1 &pcfg_pull_none>, - <3 20 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>, + <3 RK_PD0 1 &pcfg_pull_none>, + <3 RK_PC3 1 &pcfg_pull_none>, + <3 RK_PB0 1 &pcfg_pull_none_12ma>, + <3 RK_PB1 1 &pcfg_pull_none_12ma>, + <3 RK_PB2 1 &pcfg_pull_none_12ma>, + <3 RK_PB6 1 &pcfg_pull_none_12ma>, + <3 RK_PD4 1 &pcfg_pull_none_12ma>, + <3 RK_PB5 1 &pcfg_pull_none_12ma>, + <3 RK_PB7 1 &pcfg_pull_none>, + <3 RK_PC0 1 &pcfg_pull_none>, + <3 RK_PC1 1 &pcfg_pull_none>, + <3 RK_PC2 1 &pcfg_pull_none>, + <3 RK_PD1 1 &pcfg_pull_none>, + <3 RK_PC4 1 &pcfg_pull_none>; }; rmii_pins: rmii-pins { - rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>, - <3 24 RK_FUNC_1 &pcfg_pull_none>, - <3 19 RK_FUNC_1 &pcfg_pull_none>, - <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>, - <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>, - <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>, - <3 15 RK_FUNC_1 &pcfg_pull_none>, - <3 16 RK_FUNC_1 &pcfg_pull_none>, - <3 20 RK_FUNC_1 &pcfg_pull_none>, - <3 21 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>, + <3 RK_PD0 1 &pcfg_pull_none>, + <3 RK_PC3 1 &pcfg_pull_none>, + <3 RK_PB0 1 &pcfg_pull_none_12ma>, + <3 RK_PB1 1 &pcfg_pull_none_12ma>, + <3 RK_PB5 1 &pcfg_pull_none_12ma>, + <3 RK_PB7 1 &pcfg_pull_none>, + <3 RK_PC0 1 &pcfg_pull_none>, + <3 RK_PC4 1 &pcfg_pull_none>, + <3 RK_PC5 1 &pcfg_pull_none>; }; }; i2c0 { i2c0_xfer: i2c0-xfer { - rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>, - <0 7 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, + <0 RK_PA7 1 &pcfg_pull_none>; }; }; i2c1 { i2c1_xfer: i2c1-xfer { - rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>, - <2 22 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>, + <2 RK_PC6 1 &pcfg_pull_none>; }; }; i2c2 { i2c2_xfer: i2c2-xfer { - rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>, - <3 31 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <0 RK_PB1 2 &pcfg_pull_none>, + <3 RK_PD7 2 &pcfg_pull_none>; }; }; i2c3 { i2c3_xfer: i2c3-xfer { - rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>, - <1 17 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>, + <1 RK_PC1 1 &pcfg_pull_none>; }; }; i2c4 { i2c4_xfer: i2c4-xfer { - rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>, - <3 25 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>, + <3 RK_PD1 2 &pcfg_pull_none>; }; }; i2c5 { i2c5_xfer: i2c5-xfer { - rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>, - <3 27 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <3 RK_PD2 2 &pcfg_pull_none>, + <3 RK_PD3 2 &pcfg_pull_none>; + }; + }; + + i2s { + i2s_8ch_bus: i2s-8ch-bus { + rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>, + <2 RK_PB5 1 &pcfg_pull_none>, + <2 RK_PB6 1 &pcfg_pull_none>, + <2 RK_PB7 1 &pcfg_pull_none>, + <2 RK_PC0 1 &pcfg_pull_none>, + <2 RK_PC1 1 &pcfg_pull_none>, + <2 RK_PC2 1 &pcfg_pull_none>, + <2 RK_PC3 1 &pcfg_pull_none>, + <2 RK_PC4 1 &pcfg_pull_none>; }; }; pwm0 { pwm0_pin: pwm0-pin { - rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <3 RK_PB0 2 &pcfg_pull_none>; }; }; pwm1 { pwm1_pin: pwm1-pin { - rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <0 RK_PB0 2 &pcfg_pull_none>; }; }; pwm3 { pwm3_pin: pwm3-pin { - rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>; + rockchip,pins = <3 RK_PD5 3 &pcfg_pull_none>; }; }; sdio0 { sdio0_bus1: sdio0-bus1 { - rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>; }; sdio0_bus4: sdio0-bus4 { - rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>, - <2 29 RK_FUNC_1 &pcfg_pull_up>, - <2 30 RK_FUNC_1 &pcfg_pull_up>, - <2 31 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>, + <2 RK_PD5 1 &pcfg_pull_up>, + <2 RK_PD6 1 &pcfg_pull_up>, + <2 RK_PD7 1 &pcfg_pull_up>; }; sdio0_cmd: sdio0-cmd { - rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <3 RK_PA0 1 &pcfg_pull_up>; }; sdio0_clk: sdio0-clk { - rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>; }; sdio0_cd: sdio0-cd { - rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <3 RK_PA2 1 &pcfg_pull_up>; }; sdio0_wp: sdio0-wp { - rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <3 RK_PA3 1 &pcfg_pull_up>; }; sdio0_pwr: sdio0-pwr { - rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <3 RK_PA4 1 &pcfg_pull_up>; }; sdio0_bkpwr: sdio0-bkpwr { - rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <3 RK_PA5 1 &pcfg_pull_up>; }; sdio0_int: sdio0-int { - rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>; }; }; sdmmc { sdmmc_clk: sdmmc-clk { - rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>; }; sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>; }; sdmmc_cd: sdmmc-cd { - rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>; }; sdmmc_bus1: sdmmc-bus1 { - rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>; }; sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>, - <2 6 RK_FUNC_1 &pcfg_pull_up>, - <2 7 RK_FUNC_1 &pcfg_pull_up>, - <2 8 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>, + <2 RK_PA6 1 &pcfg_pull_up>, + <2 RK_PA7 1 &pcfg_pull_up>, + <2 RK_PB0 1 &pcfg_pull_up>; + }; + }; + + spdif { + spdif_tx: spdif-tx { + rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; }; }; spi0 { spi0_clk: spi0-clk { - rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <1 RK_PD5 2 &pcfg_pull_up>; }; spi0_cs0: spi0-cs0 { - rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>; + rockchip,pins = <1 RK_PD0 3 &pcfg_pull_up>; }; spi0_cs1: spi0-cs1 { - rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>; + rockchip,pins = <1 RK_PD1 3 &pcfg_pull_up>; }; spi0_tx: spi0-tx { - rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>; + rockchip,pins = <1 RK_PC7 3 &pcfg_pull_up>; }; spi0_rx: spi0-rx { - rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>; + rockchip,pins = <1 RK_PC6 3 &pcfg_pull_up>; }; }; spi1 { spi1_clk: spi1-clk { - rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>; }; spi1_cs0: spi1-cs0 { - rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <1 RK_PB7 2 &pcfg_pull_up>; }; spi1_cs1: spi1-cs1 { - rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <3 RK_PD4 2 &pcfg_pull_up>; }; spi1_rx: spi1-rx { - rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <1 RK_PC0 2 &pcfg_pull_up>; }; spi1_tx: spi1-tx { - rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <1 RK_PC1 2 &pcfg_pull_up>; }; }; spi2 { spi2_clk: spi2-clk { - rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <0 RK_PB4 2 &pcfg_pull_up>; }; spi2_cs0: spi2-cs0 { - rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>; }; spi2_rx: spi2-rx { - rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <0 RK_PB2 2 &pcfg_pull_up>; }; spi2_tx: spi2-tx { - rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>; }; }; tsadc { - otp_gpio: otp-gpio { - rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>; + otp_pin: otp-pin { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; }; otp_out: otp-out { - rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; }; }; uart0 { uart0_xfer: uart0-xfer { - rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>, - <2 25 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up>, + <2 RK_PD1 1 &pcfg_pull_none>; }; uart0_cts: uart0-cts { - rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>; }; uart0_rts: uart0-rts { - rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>; }; }; uart1 { uart1_xfer: uart1-xfer { - rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>, - <0 21 RK_FUNC_3 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC4 3 &pcfg_pull_up>, + <0 RK_PC5 3 &pcfg_pull_none>; }; uart1_cts: uart1-cts { - rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC6 3 &pcfg_pull_none>; }; uart1_rts: uart1-rts { - rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC7 3 &pcfg_pull_none>; }; }; uart2 { uart2_xfer: uart2-xfer { - rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>, - <2 5 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA6 2 &pcfg_pull_up>, + <2 RK_PA5 2 &pcfg_pull_none>; }; /* no rts / cts for uart2 */ }; uart3 { uart3_xfer: uart3-xfer { - rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>, - <3 30 RK_FUNC_3 &pcfg_pull_none>; + rockchip,pins = <3 RK_PD5 2 &pcfg_pull_up>, + <3 RK_PD6 3 &pcfg_pull_none>; }; uart3_cts: uart3-cts { - rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>; }; uart3_rts: uart3-rts { - rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <3 RK_PC1 2 &pcfg_pull_none>; }; }; uart4 { uart4_xfer: uart4-xfer { - rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>, - <0 26 RK_FUNC_3 &pcfg_pull_none>; + rockchip,pins = <0 RK_PD3 3 &pcfg_pull_up>, + <0 RK_PD2 3 &pcfg_pull_none>; }; uart4_cts: uart4-cts { - rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>; + rockchip,pins = <0 RK_PD0 3 &pcfg_pull_none>; }; uart4_rts: uart4-rts { - rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>; + rockchip,pins = <0 RK_PD1 3 &pcfg_pull_none>; }; }; }; From ba421b96a25d268900f674a20d219118776edce6 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 9 Feb 2021 14:47:09 +0100 Subject: [PATCH 08/17] rockchip: rk3368: sync down rk3368-lion board devicetree from Linux This brings the actual rk3368-lion devicetree files from Linux 5.10 instead of using something separate. Signed-off-by: Heiko Stuebner Reviewed-by: Kever Yang --- arch/arm/dts/Makefile | 2 +- ...ot.dtsi => rk3368-lion-haikou-u-boot.dtsi} | 4 + arch/arm/dts/rk3368-lion-haikou.dts | 140 +++++++++ .../dts/{rk3368-lion.dts => rk3368-lion.dtsi} | 271 +++++++++++++----- configs/lion-rk3368_defconfig | 2 + 5 files changed, 351 insertions(+), 68 deletions(-) rename arch/arm/dts/{rk3368-lion-u-boot.dtsi => rk3368-lion-haikou-u-boot.dtsi} (98%) create mode 100644 arch/arm/dts/rk3368-lion-haikou.dts rename arch/arm/dts/{rk3368-lion.dts => rk3368-lion.dtsi} (54%) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9a8de46272..dd4d4efed3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -114,7 +114,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \ rk3328-rock-pi-e.dtb dtb-$(CONFIG_ROCKCHIP_RK3368) += \ - rk3368-lion.dtb \ + rk3368-lion-haikou.dtb \ rk3368-sheep.dtb \ rk3368-geekbox.dtb \ rk3368-px5-evb.dtb \ diff --git a/arch/arm/dts/rk3368-lion-u-boot.dtsi b/arch/arm/dts/rk3368-lion-haikou-u-boot.dtsi similarity index 98% rename from arch/arm/dts/rk3368-lion-u-boot.dtsi rename to arch/arm/dts/rk3368-lion-haikou-u-boot.dtsi index 9bd6352755..7826d1e70b 100644 --- a/arch/arm/dts/rk3368-lion-u-boot.dtsi +++ b/arch/arm/dts/rk3368-lion-haikou-u-boot.dtsi @@ -38,6 +38,10 @@ }; }; +&gpio2 { + u-boot,dm-pre-reloc; +}; + &pinctrl { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/rk3368-lion-haikou.dts b/arch/arm/dts/rk3368-lion-haikou.dts new file mode 100644 index 0000000000..7fcb1eacea --- /dev/null +++ b/arch/arm/dts/rk3368-lion-haikou.dts @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Theobroma Systems Design und Consulting GmbH + */ + +/dts-v1/; +#include "rk3368-lion.dtsi" + +/ { + model = "Theobroma Systems RK3368-uQ7 Baseboard"; + compatible = "tsd,rk3368-lion-haikou", "rockchip,rk3368"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + i2cmux2 { + i2c@0 { + eeprom: eeprom@50 { + compatible = "atmel,24c01"; + pagesize = <8>; + reg = <0x50>; + }; + }; + }; + + leds { + pinctrl-0 = <&module_led_pins>, <&sd_card_led_pin>; + + sd_card_led: led-3 { + label = "sd_card_led"; + gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + }; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_baseboard: vcc3v3-baseboard { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_baseboard"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + regulator-name = "vcc5v0_otg"; + regulator-always-on; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio2 RK_PB3 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <25000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; + rockchip,default-sample-phase = <90>; + vmmc-supply = <&vcc3v3_baseboard>; + status = "okay"; +}; + +&spi2 { + cs-gpios = <0>, <&gpio2 RK_PC3 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "okay"; +}; + +&uart1 { + /* alternate function of GPIO5/6 */ + status = "disabled"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&haikou_pin_hog>; + + hog { + haikou_pin_hog: haikou-pin-hog { + rockchip,pins = + /* LID_BTN */ + <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, + /* BATLOW# */ + <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>, + /* SLP_BTN# */ + <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>, + /* BIOS_DISABLE# */ + <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + sd_card_led_pin: sd-card-led-pin { + rockchip,pins = + <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + sdmmc_cd_pin: sdmmc-cd-pin { + rockchip,pins = + <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb_otg { + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = + <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm/dts/rk3368-lion.dts b/arch/arm/dts/rk3368-lion.dtsi similarity index 54% rename from arch/arm/dts/rk3368-lion.dts rename to arch/arm/dts/rk3368-lion.dtsi index 2814542083..532e6a6828 100644 --- a/arch/arm/dts/rk3368-lion.dts +++ b/arch/arm/dts/rk3368-lion.dtsi @@ -1,25 +1,14 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + * Copyright (c) 2018 Theobroma Systems Design und Consulting GmbH */ /dts-v1/; #include "rk3368.dtsi" -#include "rk3368-lion-u-boot.dtsi" -#include / { - model = "Theobroma Systems RK3368-uQ7 SoM"; - compatible = "tsd,rk3368-uq7", "tsd,lion", "rockchip,rk3368"; - - aliases { - mmc0 = &emmc; - mmc1 = &sdmmc; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; + chosen { + stdout-path = "serial0:115200n8"; }; ext_gmac: gmac-clk { @@ -29,6 +18,80 @@ #clock-cells = <0>; }; + i2cmux1 { + compatible = "i2c-mux-gpio"; + #address-cells = <1>; + #size-cells = <0>; + i2c-parent = <&i2c1>; + mux-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + + /* Q7_GPO_I2C */ + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* Q7_SMB */ + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + i2cmux2 { + compatible = "i2c-mux-gpio"; + #address-cells = <1>; + #size-cells = <0>; + i2c-parent = <&i2c2>; + mux-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + + /* Q7_LVDS_BLC_I2C */ + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + fan: fan@18 { + compatible = "ti,amc6821"; + reg = <0x18>; + #cooling-cells = <2>; + }; + + rtc_twi: rtc@6f { + compatible = "isil,isl1208"; + reg = <0x6f>; + }; + }; + + /* Q7_GP2_I2C */ + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&module_led_pins>; + + module_led1: led-1 { + label = "module_led1"; + gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + panic-indicator; + }; + + module_led2: led-2 { + label = "module_led2"; + gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + vcc_sys: vcc-sys-regulator { compatible = "regulator-fixed"; regulator-name = "vcc_sys"; @@ -39,43 +102,81 @@ }; }; -&uart0 { - status = "okay"; +&cpu_l0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu>; }; &emmc { - status = "okay"; bus-width = <8>; - cap-mmc-highspeed; clock-frequency = <150000000>; - disable-wp; - keep-power-in-suspend; + mmc-hs200-1_8v; non-removable; - num-slots = <1>; vmmc-supply = <&vcc33_io>; vqmmc-supply = <&vcc18_io>; pinctrl-names = "default"; pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>; -}; - -&sdmmc { status = "okay"; }; &gmac { - status = "okay"; - phy-supply = <&vcc33_io>; - phy-mode = "rgmii"; - clock_in_out = "input"; - snps,reset-gpio = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <2 10000 50000>; assigned-clocks = <&cru SCLK_MAC>; assigned-clock-parents = <&ext_gmac>; + clock_in_out = "input"; + phy-handle = <&phy0>; + phy-supply = <&vcc33_io>; + phy-mode = "rgmii"; pinctrl-names = "default"; pinctrl-0 = <&rgmii_pins>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + snps,reset-gpio = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>; tx_delay = <0x10>; rx_delay = <0x10>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + /* Microsemi VSC8531-02 */ + phy0: phy@0 { + compatible = "ethernet-phy-id0007.0570"; + reg = <0>; + vsc8531,clk-out-frequency = <125000000>; + vsc8531,edge-slowdown = <7>; + vsc8531,led-0-mode = <1>; + vsc8531,led-1-mode = <2>; + }; + }; }; &i2c0 { @@ -85,7 +186,11 @@ compatible = "rockchip,rk808"; reg = <0x1b>; interrupt-parent = <&gpio0>; - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; + clock-output-names = "xin32k", "rk808-clkout2"; + #clock-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>, <&pmic_sleep>; rockchip,system-power-controller; vcc1-supply = <&vcc_sys>; vcc2-supply = <&vcc_sys>; @@ -98,97 +203,129 @@ vcc10-supply = <&vcc_sys>; vcc11-supply = <&vcc_sys>; vcc12-supply = <&vcc_sys>; - clock-output-names = "xin32k", "rk808-clkout2"; - #clock-cells = <1>; regulators { vdd_cpu: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; + regulator-name = "vdd_cpu"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1500000>; - regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; }; vdd_log: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; + regulator-name = "vdd_log"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1500000>; - regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; }; vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; regulator-always-on; regulator-boot-on; - regulator-name = "vcc_ddr"; }; vcc33_io: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; + regulator-name = "vcc33_io"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-name = "vcc33_io"; + regulator-always-on; + regulator-boot-on; }; vcc33_video: LDO_REG2 { - regulator-always-on; - regulator-boot-on; + regulator-name = "vcc33_video"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-name = "vcc33_video"; + regulator-always-on; + regulator-boot-on; }; vdd10_pll: LDO_REG3 { - regulator-always-on; - regulator-boot-on; + regulator-name = "vdd10_pll"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; - regulator-name = "vdd10_pll"; + regulator-always-on; + regulator-boot-on; }; vcc18_io: LDO_REG4 { - regulator-boot-on; + regulator-name = "vcc18_io"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_io"; + regulator-boot-on; }; vdd10_video: LDO_REG6 { - regulator-always-on; - regulator-boot-on; + regulator-name = "vdd10_video"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; - regulator-name = "vdd10_video"; + regulator-always-on; + regulator-boot-on; }; vcc18_video: LDO_REG8 { - regulator-always-on; - regulator-boot-on; + regulator-name = "vcc18_video"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_video"; + regulator-always-on; + regulator-boot-on; }; }; }; }; -&uart0 { +&i2c1 { status = "okay"; }; +&i2c2 { + status = "okay"; +}; + +&pinctrl { + leds { + module_led_pins: module-led-pins { + rockchip,pins = + <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>, + <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + pmic_sleep: pmic-sleep { + rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; + }; + }; +}; + &spi1 { status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - spiflash: w25q32dw@0 { + norflash: flash@0 { compatible = "jedec,spi-nor"; reg = <0>; - spi-max-frequency = <49500000>; - spi-cpol; - spi-cpha; + spi-max-frequency = <50000000>; }; }; + +&uart1 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig index b409715060..f547875dee 100644 --- a/configs/lion-rk3368_defconfig +++ b/configs/lion-rk3368_defconfig @@ -32,6 +32,7 @@ CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200 CONFIG_SPL_ATF=y CONFIG_TPL=y @@ -44,6 +45,7 @@ CONFIG_CMD_MTDPARTS=y CONFIG_SPL_OF_CONTROL=y CONFIG_TPL_OF_CONTROL=y CONFIG_OF_LIVE=y +CONFIG_DEFAULT_DEVICE_TREE="rk3368-lion-haikou" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent" CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y From 439fdaa26a85ff06858f632c3c8056cb8f846ab8 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 9 Feb 2021 14:47:10 +0100 Subject: [PATCH 09/17] rockchip: lion: update board defconfig Adds the needed target option and drivers needed for correct bringup. Signed-off-by: Heiko Stuebner Reviewed-by: Kever Yang --- configs/lion-rk3368_defconfig | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig index f547875dee..6d6b73d977 100644 --- a/configs/lion-rk3368_defconfig +++ b/configs/lion-rk3368_defconfig @@ -9,6 +9,7 @@ CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0 CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_TARGET_LION_RK3368=y CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xFF180000 CONFIG_DEBUG_UART_CLOCK=24000000 @@ -39,6 +40,8 @@ CONFIG_TPL=y CONFIG_TPL_DRIVERS_MISC_SUPPORT=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y CONFIG_CMD_BOOTSTAGE=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_MTDPARTS=y @@ -62,14 +65,15 @@ CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_TPL_CLK=y CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MTD=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_PHY_MSCC=y CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y CONFIG_GMAC_ROCKCHIP=y @@ -78,6 +82,7 @@ CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_TPL_RAM=y @@ -88,6 +93,13 @@ CONFIG_ROCKCHIP_SPI=y CONFIG_SYSINFO=y CONFIG_SYSINFO_SMBIOS=y CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_DWC2=y +CONFIG_ROCKCHIP_USB2_PHY=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_SPL_TINY_MEMSET=y CONFIG_LZO=y CONFIG_ERRNO_STR=y From 44e1ad40e9e679006b572895293d2ba4efeb9968 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Sun, 14 Feb 2021 19:40:15 +0000 Subject: [PATCH 10/17] include: configs: rk3399: drop a dangling comment Drop a irrelevent comment now the related configs have moved to the various config files. Signed-off-by: Peter Robinson Reviewed-by: Kever Yang --- include/configs/rk3399_common.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index d0fc598319..b37ed5cce0 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -75,6 +75,4 @@ #endif -/* enable usb config for usb ether */ - #endif From 98c79622918d91b70dc3f172731b065814e2755b Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Sun, 14 Feb 2021 19:43:28 +0000 Subject: [PATCH 11/17] rockchip: rk3399: rock960: explicitly disable SPI flash The Rock960 doesn't have SPI flash on-board, but the bits get enabled by default which means when booting we get some errors. Explicitly disable it to stop the errors. Signed-off-by: Peter Robinson Reviewed-by: Kever Yang --- configs/rock960-rk3399_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 28d1fc53a5..9f1aeaa46f 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -23,6 +23,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_SF is not set CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y From 1621afc84f8a109cfdb98c9e370c355289e07870 Mon Sep 17 00:00:00 2001 From: Christoph Muellner Date: Fri, 19 Feb 2021 01:29:48 +0100 Subject: [PATCH 12/17] rockchip: rk3399-puma: Restore correct VDD_LOG supply. A commit from last year re-imported the DTS files form the upstream kernel. By doing so the VDD_LOG regulator in the board's DTS was dropped. Let's restore this, but move it into the u-boot overlay to prevent this issue in the future. Fixes: 167efc2c7a46 ("arm64: dts: rk3399: Sync v5.7-rc1 from Linux") Signed-off-by: Christoph Muellner Reviewed-by: Heiko Stuebner Reviewed-by: Kever Yang --- arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi b/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi index e7a1aea3a5..e0476ab25c 100644 --- a/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi +++ b/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi @@ -48,6 +48,18 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-init-microvolt = <950000>; + vin-supply = <&vcc5v0_sys>; + }; }; &gpio1 { From 8a5a88308dd485f9203d7b5a38a75202e9f29853 Mon Sep 17 00:00:00 2001 From: Christoph Muellner Date: Fri, 19 Feb 2021 01:30:02 +0100 Subject: [PATCH 13/17] rockchip: rk3399-puma: Increase environment size to 16 kiB. On Puma we have the environment at an offset of 16 kiB. On the eMMC this gives us 16 kiB for the environment before the SPL starts. On the SPI NOR we also have 16 kiB until end of flash. So let's increase the environment size from 8 kiB to its maximum of 16 kiB for both MMC and SPI NOR. Signed-off-by: Christoph Muellner Reviewed-by: Heiko Stuebner Reviewed-by: Kever Yang --- board/theobroma-systems/puma_rk3399/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/theobroma-systems/puma_rk3399/Kconfig b/board/theobroma-systems/puma_rk3399/Kconfig index e82623a170..21946d984d 100644 --- a/board/theobroma-systems/puma_rk3399/Kconfig +++ b/board/theobroma-systems/puma_rk3399/Kconfig @@ -13,7 +13,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y config ENV_SIZE - default 0x2000 + default 0x4000 config ENV_OFFSET default 0x3fc000 if ENV_IS_IN_SPI_FLASH From 4e456fb636bceee31f65415ed41c44cfb23e0257 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Date: Mon, 22 Feb 2021 10:25:58 +0100 Subject: [PATCH 14/17] odroid-go2: do not disable EFI MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove the unset of the EFI loader, it's possible for U-Boot to provide a EFI environment on this board, and it's also required by the FreeBSD loader which mandated EFI on Aarch64. Signed-off-by: Roger Pau Monné Reviewed-by: Kever Yang --- configs/odroid-go2_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig index 5632b15611..be7ba09334 100644 --- a/configs/odroid-go2_defconfig +++ b/configs/odroid-go2_defconfig @@ -109,4 +109,3 @@ CONFIG_SPL_TINY_MEMSET=y CONFIG_TPL_TINY_MEMSET=y CONFIG_LZO=y CONFIG_ERRNO_STR=y -# CONFIG_EFI_LOADER is not set From 253b151d489dd3186bc27699b1ab551a29265759 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Date: Mon, 22 Feb 2021 10:25:59 +0100 Subject: [PATCH 15/17] odroid-go2: fix default FDT file path The path in the Linux kernel dts directory is rockchip/rk3326-odroid-go2.dtb. That also seems to match the FDT path set on other boards (ie: rock64-rk3328 for example). Signed-off-by: Roger Pau Monne Reviewed-by: Kever Yang --- configs/odroid-go2_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig index be7ba09334..6aa41e3755 100644 --- a/configs/odroid-go2_defconfig +++ b/configs/odroid-go2_defconfig @@ -24,7 +24,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_BEST_MATCH=y CONFIG_SPL_LOAD_FIT=y -CONFIG_DEFAULT_FDT_FILE="rk3326-odroidgo2.dtb" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3326-odroid-go2.dtb" # CONFIG_CONSOLE_MUX is not set # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y From b69b9f3f54732c303939eb748aad97cd4cf60168 Mon Sep 17 00:00:00 2001 From: Xiaobo Tian Date: Sat, 27 Feb 2021 22:39:11 +0800 Subject: [PATCH 16/17] arm64: rk3399: Add support NanoPi R4s NanoPi R4s is SBC base on Rockchip RK3399 hexa-core processor with dual-Core Cortex-A72 and Mali-T864 GPU with 4GiB(LPDDR4) of RAM, SD card support, including 2 gigabit ethernet(RTL8211E 1Gbps - RTL8111H 1Gbps) and 2 USB 3.0 port. port.It also has two GPIO headers which allows further peripherals to be used. The devicetree file is taken of the rk3399 nanopi4 Linux kernel [1]. [1] https://github.com/torvalds/linux/commit/e7a095908227fb3ccc86d001d9e13c9ae2bef8e6 Signed-off-by: xiaobo Reviewed-by: Kever Yang --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi | 16 +++ arch/arm/dts/rk3399-nanopi-r4s.dts | 138 +++++++++++++++++++++ board/rockchip/evb_rk3399/MAINTAINERS | 6 + configs/nanopi-r4s-rk3399_defconfig | 62 +++++++++ 5 files changed, 223 insertions(+) create mode 100644 arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-nanopi-r4s.dts create mode 100644 configs/nanopi-r4s-rk3399_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index dd4d4efed3..0a13947381 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -132,6 +132,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-nanopi-m4.dtb \ rk3399-nanopi-m4-2gb.dtb \ rk3399-nanopi-neo4.dtb \ + rk3399-nanopi-r4s.dtb \ rk3399-orangepi.dtb \ rk3399-pinebook-pro.dtb \ rk3399-puma-haikou.dtb \ diff --git a/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi new file mode 100644 index 0000000000..cd1642527b --- /dev/null +++ b/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * RK3399-based FriendlyElec boards device tree source + * + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd + * + * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * Copyright (c) 2018 Collabora Ltd. + * Copyright (c) 2019 Arm Ltd. + * Copyright (C) 2020 Xiaobo + */ + +#include "rk3399-nanopi4-u-boot.dtsi" +#include "rk3399-sdram-lpddr4-100.dtsi" diff --git a/arch/arm/dts/rk3399-nanopi-r4s.dts b/arch/arm/dts/rk3399-nanopi-r4s.dts new file mode 100644 index 0000000000..6f2cf17bf1 --- /dev/null +++ b/arch/arm/dts/rk3399-nanopi-r4s.dts @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd + * + * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * Copyright (c) 2018 Collabora Ltd. + * Copyright (c) 2019 Arm Ltd. + * Copyright (C) 2020 Xiaobo + */ + +/dts-v1/; +#include "rk3399-nanopi4.dtsi" + +/ { + model = "FriendlyElec NanoPi R4S"; + compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399"; + + aliases { + ethernet1 = &r8169; + }; + + vdd_5v: vdd-5v { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v"; + regulator-always-on; + regulator-boot-on; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <0 12 18 255>; + #cooling-cells = <2>; + fan-supply = <&vdd_5v>; + pwms = <&pwm1 0 50000 0>; + }; +}; + +&cpu_thermal { + trips { + cpu_warm: cpu_warm { + temperature = <55000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_hot: cpu_hot { + temperature = <65000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map2 { + trip = <&cpu_warm>; + cooling-device = <&fan THERMAL_NO_LIMIT 1>; + }; + + map3 { + trip = <&cpu_hot>; + cooling-device = <&fan 2 THERMAL_NO_LIMIT>; + }; + }; +}; + +&emmc_phy { + status = "disabled"; +}; + +&fusb0 { + status = "disabled"; +}; + +&leds { + lan_led: led-1 { + gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; + label = "nanopi-r4s:green:lan"; + }; + + wan_led: led-2 { + gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; + label = "nanopi-r4s:green:wan"; + }; +}; + +&leds_gpio { + rockchip,pins = + <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; +}; + +&pcie0 { + max-link-speed = <1>; + num-lanes = <1>; + vpcie3v3-supply = <&vcc3v3_sys>; + + pcie@0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + r8169: pcie@0,0 { + reg = <0x000000 0 0 0 0>; + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; +}; + +&sdhci { + status = "disabled"; +}; + +&sdio0 { + status = "disabled"; +}; + +&sdmmc { + host-index-min = <1>; +}; + +&u2phy0_host { + phy-supply = <&vdd_5v>; +}; + +&u2phy1_host { + status = "disabled"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "host"; +}; + +&vcc3v3_sys { + vin-supply = <&vcc5v0_sys>; +}; diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index 4c889e06a6..3b9d60eccd 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -55,6 +55,12 @@ S: Maintained F: configs/nanopi-neo4-rk3399_defconfig F: arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi +NANOPI-R4S +M: Xiaobo Tian +S: Maintained +F: configs/nanopi-r4s-rk3399_defconfig +F: arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi + ORANGEPI-RK3399 M: Jagan Teki S: Maintained diff --git a/configs/nanopi-r4s-rk3399_defconfig b/configs/nanopi-r4s-rk3399_defconfig new file mode 100644 index 0000000000..0a3c28b012 --- /dev/null +++ b/configs/nanopi-r4s-rk3399_defconfig @@ -0,0 +1,62 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_TARGET_EVB_RK3399=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4s.dtb" +CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_TPL=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4s" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM_RK3399_LPDDR4=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y From a99d70c180dc083b47673b5f0282fc8ba8193bc9 Mon Sep 17 00:00:00 2001 From: Alexandre Vicenzi Date: Fri, 26 Mar 2021 13:37:10 +0100 Subject: [PATCH 17/17] board: dts: rockchip: Add NanoPi M4B Add initial support for NanoPi M4B, a minor revision of the original NanoPi M4. Commit details of rk3399-nanopi-m4b.dts sync from Linux 5.12-rc4: "arm64: dts: rockchip: Add NanoPi M4B board" (sha1: c7b03115003f7f337ab165542cee37148cf30a8a) Signed-off-by: Alexandre Vicenzi Reviewed-by: Kever Yang --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-nanopi-m4b-u-boot.dtsi | 7 +++ arch/arm/dts/rk3399-nanopi-m4b.dts | 52 ++++++++++++++++++ board/rockchip/evb_rk3399/MAINTAINERS | 6 +++ configs/nanopi-m4b-rk3399_defconfig | 61 ++++++++++++++++++++++ doc/board/rockchip/rockchip.rst | 1 + 6 files changed, 128 insertions(+) create mode 100644 arch/arm/dts/rk3399-nanopi-m4b-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-nanopi-m4b.dts create mode 100644 configs/nanopi-m4b-rk3399_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0a13947381..cedddd370f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -131,6 +131,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-nanopc-t4.dtb \ rk3399-nanopi-m4.dtb \ rk3399-nanopi-m4-2gb.dtb \ + rk3399-nanopi-m4b.dtb \ rk3399-nanopi-neo4.dtb \ rk3399-nanopi-r4s.dtb \ rk3399-orangepi.dtb \ diff --git a/arch/arm/dts/rk3399-nanopi-m4b-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi-m4b-u-boot.dtsi new file mode 100644 index 0000000000..9c3c1ef810 --- /dev/null +++ b/arch/arm/dts/rk3399-nanopi-m4b-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 Alexandre Vicenzi + */ + +#include "rk3399-nanopi4-u-boot.dtsi" +#include "rk3399-sdram-ddr3-1866.dtsi" diff --git a/arch/arm/dts/rk3399-nanopi-m4b.dts b/arch/arm/dts/rk3399-nanopi-m4b.dts new file mode 100644 index 0000000000..72182c58cc --- /dev/null +++ b/arch/arm/dts/rk3399-nanopi-m4b.dts @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * FriendlyElec NanoPi M4B board device tree source + * + * Copyright (c) 2020 Chen-Yu Tsai + */ + +/dts-v1/; +#include "rk3399-nanopi-m4.dts" + +/ { + model = "FriendlyElec NanoPi M4B"; + compatible = "friendlyarm,nanopi-m4b", "rockchip,rk3399"; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1500000>; + poll-interval = <100>; + + recovery { + label = "Recovery"; + linux,code = ; + press-threshold-microvolt = <18000>; + }; + }; +}; + +/* No USB type-C PD power manager */ +/delete-node/ &fusb0; + +&i2c4 { + status = "disabled"; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_usb2>; +}; + +&u2phy0_otg { + phy-supply = <&vbus_typec>; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_usb1>; +}; + +&vbus_typec { + enable-active-high; + gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; +}; diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index 3b9d60eccd..25e308d186 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -49,6 +49,12 @@ S: Maintained F: configs/nanopi-m4-2gb-rk3399_defconfig F: arch/arm/dts/rk3399-nanopi-m4-2gb-u-boot.dtsi +NANOPI-M4B +M: Alexandre Vicenzi +S: Maintained +F: configs/nanopi-m4b-rk3399_defconfig +F: arch/arm/dts/rk3399-nanopi-m4b-u-boot.dtsi + NANOPI-NEO4 M: Jagan Teki S: Maintained diff --git a/configs/nanopi-m4b-rk3399_defconfig b/configs/nanopi-m4b-rk3399_defconfig new file mode 100644 index 0000000000..eceb67e736 --- /dev/null +++ b/configs/nanopi-m4b-rk3399_defconfig @@ -0,0 +1,61 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_TARGET_EVB_RK3399=y +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4b" +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4b.dtb" +CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_TPL=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 955e6858f2..fbb9983988 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -61,6 +61,7 @@ List of mainline supported rockchip boards: - Firefly ROC-RK3399-PC - FriendlyElec NanoPC-T4 (nanopc-t4-rk3399) - FriendlyElec NanoPi M4 (nanopi-m4-rk3399) + - FriendlyElec NanoPi M4B (nanopi-m4b-rk3399) - FriendlyARM NanoPi NEO4 (nanopi-neo4-rk3399) - Google Bob (chromebook_bob) - Khadas Edge (khadas-edge-rk3399)