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https://github.com/brain-hackers/u-boot-brain
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powerpc: mpc5xxx: remove aev, TB5200 board support
They have not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Masahiro Yamada
Tom Rini
parent
2da8137b45
commit
470ee8b125
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@ -65,15 +65,9 @@ config TARGET_DIGSY_MTC
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config TARGET_PCM030
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bool "Support pcm030"
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config TARGET_AEV
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bool "Support aev"
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config TARGET_CHARON
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bool "Support charon"
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config TARGET_TB5200
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bool "Support TB5200"
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config TARGET_TQM5200
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bool "Support TQM5200"
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@ -1,16 +1,3 @@
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if TARGET_AEV
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config SYS_BOARD
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default "tqm5200"
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config SYS_VENDOR
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default "tqc"
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config SYS_CONFIG_NAME
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default "aev"
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endif
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if TARGET_CHARON
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config SYS_BOARD
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@ -24,19 +11,6 @@ config SYS_CONFIG_NAME
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endif
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if TARGET_TB5200
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config SYS_BOARD
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default "tqm5200"
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config SYS_VENDOR
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default "tqc"
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config SYS_CONFIG_NAME
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default "TB5200"
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endif
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if TARGET_TQM5200
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config SYS_BOARD
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@ -9,9 +9,6 @@ F: configs/cam5200_defconfig
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F: configs/cam5200_niosflash_defconfig
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F: configs/fo300_defconfig
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F: configs/MiniFAP_defconfig
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F: include/configs/TB5200.h
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F: configs/TB5200_defconfig
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F: configs/TB5200_B_defconfig
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F: configs/TQM5200_defconfig
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F: configs/TQM5200_B_defconfig
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F: configs/TQM5200_B_HIGHBOOT_defconfig
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@ -5,4 +5,4 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := tqm5200.o cmd_stk52xx.o cmd_tb5200.o cam5200_flash.o
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obj-y := tqm5200.o cmd_stk52xx.o cam5200_flash.o
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@ -1,88 +0,0 @@
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/*
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* (C) Copyright 2005 - 2006
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* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* TB5200 specific functions
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*/
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/*#define DEBUG*/
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#include <common.h>
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#include <command.h>
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#if defined(CONFIG_CMD_BSP)
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#if defined (CONFIG_TB5200)
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#define SM501_PANEL_DISPLAY_CONTROL 0x00080000UL
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static void led_init(void)
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{
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struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
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/* configure timer 4 for simple GPIO output */
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gpt->gpt4.emsr |= 0x00000024;
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}
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int cmd_led(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
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led_init();
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if (strcmp (argv[1], "on") == 0) {
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debug ("switch status LED on\n");
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gpt->gpt4.emsr |= (1 << 4);
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} else if (strcmp (argv[1], "off") == 0) {
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debug ("switch status LED off\n");
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gpt->gpt4.emsr &= ~(1 << 4);
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} else {
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printf ("Usage:\nled on/off\n");
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return 1;
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}
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return 0;
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}
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static void sm501_backlight (unsigned int state)
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{
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if (state == 1) {
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*(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) |=
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(1 << 26) | (1 << 27);
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} else if (state == 0)
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*(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) &=
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~((1 << 26) | (1 << 27));
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}
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int cmd_backlight(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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if (strcmp (argv[1], "on") == 0) {
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debug ("switch backlight on\n");
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sm501_backlight (1);
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} else if (strcmp (argv[1], "off") == 0) {
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debug ("switch backlight off\n");
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sm501_backlight (0);
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} else {
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printf ("Usage:\nbacklight on/off\n");
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return 1;
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}
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return 0;
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}
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U_BOOT_CMD(
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led , 2, 1, cmd_led,
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"switch status LED on or off",
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"on/off"
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);
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U_BOOT_CMD(
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backlight , 2, 1, cmd_backlight,
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"switch backlight on or off",
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"on/off"
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);
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#endif /* CONFIG_STK52XX */
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#endif
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@ -258,11 +258,6 @@ phys_size_t initdram (int board_type)
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int checkboard (void)
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{
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#if defined(CONFIG_AEVFIFO)
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puts ("Board: AEVFIFO\n");
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return 0;
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#endif
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#if defined(CONFIG_TQM5200S)
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# define MODULE_NAME "TQM5200S"
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#else
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@ -271,8 +266,6 @@ int checkboard (void)
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#if defined(CONFIG_STK52XX)
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# define CARRIER_NAME "STK52xx"
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#elif defined(CONFIG_TB5200)
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# define CARRIER_NAME "TB5200"
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#elif defined(CONFIG_CAM5200)
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# define CARRIER_NAME "CAM5200"
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#elif defined(CONFIG_FO300)
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@ -762,7 +755,7 @@ void video_get_info_str (int line_number, char *info)
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if (line_number == 1) {
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strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
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#if defined (CONFIG_CHARON) || defined (CONFIG_FO300) || \
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defined(CONFIG_STK52XX) || defined(CONFIG_TB5200)
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defined(CONFIG_STK52XX)
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} else if (line_number == 2) {
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#if defined (CONFIG_CHARON)
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strcpy (info, " on a CHARON carrier board");
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@ -770,9 +763,6 @@ void video_get_info_str (int line_number, char *info)
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#if defined (CONFIG_STK52XX)
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strcpy (info, " on a STK52xx carrier board");
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#endif
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#if defined (CONFIG_TB5200)
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strcpy (info, " on a TB5200 carrier board");
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#endif
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#if defined (CONFIG_FO300)
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strcpy (info, " on a FO300 carrier board");
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#endif
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@ -1,4 +0,0 @@
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CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B"
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CONFIG_PPC=y
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CONFIG_MPC5xxx=y
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CONFIG_TARGET_TB5200=y
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@ -1,3 +0,0 @@
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CONFIG_PPC=y
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CONFIG_MPC5xxx=y
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CONFIG_TARGET_TB5200=y
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@ -1,3 +0,0 @@
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CONFIG_PPC=y
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CONFIG_MPC5xxx=y
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CONFIG_TARGET_AEV=y
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@ -12,6 +12,8 @@ The list should be sorted in reverse chronological order.
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Board Arch CPU Commit Removed Last known maintainer/contact
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=================================================================================================
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aev powerpc mpc5xxx - -
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TB5200 powerpc mpc5xxx - -
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JSE powerpc ppc4xx - - Stephen Williams <steve@icarus.com>
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BC3450 powerpc mpc5xxx - -
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hawkboard arm arm926ejs cb957cda 2015-02-24 Syed Mohammed Khasim <sm.khasim@gmail.com>:Sughosh Ganu <urwithsughosh@gmail.com>
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@ -1,496 +0,0 @@
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/*
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* (C) Copyright 2003-2006
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2004-2006
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* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
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#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
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#define CONFIG_TB5200 1 /* ... on a TB5200 base board */
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/*
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* Valid values for CONFIG_SYS_TEXT_BASE are:
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* 0xFC000000 boot low (standard configuration with room for
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* max 64 MByte Flash ROM)
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* 0xFFF00000 boot high (for a backup copy of U-Boot)
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* 0x00100000 boot from RAM (for testing only)
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*/
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#ifndef CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_TEXT_BASE 0xFC000000
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#endif
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#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
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#define CONFIG_HIGH_BATS 1 /* High BATs supported */
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/*
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* Serial console configuration
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*/
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#define CONFIG_PSC_CONSOLE 1 /* default console is on PSC1 */
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#define CONFIG_PSC_CONSOLE2 6 /* second console is on PSC6 */
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#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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/*
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* Video console
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*/
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#if 1
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#define CONFIG_VIDEO
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#define CONFIG_VIDEO_SM501
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#define CONFIG_VIDEO_SM501_32BPP
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#define CONFIG_CFB_CONSOLE
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_VGA_AS_SINGLE_DEVICE
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#define CONFIG_CONSOLE_EXTRA_INFO
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#define CONFIG_VIDEO_SW_CURSOR
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#define CONFIG_SPLASH_SCREEN
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV
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#endif
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/* Partitions */
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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#define CONFIG_ISO_PARTITION
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/* USB */
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#define CONFIG_USB_OHCI
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#define CONFIG_USB_STORAGE
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/* POST support */
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#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
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CONFIG_SYS_POST_CPU | \
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CONFIG_SYS_POST_I2C)
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#ifdef CONFIG_POST
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/* preserve space for the post_word at end of on-chip SRAM */
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#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
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#endif
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_ECHO
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_IDE
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#define CONFIG_CMD_JFFS2
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_REGINFO
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#define CONFIG_CMD_SNTP
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#define CONFIG_CMD_BSP
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#define CONFIG_CMD_USB
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#ifdef CONFIG_VIDEO
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#define CONFIG_CMD_BMP
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#endif
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#ifdef CONFIG_POST
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#define CONFIG_CMD_DIAG
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#endif
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#define CONFIG_TIMESTAMP /* display image timestamps */
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#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) /* Boot low */
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# define CONFIG_SYS_LOWBOOT 1
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#endif
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/*
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* Autobooting
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*/
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#define CONFIG_PREBOOT "echo;" \
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"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
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"echo"
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#undef CONFIG_BOOTARGS
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#if defined(CONFIG_TQM5200_B)
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"rootpath=/opt/eldk/ppc_6xx\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"flash_self=run ramargs addip;" \
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"bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"flash_nfs=run nfsargs addip;" \
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"bootm ${kernel_addr}\0" \
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"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
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"bootfile=/tftpboot/tqm5200/uImage\0" \
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"load=tftp 200000 ${u-boot}\0" \
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"u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
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"update=protect off FC000000 FC07FFFF;" \
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"erase FC000000 FC07FFFF;" \
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"cp.b 200000 FC000000 ${filesize};" \
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"protect on FC000000 FC07FFFF\0" \
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""
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#else
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"rootpath=/opt/eldk/ppc_6xx\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"flash_self=run ramargs addip;" \
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"bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"flash_nfs=run nfsargs addip;" \
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"bootm ${kernel_addr}\0" \
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"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
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"bootfile=/tftpboot/tqm5200/uImage\0" \
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"load=tftp 200000 $(u-boot)\0" \
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"u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
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"update=protect off FC000000 FC05FFFF;" \
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"erase FC000000 FC05FFFF;" \
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"cp.b 200000 FC000000 ${filesize};" \
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"protect on FC000000 FC05FFFF\0" \
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""
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#endif /* CONFIG_TQM5200_B */
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#define CONFIG_BOOTCOMMAND "run net_nfs"
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/*
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* IPB Bus clocking configuration.
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*/
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#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
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#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
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/*
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* PCI Bus clocking configuration
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*
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* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
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* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
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* of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
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*/
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#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
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#endif
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/*
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* I2C configuration
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*/
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 */
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/*
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* I2C clock frequency
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*
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* Please notice, that the resulting clock frequency could differ from the
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* configured value. This is because the I2C clock is derived from system
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* clock over a frequency divider with only a few divider values. U-boot
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* calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
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* approximation allways lies below the configured value, never above.
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*/
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#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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/*
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* EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
|
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* also). For other EEPROMs configuration should be verified. On Mini-FAP the
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* EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
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* same configuration could be used.
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*/
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
|
||||
|
||||
/* List of I2C addresses to be verified by POST */
|
||||
#undef CONFIG_SYS_POST_I2C_ADDRS
|
||||
#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_EEPROM_ADDR, \
|
||||
CONFIG_SYS_I2C_RTC_ADDR, \
|
||||
CONFIG_SYS_I2C_SLAVE}
|
||||
|
||||
/*
|
||||
* Flash configuration
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE /* 0xFC000000 */
|
||||
|
||||
/* use CFI flash driver */
|
||||
#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
|
||||
#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
|
||||
|
||||
#if !defined(CONFIG_SYS_LOWBOOT)
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
|
||||
#else /* CONFIG_SYS_LOWBOOT */
|
||||
#if defined(CONFIG_TQM5200_B)
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00080000)
|
||||
#else
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
|
||||
#endif /* CONFIG_TQM5200_B */
|
||||
#endif /* CONFIG_SYS_LOWBOOT */
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
|
||||
(= chip selects) */
|
||||
|
||||
/* Dynamic MTD partition support */
|
||||
#define CONFIG_CMD_MTDPARTS
|
||||
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
|
||||
#define CONFIG_FLASH_CFI_MTD
|
||||
#define MTDIDS_DEFAULT "nor0=TQM5200-0"
|
||||
#if defined(CONFIG_TQM5200_B)
|
||||
#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:768k(firmware)," \
|
||||
"1280k(kernel)," \
|
||||
"2m(initrd)," \
|
||||
"4m(small-fs)," \
|
||||
"16m(big-fs)," \
|
||||
"8m(misc)"
|
||||
#else
|
||||
#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
|
||||
"1408k(kernel)," \
|
||||
"2m(initrd)," \
|
||||
"4m(small-fs)," \
|
||||
"16m(big-fs)," \
|
||||
"8m(misc)"
|
||||
#endif /* CONFIG_TQM5200_B */
|
||||
|
||||
/*
|
||||
* Environment settings
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_SIZE 0x10000
|
||||
#if defined(CONFIG_TQM5200_B)
|
||||
#define CONFIG_ENV_SECT_SIZE 0x40000
|
||||
#else
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000
|
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
|
||||
#endif /* CONFIG_TQM5200_B */
|
||||
|
||||
/*
|
||||
* Memory map
|
||||
*/
|
||||
#define CONFIG_SYS_MBAR 0xF0000000
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
|
||||
|
||||
/* Use ON-Chip SRAM until RAM will be available */
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
|
||||
#ifdef CONFIG_POST
|
||||
/* preserve space for the post_word at end of on-chip SRAM */
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
|
||||
#else
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
|
||||
#endif
|
||||
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
|
||||
# define CONFIG_SYS_RAMBOOT 1
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_TQM5200_B)
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
|
||||
#else
|
||||
#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
|
||||
#endif /* CONFIG_TQM5200_B */
|
||||
#define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* Reserve 1024 kB for malloc() */
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*
|
||||
* Ethernet configuration
|
||||
*/
|
||||
#define CONFIG_MPC5xxx_FEC 1
|
||||
#define CONFIG_MPC5xxx_FEC_MII100
|
||||
/*
|
||||
* Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
|
||||
*/
|
||||
/* #define CONFIG_MPC5xxx_FEC_MII10 */
|
||||
#define CONFIG_PHY_ADDR 0x00
|
||||
|
||||
/*
|
||||
* GPIO configuration
|
||||
*
|
||||
* use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
|
||||
* Bit 0 (mask: 0x80000000): 1
|
||||
* use ALT CAN position: Bits 2-3 (mask: 0x30000000):
|
||||
* 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
|
||||
* 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
|
||||
* Use for REV200 STK52XX boards. Do not use with REV100 modules
|
||||
* (because, there I2C1 is used as I2C bus)
|
||||
* use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
|
||||
* use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
|
||||
* 000 -> All PSC2 pins are GIOPs
|
||||
* 001 -> CAN1/2 on PSC2 pins
|
||||
* Use for REV100 STK52xx boards
|
||||
* use PSC3: Bits 20:23 (mask: 0x00000300):
|
||||
* 0001 -> USB2
|
||||
* 0000 -> GPIO
|
||||
* use PSC6:
|
||||
* on STK52xx:
|
||||
* use as UART. Pins PSC6_0 to PSC6_3 are used.
|
||||
* Bits 9:11 (mask: 0x00700000):
|
||||
* 101 -> PSC6 : Extended POST test is not available
|
||||
* on MINI-FAP and TQM5200_IB:
|
||||
* use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
|
||||
* 000 -> PSC6 could not be used as UART, CODEC or IrDA
|
||||
* GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
|
||||
* tests.
|
||||
*/
|
||||
#define CONFIG_SYS_GPS_PORT_CONFIG 0x81500114
|
||||
|
||||
/*
|
||||
* RTC configuration
|
||||
*/
|
||||
#define CONFIG_RTC_M41T11 1
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
|
||||
#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* because Linux uses the same base
|
||||
year */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/* Enable an alternate, more extensive memory test */
|
||||
#define CONFIG_SYS_ALT_MEMTEST
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
|
||||
|
||||
/*
|
||||
* Enable loopw command.
|
||||
*/
|
||||
#define CONFIG_LOOPW
|
||||
|
||||
/*
|
||||
* Various low-level settings
|
||||
*/
|
||||
#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
|
||||
#define CONFIG_SYS_HID0_FINAL HID0_ICE
|
||||
|
||||
#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
|
||||
#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
|
||||
#define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
|
||||
#else
|
||||
#define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
|
||||
#endif
|
||||
#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
|
||||
|
||||
#define CONFIG_LAST_STAGE_INIT
|
||||
|
||||
/*
|
||||
* SRAM - Do not map below 2 GB in address space, because this area is used
|
||||
* for SDRAM autosizing.
|
||||
*/
|
||||
#define CONFIG_SYS_CS2_START 0xE5000000
|
||||
#define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */
|
||||
#define CONFIG_SYS_CS2_CFG 0x0004D930
|
||||
|
||||
/*
|
||||
* Grafic controller - Do not map below 2 GB in address space, because this
|
||||
* area is used for SDRAM autosizing.
|
||||
*/
|
||||
#define SM501_FB_BASE 0xE0000000
|
||||
#define CONFIG_SYS_CS1_START (SM501_FB_BASE)
|
||||
#define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */
|
||||
#define CONFIG_SYS_CS1_CFG 0x8F48FF70
|
||||
#define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000
|
||||
|
||||
#define CONFIG_SYS_CS_BURST 0x00000000
|
||||
#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
|
||||
|
||||
#define CONFIG_SYS_RESET_ADDRESS 0xff000000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* USB stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_USB_CLOCK 0x0001BBBB
|
||||
#define CONFIG_USB_CONFIG 0x00001000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff Supports IDE harddisk
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
|
||||
|
||||
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
|
||||
#undef CONFIG_IDE_LED /* LED for ide not supported */
|
||||
|
||||
#define CONFIG_IDE_RESET /* reset for ide supported */
|
||||
#define CONFIG_IDE_PREINIT
|
||||
|
||||
#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
|
||||
#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
|
||||
|
||||
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
|
||||
|
||||
#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
|
||||
|
||||
/* Offset for data I/O */
|
||||
#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
|
||||
|
||||
/* Offset for normal register accesses */
|
||||
#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
|
||||
|
||||
/* Offset for alternate registers */
|
||||
#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
|
||||
|
||||
/* Interval between registers */
|
||||
#define CONFIG_SYS_ATA_STRIDE 4
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -1,390 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2003-2006
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* (C) Copyright 2004-2005
|
||||
* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
|
||||
#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
|
||||
#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
|
||||
#define CONFIG_STK52XX 1 /* ... on a STK52XX base board */
|
||||
#define CONFIG_STK52XX_REV100 1 /* define for revision 100 baseboards */
|
||||
#define CONFIG_AEVFIFO 1
|
||||
#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
|
||||
|
||||
/*
|
||||
* Valid values for CONFIG_SYS_TEXT_BASE are:
|
||||
* 0xFC000000 boot low (standard configuration with room for
|
||||
* max 64 MByte Flash ROM)
|
||||
* 0xFFF00000 boot high (for a backup copy of U-Boot)
|
||||
* 0x00100000 boot from RAM (for testing only)
|
||||
*/
|
||||
#ifndef CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_TEXT_BASE 0xFC000000
|
||||
#endif
|
||||
|
||||
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
|
||||
|
||||
/*
|
||||
* Serial console configuration
|
||||
*/
|
||||
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
|
||||
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
|
||||
|
||||
/*
|
||||
* PCI Mapping:
|
||||
* 0x40000000 - 0x4fffffff - PCI Memory
|
||||
* 0x50000000 - 0x50ffffff - PCI IO Space
|
||||
*/
|
||||
#ifdef CONFIG_AEVFIFO
|
||||
#define CONFIG_PCI 1
|
||||
#define CONFIG_PCI_PNP 1
|
||||
/* #define CONFIG_PCI_SCAN_SHOW 1 */
|
||||
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
|
||||
|
||||
#define CONFIG_PCI_MEM_BUS 0x40000000
|
||||
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
|
||||
#define CONFIG_PCI_MEM_SIZE 0x10000000
|
||||
|
||||
#define CONFIG_PCI_IO_BUS 0x50000000
|
||||
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
|
||||
#define CONFIG_PCI_IO_SIZE 0x01000000
|
||||
|
||||
#define CONFIG_EEPRO100 1
|
||||
#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
|
||||
#define CONFIG_NS8382X 1
|
||||
#endif /* CONFIG_AEVFIFO */
|
||||
|
||||
/* Partitions */
|
||||
#define CONFIG_MAC_PARTITION
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_ISO_PARTITION
|
||||
|
||||
/* POST support */
|
||||
#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
|
||||
CONFIG_SYS_POST_CPU | \
|
||||
CONFIG_SYS_POST_I2C)
|
||||
|
||||
#ifdef CONFIG_POST
|
||||
/* preserve space for the post_word at end of on-chip SRAM */
|
||||
#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_ASKENV
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_ECHO
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_NFS
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_REGINFO
|
||||
#define CONFIG_CMD_SNTP
|
||||
|
||||
#ifdef CONFIG_POST
|
||||
#define CONFIG_CMD_DIAG
|
||||
#endif
|
||||
|
||||
|
||||
#define CONFIG_TIMESTAMP /* display image timestamps */
|
||||
|
||||
#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) /* Boot low */
|
||||
# define CONFIG_SYS_LOWBOOT 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Autobooting
|
||||
*/
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
|
||||
#define CONFIG_PREBOOT "echo;" \
|
||||
"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
|
||||
"echo"
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"rootpath=/opt/eldk/ppc_6xx\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath} " \
|
||||
"console=ttyS0,${baudrate}\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"flash_self=run ramargs addip;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
||||
"flash_nfs=run nfsargs addip;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
|
||||
"bootfile=/tftpboot/tqm5200/uImage\0" \
|
||||
"load=tftp 200000 ${u-boot}\0" \
|
||||
"u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
|
||||
"update=protect off FC000000 FC05FFFF;" \
|
||||
"erase FC000000 FC05FFFF;" \
|
||||
"cp.b 200000 FC000000 ${filesize};" \
|
||||
"protect on FC000000 FC05FFFF\0" \
|
||||
""
|
||||
|
||||
#define CONFIG_BOOTCOMMAND "run net_nfs"
|
||||
|
||||
/*
|
||||
* IPB Bus clocking configuration.
|
||||
*/
|
||||
#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
|
||||
|
||||
#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
|
||||
/*
|
||||
* PCI Bus clocking configuration
|
||||
*
|
||||
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
|
||||
* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
|
||||
* of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
|
||||
*/
|
||||
#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* I2C configuration
|
||||
*/
|
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
|
||||
#ifdef CONFIG_TQM5200_REV100
|
||||
#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */
|
||||
#else
|
||||
#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 for all other revs */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* I2C clock frequency
|
||||
*
|
||||
* Please notice, that the resulting clock frequency could differ from the
|
||||
* configured value. This is because the I2C clock is derived from system
|
||||
* clock over a frequency divider with only a few divider values. U-boot
|
||||
* calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
|
||||
* approximation allways lies below the configured value, never above.
|
||||
*/
|
||||
#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
|
||||
/*
|
||||
* EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
|
||||
* also). For other EEPROMs configuration should be verified. On Mini-FAP the
|
||||
* EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
|
||||
* same configuration could be used.
|
||||
*/
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
|
||||
|
||||
/*
|
||||
* Flash configuration
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE /* 0xFC000000 */
|
||||
|
||||
/* use CFI flash driver if no module variant is spezified */
|
||||
#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
|
||||
#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
|
||||
#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
|
||||
|
||||
#if !defined(CONFIG_SYS_LOWBOOT)
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
|
||||
#else /* CONFIG_SYS_LOWBOOT */
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
|
||||
#endif /* CONFIG_SYS_LOWBOOT */
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
|
||||
(= chip selects) */
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
|
||||
|
||||
|
||||
/*
|
||||
* Environment settings
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_SIZE 0x10000
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000
|
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
|
||||
|
||||
/*
|
||||
* Memory map
|
||||
*/
|
||||
#define CONFIG_SYS_MBAR 0xF0000000
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
|
||||
|
||||
/* Use ON-Chip SRAM until RAM will be available */
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
|
||||
#ifdef CONFIG_POST
|
||||
/* preserve space for the post_word at end of on-chip SRAM */
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
|
||||
#else
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
|
||||
#endif
|
||||
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
|
||||
# define CONFIG_SYS_RAMBOOT 1
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
|
||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*
|
||||
* Ethernet configuration
|
||||
*/
|
||||
#define CONFIG_MPC5xxx_FEC 1
|
||||
#define CONFIG_MPC5xxx_FEC_MII100
|
||||
/*
|
||||
* Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
|
||||
*/
|
||||
/* #define CONFIG_MPC5xxx_FEC_MII10 */
|
||||
#define CONFIG_PHY_ADDR 0x00
|
||||
|
||||
/*
|
||||
* GPIO configuration
|
||||
*
|
||||
* use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
|
||||
* Bit 0 (mask: 0x80000000): 1
|
||||
* use ALT CAN position: Bits 2-3 (mask: 0x30000000):
|
||||
* 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
|
||||
* 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
|
||||
* Use for REV200 STK52XX boards. Do not use with REV100 modules
|
||||
* (because, there I2C1 is used as I2C bus)
|
||||
* use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
|
||||
* use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
|
||||
* 000 -> All PSC2 pins are GIOPs
|
||||
* 001 -> CAN1/2 on PSC2 pins
|
||||
* Use for REV100 STK52xx boards
|
||||
* use PSC6:
|
||||
* on STK52xx:
|
||||
* use as UART. Pins PSC6_0 to PSC6_3 are used.
|
||||
* Bits 9:11 (mask: 0x00700000):
|
||||
* 101 -> PSC6 : Extended POST test is not available
|
||||
* on MINI-FAP and TQM5200_IB:
|
||||
* use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
|
||||
* 000 -> PSC6 could not be used as UART, CODEC or IrDA
|
||||
* GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
|
||||
* tests.
|
||||
*/
|
||||
#define CONFIG_SYS_GPS_PORT_CONFIG 0x81500014
|
||||
|
||||
/*
|
||||
* RTC configuration
|
||||
*/
|
||||
#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
/* Enable an alternate, more extensive memory test */
|
||||
#define CONFIG_SYS_ALT_MEMTEST
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
|
||||
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Enable loopw command.
|
||||
*/
|
||||
#define CONFIG_LOOPW
|
||||
|
||||
/*
|
||||
* Various low-level settings
|
||||
*/
|
||||
#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
|
||||
#define CONFIG_SYS_HID0_FINAL HID0_ICE
|
||||
|
||||
#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
|
||||
#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
|
||||
#define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
|
||||
#else
|
||||
#define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
|
||||
#endif
|
||||
#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
|
||||
|
||||
#define CONFIG_LAST_STAGE_INIT
|
||||
|
||||
/*
|
||||
* SRAM - Do not map below 2 GB in address space, because this area is used
|
||||
* for SDRAM autosizing.
|
||||
*/
|
||||
#define CONFIG_SYS_CS2_START 0xE5000000
|
||||
#define CONFIG_SYS_CS2_SIZE 0x80000 /* 512 kByte */
|
||||
#define CONFIG_SYS_CS2_CFG 0x0004D930
|
||||
|
||||
/*
|
||||
* Grafic controller - Do not map below 2 GB in address space, because this
|
||||
* area is used for SDRAM autosizing.
|
||||
*/
|
||||
#define SM501_FB_BASE 0xE0000000
|
||||
#define CONFIG_SYS_CS1_START (SM501_FB_BASE)
|
||||
#define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */
|
||||
#define CONFIG_SYS_CS1_CFG 0x8F48FF70
|
||||
#define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000
|
||||
|
||||
#define CONFIG_SYS_CS_BURST 0x00000000
|
||||
#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
|
||||
|
||||
#define CONFIG_SYS_RESET_ADDRESS 0xff000000
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue
Block a user