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https://github.com/brain-hackers/u-boot-brain
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rockchip: add core px30 headers
Add headers needed by the upcoming px30 support, including two new dt-binding headers taken from the Linux kernel. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Heiko Stuebner
Kever Yang
parent
22b7b86005
commit
46281a76be
144
arch/arm/include/asm/arch-rockchip/grf_px30.h
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144
arch/arm/include/asm/arch-rockchip/grf_px30.h
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd.
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*/
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#ifndef _ASM_ARCH_GRF_px30_H
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#define _ASM_ARCH_GRF_px30_H
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#include <common.h>
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struct px30_grf {
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unsigned int gpio1al_iomux;
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unsigned int gpio1ah_iomux;
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unsigned int gpio1bl_iomux;
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unsigned int gpio1bh_iomux;
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unsigned int gpio1cl_iomux;
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unsigned int gpio1ch_iomux;
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unsigned int gpio1dl_iomux;
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unsigned int gpio1dh_iomux;
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unsigned int gpio2al_iomux;
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unsigned int gpio2ah_iomux;
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unsigned int gpio2bl_iomux;
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unsigned int gpio2bh_iomux;
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unsigned int gpio2cl_iomux;
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unsigned int gpio2ch_iomux;
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unsigned int gpio2dl_iomux;
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unsigned int gpio2dh_iomux;
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unsigned int gpio3al_iomux;
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unsigned int gpio3ah_iomux;
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unsigned int gpio3bl_iomux;
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unsigned int gpio3bh_iomux;
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unsigned int gpio3cl_iomux;
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unsigned int gpio3ch_iomux;
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unsigned int gpio3dl_iomux;
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unsigned int gpio3dh_iomux;
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unsigned int gpio1a_p;
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unsigned int gpio1b_p;
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unsigned int gpio1c_p;
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unsigned int gpio1d_p;
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unsigned int gpio2a_p;
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unsigned int gpio2b_p;
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unsigned int gpio2c_p;
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unsigned int gpio2d_p;
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unsigned int gpio3a_p;
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unsigned int gpio3b_p;
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unsigned int gpio3c_p;
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unsigned int gpio3d_p;
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unsigned int gpio1a_sr;
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unsigned int gpio1b_sr;
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unsigned int gpio1c_sr;
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unsigned int gpio1d_sr;
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unsigned int gpio2a_sr;
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unsigned int gpio2b_sr;
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unsigned int gpio2c_sr;
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unsigned int gpio2d_sr;
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unsigned int gpio3a_sr;
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unsigned int gpio3b_sr;
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unsigned int gpio3c_sr;
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unsigned int gpio3d_sr;
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unsigned int gpio1a_smt;
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unsigned int gpio1b_smt;
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unsigned int gpio1c_smt;
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unsigned int gpio1d_smt;
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unsigned int gpio2a_smt;
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unsigned int gpio2b_smt;
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unsigned int gpio2c_smt;
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unsigned int gpio2d_smt;
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unsigned int gpio3a_smt;
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unsigned int gpio3b_smt;
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unsigned int gpio3c_smt;
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unsigned int gpio3d_smt;
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unsigned int gpio1a_e;
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unsigned int gpio1b_e;
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unsigned int gpio1c_e;
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unsigned int gpio1d_e;
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unsigned int gpio2a_e;
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unsigned int gpio2b_e;
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unsigned int gpio2c_e;
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unsigned int gpio2d_e;
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unsigned int gpio3a_e;
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unsigned int gpio3b_e;
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unsigned int gpio3c_e;
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unsigned int gpio3d_e;
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unsigned int reserved0[(0x180 - 0x11C) / 4 - 1];
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unsigned int io_vsel;
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unsigned int iofunc_con0;
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unsigned int reserved1[(0x400 - 0x184) / 4 - 1];
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unsigned int soc_con[6];
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unsigned int reserved2[(0x480 - 0x414) / 4 - 1];
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unsigned int soc_status0;
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unsigned int reserved3[(0x500 - 0x480) / 4 - 1];
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unsigned int cpu_con[3];
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unsigned int reserved4[5];
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unsigned int cpu_status[2];
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unsigned int reserved5[2];
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unsigned int soc_noc_con[2];
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unsigned int reserved6[6];
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unsigned int ddr_bankhash[4];
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unsigned int reserved7[(0x700 - 0x55c) / 4 - 1];
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unsigned int host0_con[2];
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unsigned int reserved8[(0x880 - 0x704) / 4 - 1];
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unsigned int otg_con3;
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unsigned int reserved9[3];
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unsigned int host0_status4;
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unsigned int reserved10[(0x904 - 0x890) / 4 - 1];
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unsigned int mac_con1;
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};
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check_member(px30_grf, mac_con1, 0x904);
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struct px30_pmugrf {
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unsigned int gpio0a_e;
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unsigned int gpio0b_e;
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unsigned int gpio0c_e;
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unsigned int gpio0d_e;
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unsigned int gpio0a_p;
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unsigned int gpio0b_p;
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unsigned int gpio0c_p;
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unsigned int gpio0d_p;
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unsigned int gpio0al_iomux;
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unsigned int gpio0bl_iomux;
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unsigned int gpio0cl_iomux;
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unsigned int gpio0dl_iomux;
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unsigned int gpio0l_sr;
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unsigned int gpio0h_sr;
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unsigned int gpio0l_smt;
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unsigned int gpio0h_smt;
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unsigned int reserved1[(0x100 - 0x3c) / 4 - 1];
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unsigned int soc_con[4];
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unsigned int reserved2[(0x180 - 0x10c) / 4 - 1];
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unsigned int pvtm_con[2];
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unsigned int reserved3[2];
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unsigned int pvtm_status[2];
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unsigned int reserved4[(0x200 - 0x194) / 4 - 1];
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unsigned int os_reg[12];
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unsigned int reset_function_status;
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};
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check_member(px30_pmugrf, reset_function_status, 0x230);
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#endif
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62
include/configs/px30_common.h
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62
include/configs/px30_common.h
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd
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*/
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#ifndef __CONFIG_PX30_COMMON_H
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#define __CONFIG_PX30_COMMON_H
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#include "rockchip-common.h"
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#define CONFIG_SYS_CBSIZE 1024
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_SYS_NS16550_MEM32
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#define CONFIG_ROCKCHIP_STIMER_BASE 0xff220020
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#define COUNTER_FREQUENCY 24000000
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/* FIXME: ff020000 is pmu_mem (10k), while ff0e0000 is regular int_mem */
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#define CONFIG_IRAM_BASE 0xff020000
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#define CONFIG_SYS_INIT_SP_ADDR 0x00400000
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#define CONFIG_SYS_LOAD_ADDR 0x00800800
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#define CONFIG_SPL_STACK 0x00400000
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#define CONFIG_SPL_MAX_SIZE 0x20000
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#define CONFIG_SPL_BSS_START_ADDR 0x4000000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x4000
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
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#define GICD_BASE 0xff131000
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#define GICC_BASE 0xff132000
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
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/* MMC/SD IP block */
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//#define CONFIG_BOUNCE_BUFFER
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#define CONFIG_SYS_SDRAM_BASE 0
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#define SDRAM_MAX_SIZE 0xff000000
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#define SDRAM_BANK_SIZE (2UL << 30)
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#ifndef CONFIG_SPL_BUILD
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#define ENV_MEM_LAYOUT_SETTINGS \
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"scriptaddr=0x00500000\0" \
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"pxefile_addr_r=0x00600000\0" \
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"fdt_addr_r=0x08300000\0" \
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"kernel_addr_r=0x00280000\0" \
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"kernel_addr_c=0x03e80000\0" \
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"ramdisk_addr_r=0x0a200000\0"
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#include <config_distro_bootcmd.h>
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#define CONFIG_EXTRA_ENV_SETTINGS \
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ENV_MEM_LAYOUT_SETTINGS \
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"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
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"partitions=" PARTS_DEFAULT \
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ROCKCHIP_DEVICE_SETTINGS \
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BOOTENV
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#endif
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#endif
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27
include/dt-bindings/power/px30-power.h
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include/dt-bindings/power/px30-power.h
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __DT_BINDINGS_POWER_PX30_POWER_H__
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#define __DT_BINDINGS_POWER_PX30_POWER_H__
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/* VD_CORE */
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#define PX30_PD_A35_0 0
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#define PX30_PD_A35_1 1
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#define PX30_PD_A35_2 2
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#define PX30_PD_A35_3 3
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#define PX30_PD_SCU 4
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/* VD_LOGIC */
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#define PX30_PD_USB 5
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#define PX30_PD_DDR 6
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#define PX30_PD_SDCARD 7
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#define PX30_PD_CRYPTO 8
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#define PX30_PD_GMAC 9
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#define PX30_PD_MMC_NAND 10
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#define PX30_PD_VPU 11
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#define PX30_PD_VO 12
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#define PX30_PD_VI 13
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#define PX30_PD_GPU 14
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/* VD_PMU */
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#define PX30_PD_PMU 15
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#endif
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16
include/dt-bindings/soc/rockchip,boot-mode.h
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include/dt-bindings/soc/rockchip,boot-mode.h
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ROCKCHIP_BOOT_MODE_H
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#define __ROCKCHIP_BOOT_MODE_H
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/*high 24 bits is tag, low 8 bits is type*/
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#define REBOOT_FLAG 0x5242C300
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/* normal boot */
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#define BOOT_NORMAL (REBOOT_FLAG + 0)
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/* enter bootloader rockusb mode */
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#define BOOT_BL_DOWNLOAD (REBOOT_FLAG + 1)
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/* enter recovery */
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#define BOOT_RECOVERY (REBOOT_FLAG + 3)
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/* enter fastboot mode */
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#define BOOT_FASTBOOT (REBOOT_FLAG + 9)
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#endif
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