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clk: uniphier: add ethernet clock control support
Add clock control for ethernet controller on each SoC. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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@ -21,7 +21,10 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
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defined(CONFIG_ARCH_UNIPHIER_PRO4) || defined(CONFIG_ARCH_UNIPHIER_PRO5) ||\
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defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B)
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UNIPHIER_LD4_SYS_CLK_NAND(2),
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UNIPHIER_CLK_GATE_SIMPLE(6, 0x2104, 12), /* ether (Pro4, PXs2) */
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UNIPHIER_CLK_GATE_SIMPLE(7, 0x2104, 5), /* ether-gb (Pro4) */
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UNIPHIER_CLK_GATE_SIMPLE(8, 0x2104, 10), /* stdmac */
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UNIPHIER_CLK_GATE_SIMPLE(10, 0x2260, 0), /* ether-phy (Pro4) */
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UNIPHIER_CLK_GATE_SIMPLE(12, 0x2104, 6), /* gio (Pro4, Pro5) */
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UNIPHIER_CLK_GATE_SIMPLE(14, 0x2104, 16), /* usb30 (Pro4, Pro5, PXs2) */
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UNIPHIER_CLK_GATE_SIMPLE(15, 0x2104, 17), /* usb31 (Pro4, Pro5, PXs2) */
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@ -34,6 +37,7 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
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const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
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#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20)
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UNIPHIER_LD11_SYS_CLK_NAND(2),
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UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 6), /* ether */
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UNIPHIER_CLK_GATE_SIMPLE(8, 0x210c, 8), /* stdmac */
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UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 14), /* usb30 (LD20) */
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UNIPHIER_CLK_GATE_SIMPLE(16, 0x210c, 12), /* usb30-phy0 (LD20) */
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@ -45,6 +49,8 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
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const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
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#if defined(CONFIG_ARCH_UNIPHIER_PXS3)
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UNIPHIER_LD11_SYS_CLK_NAND(2),
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UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 9), /* ether0 */
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UNIPHIER_CLK_GATE_SIMPLE(7, 0x210c, 10), /* ether1 */
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UNIPHIER_CLK_GATE_SIMPLE(12, 0x210c, 4), /* usb30 (gio0) */
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UNIPHIER_CLK_GATE_SIMPLE(13, 0x210c, 5), /* usb31-0 (gio1) */
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UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 6), /* usb31-1 (gio1-1) */
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