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clk: renesas: Fix SDH clock divider decoding on Gen2

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The gen2_clk_get_sdh_div() function is supposed to look up the
$val value read out of the SDCKCR register in the supplied table
and return the matching divider value. The current implementation
was matching the value from SDCKCR on the divider value in the
table, which is wrong. Fix this and rework the function a bit
to make it more readable.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Marek Vasut 2019-03-18 05:11:42 +01:00 committed by Marek Vasut
parent c49d0ac38a
commit 45b01b462f
1 changed files with 9 additions and 5 deletions
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14
drivers/clk/renesas/clk-rcar-gen2.c
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@ -44,13 +44,17 @@ static const struct clk_div_table cpg_sd01_div_table[] = {
{ 0, 0 },
};
static u8 gen2_clk_get_sdh_div(const struct clk_div_table *table, u8 div)
static u8 gen2_clk_get_sdh_div(const struct clk_div_table *table, u8 val)
{
while ((*table++).val) {
if ((*table).div == div)
return div;
for (;;) {
if (!(*table).div)
return 0xff;
if ((*table).val == val)
return (*table).div;
table++;
}
return 0xff;
}
static int gen2_clk_enable(struct clk *clk)