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https://github.com/brain-hackers/u-boot-brain
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mpc83xx: Size optimization of start.S
Currently there are in excess of 100 bytes located at the beginning of the image built by start.S that are not being utilized. This patch moves a few functions into this part of the image. This will create a greater number of *available* bytes that can be used by board specific code in NAND builds and will decrease the size of the assembled code in other builds. Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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@ -109,6 +109,45 @@ version_string:
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.ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
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.ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
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.ascii " ", CONFIG_IDENT_STRING, "\0"
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.ascii " ", CONFIG_IDENT_STRING, "\0"
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.align 2
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.globl enable_addr_trans
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enable_addr_trans:
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/* enable address translation */
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mfmsr r5
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ori r5, r5, (MSR_IR | MSR_DR)
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mtmsr r5
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isync
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blr
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.globl disable_addr_trans
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disable_addr_trans:
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/* disable address translation */
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mflr r4
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mfmsr r3
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andi. r0, r3, (MSR_IR | MSR_DR)
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beqlr
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andc r3, r3, r0
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mtspr SRR0, r4
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mtspr SRR1, r3
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rfi
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.globl get_pvr
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get_pvr:
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mfspr r3, PVR
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blr
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.globl ppcDWstore
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ppcDWstore:
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lfd 1, 0(r4)
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stfd 1, 0(r3)
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blr
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.globl ppcDWload
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ppcDWload:
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lfd 1, 0(r3)
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stfd 1, 0(r4)
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blr
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#ifndef CONFIG_DEFAULT_IMMR
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#ifndef CONFIG_DEFAULT_IMMR
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#error CONFIG_DEFAULT_IMMR must be defined
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#error CONFIG_DEFAULT_IMMR must be defined
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@ -698,27 +737,6 @@ setup_bats:
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blr
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blr
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.globl enable_addr_trans
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enable_addr_trans:
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/* enable address translation */
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mfmsr r5
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ori r5, r5, (MSR_IR | MSR_DR)
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mtmsr r5
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isync
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blr
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.globl disable_addr_trans
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disable_addr_trans:
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/* disable address translation */
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mflr r4
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mfmsr r3
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andi. r0, r3, (MSR_IR | MSR_DR)
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beqlr
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andc r3, r3, r0
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mtspr SRR0, r4
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mtspr SRR1, r3
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rfi
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/* Cache functions.
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/* Cache functions.
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*
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*
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* Note: requires that all cache bits in
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* Note: requires that all cache bits in
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@ -796,23 +814,6 @@ flush_dcache:
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b 1b
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b 1b
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2: blr
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2: blr
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.globl get_pvr
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get_pvr:
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mfspr r3, PVR
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blr
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.globl ppcDWstore
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ppcDWstore:
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lfd 1, 0(r4)
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stfd 1, 0(r3)
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blr
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.globl ppcDWload
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ppcDWload:
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lfd 1, 0(r3)
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stfd 1, 0(r4)
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blr
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/*-------------------------------------------------------------------*/
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/*-------------------------------------------------------------------*/
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/*
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/*
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