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arm: rmobile: r8a779x: Fix L2 cache init and latency setting
L2CTLR only need to update for cluster 0. This changes L2CTLR to initialize only when cluster is 0. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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@ -2,7 +2,7 @@
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* arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
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* arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
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* This file is lager low level initialize.
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* This file is lager low level initialize.
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*
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*
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* Copyright (C) 2013 Renesas Electronics Corporation
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* Copyright (C) 2013, 2014 Renesas Electronics Corporation
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*
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*
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* SPDX-License-Identifier: GPL-2.0
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* SPDX-License-Identifier: GPL-2.0
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*/
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*/
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@ -36,16 +36,32 @@ do_cpu_waiting:
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.align 4
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.align 4
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do_lowlevel_init:
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do_lowlevel_init:
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/* surpress wfe if ca15 */
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/* surpress wfe if ca15 */
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tst r4, #4
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tst r4, #4
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mrceq p15, 0, r0, c1, c0, 1 /* actlr */
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mrceq p15, 0, r0, c1, c0, 1 /* actlr */
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orreq r0, r0, #(1<<7)
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orreq r0, r0, #(1<<7)
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mcreq p15, 0, r0, c1, c0, 1
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mcreq p15, 0, r0, c1, c0, 1
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/* and set l2 latency */
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/* and set l2 latency */
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mrceq p15, 1, r0, c9, c0, 2 /* l2ctlr */
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mrceq p15, 1, r0, c9, c0, 2 /* l2ctlr */
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orreq r0, r0, #0x00000800
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orreq r0, r0, #0x00000800
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orreq r0, r0, #0x00000003
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orreq r0, r0, #0x00000003
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mcreq p15, 1, r0, c9, c0, 2
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mcreq p15, 1, r0, c9, c0, 2
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mrc p15, 0, r0, c0, c0, 5 /* r0 = MPIDR */
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and r0, r0, #0xf00
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lsr r0, r0, #8
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tst r0, #1 /* only need for cluster 0 */
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bne _exit_init_l2_a15
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mrc p15, 1, r0, c9, c0, 2 /* r0 = L2CTLR */
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and r1, r0, #7
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cmp r1, #3 /* has already been set up */
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bicne r0, r0, #0xe7
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orrne r0, r0, #0x83 /* L2CTLR[7:6] + L2CTLR[2:0] */
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orrne r0, r0, #0x20 /* L2CTLR[5] */
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mcrne p15, 1, r0, c9, c0, 2
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_exit_init_l2_a15:
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ldr r3, =(CONFIG_SYS_INIT_SP_ADDR)
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ldr r3, =(CONFIG_SYS_INIT_SP_ADDR)
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sub sp, r3, #4
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sub sp, r3, #4
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str lr, [sp]
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str lr, [sp]
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