Patches by Lars Munch, 12 Jul 2004:
- move at45.c to board/at91rm9200dk/ since this is at91rm9200dk board specific - split out the LXT971A PHY from ns_9750_eth.h - split the dm9161 phy part out of at91rm9200_ether.c
This commit is contained in:
wdenk
parent
6705d81e90
commit
429168ea88
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@ -2,6 +2,12 @@
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Changes since U-Boot 1.1.1:
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======================================================================
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* Patches by Lars Munch, 12 Jul 2004:
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- move at45.c to board/at91rm9200dk/ since this is at91rm9200dk
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board specific
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- split out the LXT971A PHY from ns_9750_eth.h
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- split the dm9161 phy part out of at91rm9200_ether.c
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* Patch by Andreas Engel, 12 Jul 2004:
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Replaced hardcoded PL011 clock frequency with config variable.
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Fixed wrong CONFIG_CMD_DFL doc.
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@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
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LIB = lib$(BOARD).a
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OBJS := at91rm9200dk.o flash.o
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OBJS := at91rm9200dk.o at45.o dm9161.o flash.o
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SOBJS :=
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$(LIB): $(OBJS) $(SOBJS)
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@ -0,0 +1,243 @@
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/*
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* (C) Copyright 2003
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* Author : Hamid Ikdoumi (Atmel)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <at91rm9200_net.h>
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#include <net.h>
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#include <dm9161.h>
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#ifdef CONFIG_DRIVER_ETHER
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#if (CONFIG_COMMANDS & CFG_CMD_NET)
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/*
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* Name:
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* dm9161_IsPhyConnected
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* Description:
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* Reads the 2 PHY ID registers
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* Arguments:
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* p_mac - pointer to AT91S_EMAC struct
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* Return value:
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* TRUE - if id read successfully
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* FALSE- if error
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*/
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static unsigned int dm9161_IsPhyConnected (AT91PS_EMAC p_mac)
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{
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unsigned short Id1, Id2;
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at91rm9200_EmacEnableMDIO (p_mac);
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at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID1, &Id1);
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at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID2, &Id2);
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at91rm9200_EmacDisableMDIO (p_mac);
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if ((Id1 == (DM9161_PHYID1_OUI >> 6)) &&
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((Id2 >> 10) == (DM9161_PHYID1_OUI & DM9161_LSB_MASK)))
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return TRUE;
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return FALSE;
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}
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/*
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* Name:
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* dm9161_GetLinkSpeed
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* Description:
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* Link parallel detection status of MAC is checked and set in the
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* MAC configuration registers
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* Arguments:
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* p_mac - pointer to MAC
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* Return value:
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* TRUE - if link status set succesfully
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* FALSE - if link status not set
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*/
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static UCHAR dm9161_GetLinkSpeed (AT91PS_EMAC p_mac)
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{
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unsigned short stat1, stat2;
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if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &stat1))
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return FALSE;
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if (!(stat1 & DM9161_LINK_STATUS)) /* link status up? */
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return FALSE;
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if (!at91rm9200_EmacReadPhy (p_mac, DM9161_DSCSR, &stat2))
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return FALSE;
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if ((stat1 & DM9161_100BASE_TX_FD) && (stat2 & DM9161_100FDX)) {
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/*set Emac for 100BaseTX and Full Duplex */
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p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
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return TRUE;
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}
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if ((stat1 & DM9161_10BASE_T_FD) && (stat2 & DM9161_10FDX)) {
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/*set MII for 10BaseT and Full Duplex */
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p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
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~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
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| AT91C_EMAC_FD;
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return TRUE;
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}
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if ((stat1 & DM9161_100BASE_T4_HD) && (stat2 & DM9161_100HDX)) {
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/*set MII for 100BaseTX and Half Duplex */
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p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
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~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
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| AT91C_EMAC_SPD;
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return TRUE;
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}
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if ((stat1 & DM9161_10BASE_T_HD) && (stat2 & DM9161_10HDX)) {
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/*set MII for 10BaseT and Half Duplex */
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p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
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return TRUE;
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}
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return FALSE;
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}
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/*
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* Name:
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* dm9161_InitPhy
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* Description:
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* MAC starts checking its link by using parallel detection and
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* Autonegotiation and the same is set in the MAC configuration registers
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* Arguments:
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* p_mac - pointer to struct AT91S_EMAC
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* Return value:
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* TRUE - if link status set succesfully
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* FALSE - if link status not set
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*/
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static UCHAR dm9161_InitPhy (AT91PS_EMAC p_mac)
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{
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UCHAR ret = TRUE;
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unsigned short IntValue;
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at91rm9200_EmacEnableMDIO (p_mac);
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if (!dm9161_GetLinkSpeed (p_mac)) {
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/* Try another time */
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ret = dm9161_GetLinkSpeed (p_mac);
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}
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/* Disable PHY Interrupts */
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at91rm9200_EmacReadPhy (p_mac, DM9161_MDINTR, &IntValue);
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/* clear FDX, SPD, Link, INTR masks */
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IntValue &= ~(DM9161_FDX_MASK | DM9161_SPD_MASK |
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DM9161_LINK_MASK | DM9161_INTR_MASK);
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at91rm9200_EmacWritePhy (p_mac, DM9161_MDINTR, &IntValue);
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at91rm9200_EmacDisableMDIO (p_mac);
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return (ret);
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}
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/*
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* Name:
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* dm9161_AutoNegotiate
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* Description:
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* MAC Autonegotiates with the partner status of same is set in the
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* MAC configuration registers
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* Arguments:
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* dev - pointer to struct net_device
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* Return value:
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* TRUE - if link status set successfully
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* FALSE - if link status not set
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*/
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static UCHAR dm9161_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
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{
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unsigned short value;
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unsigned short PhyAnar;
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unsigned short PhyAnalpar;
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/* Set dm9161 control register */
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if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
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return FALSE;
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value &= ~DM9161_AUTONEG; /* remove autonegotiation enable */
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value |= DM9161_ISOLATE; /* Electrically isolate PHY */
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if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
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return FALSE;
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/* Set the Auto_negotiation Advertisement Register */
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/* MII advertising for Next page, 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */
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PhyAnar = DM9161_NP | DM9161_TX_FDX | DM9161_TX_HDX |
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DM9161_10_FDX | DM9161_10_HDX | DM9161_AN_IEEE_802_3;
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if (!at91rm9200_EmacWritePhy (p_mac, DM9161_ANAR, &PhyAnar))
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return FALSE;
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/* Read the Control Register */
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if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
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return FALSE;
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value |= DM9161_SPEED_SELECT | DM9161_AUTONEG | DM9161_DUPLEX_MODE;
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if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
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return FALSE;
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/* Restart Auto_negotiation */
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value |= DM9161_RESTART_AUTONEG;
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if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
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return FALSE;
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/*check AutoNegotiate complete */
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udelay (10000);
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at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &value);
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if (!(value & DM9161_AUTONEG_COMP))
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return FALSE;
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/* Get the AutoNeg Link partner base page */
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if (!at91rm9200_EmacReadPhy (p_mac, DM9161_ANLPAR, &PhyAnalpar))
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return FALSE;
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if ((PhyAnar & DM9161_TX_FDX) && (PhyAnalpar & DM9161_TX_FDX)) {
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/*set MII for 100BaseTX and Full Duplex */
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p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
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return TRUE;
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}
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if ((PhyAnar & DM9161_10_FDX) && (PhyAnalpar & DM9161_10_FDX)) {
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/*set MII for 10BaseT and Full Duplex */
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p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
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~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
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| AT91C_EMAC_FD;
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return TRUE;
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}
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return FALSE;
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}
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/*
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* Name:
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* at91rm92000_GetPhyInterface
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* Description:
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* Initialise the interface functions to the PHY
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* Arguments:
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* None
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* Return value:
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* None
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*/
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void at91rm92000_GetPhyInterface(AT91PS_PhyOps p_phyops)
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{
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p_phyops->Init = dm9161_InitPhy;
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p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
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p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
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p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
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}
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#endif /* CONFIG_COMMANDS & CFG_CMD_NET */
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#endif /* CONFIG_DRIVER_ETHER */
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@ -27,7 +27,7 @@ LIB = lib$(CPU).a
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START = start.o
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OBJS = serial.o interrupts.o cpu.o \
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at91rm9200_ether.o at45.o
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at91rm9200_ether.o
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all: .depend $(START) $(LIB)
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@ -60,205 +60,10 @@ typedef struct {
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#if (CONFIG_COMMANDS & CFG_CMD_NET)
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/* structure to interface the PHY */
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AT91S_PhyOps AT91S_Dm9161Ops;
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AT91PS_PhyOps pPhyOps;
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AT91S_PhyOps PhyOps;
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AT91PS_EMAC p_mac;
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/*************************** Phy layer functions ************************/
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/** functions to interface the DAVICOM 10/100Mbps ethernet phy **********/
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/*
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* Name:
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* dm9161_IsPhyConnected
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* Description:
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* Reads the 2 PHY ID registers
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* Arguments:
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* p_mac - pointer to AT91S_EMAC struct
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* Return value:
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* TRUE - if id read successfully
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* FALSE- if error
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*/
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static unsigned int dm9161_IsPhyConnected (AT91PS_EMAC p_mac)
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{
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unsigned short Id1, Id2;
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at91rm9200_EmacEnableMDIO (p_mac);
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at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID1, &Id1);
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at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID2, &Id2);
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at91rm9200_EmacDisableMDIO (p_mac);
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if ((Id1 == (DM9161_PHYID1_OUI >> 6)) &&
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((Id2 >> 10) == (DM9161_PHYID1_OUI & DM9161_LSB_MASK)))
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return TRUE;
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return FALSE;
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}
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/*
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* Name:
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* dm9161_GetLinkSpeed
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* Description:
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* Link parallel detection status of MAC is checked and set in the
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* MAC configuration registers
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* Arguments:
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* p_mac - pointer to MAC
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* Return value:
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* TRUE - if link status set succesfully
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* FALSE - if link status not set
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*/
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static UCHAR dm9161_GetLinkSpeed (AT91PS_EMAC p_mac)
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{
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unsigned short stat1, stat2;
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if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &stat1))
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return FALSE;
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if (!(stat1 & DM9161_LINK_STATUS)) /* link status up? */
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return FALSE;
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if (!at91rm9200_EmacReadPhy (p_mac, DM9161_DSCSR, &stat2))
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return FALSE;
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if ((stat1 & DM9161_100BASE_TX_FD) && (stat2 & DM9161_100FDX)) {
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/*set Emac for 100BaseTX and Full Duplex */
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p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
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return TRUE;
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}
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if ((stat1 & DM9161_10BASE_T_FD) && (stat2 & DM9161_10FDX)) {
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/*set MII for 10BaseT and Full Duplex */
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p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
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~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
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| AT91C_EMAC_FD;
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return TRUE;
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}
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if ((stat1 & DM9161_100BASE_T4_HD) && (stat2 & DM9161_100HDX)) {
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/*set MII for 100BaseTX and Half Duplex */
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p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
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~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
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| AT91C_EMAC_SPD;
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return TRUE;
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}
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if ((stat1 & DM9161_10BASE_T_HD) && (stat2 & DM9161_10HDX)) {
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/*set MII for 10BaseT and Half Duplex */
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p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
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return TRUE;
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}
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return FALSE;
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}
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/*
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* Name:
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* dm9161_InitPhy
|
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* Description:
|
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* MAC starts checking its link by using parallel detection and
|
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* Autonegotiation and the same is set in the MAC configuration registers
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* Arguments:
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* p_mac - pointer to struct AT91S_EMAC
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* Return value:
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* TRUE - if link status set succesfully
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* FALSE - if link status not set
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*/
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static UCHAR dm9161_InitPhy (AT91PS_EMAC p_mac)
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{
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UCHAR ret = TRUE;
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unsigned short IntValue;
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at91rm9200_EmacEnableMDIO (p_mac);
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if (!dm9161_GetLinkSpeed (p_mac)) {
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/* Try another time */
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ret = dm9161_GetLinkSpeed (p_mac);
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}
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/* Disable PHY Interrupts */
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at91rm9200_EmacReadPhy (p_mac, DM9161_MDINTR, &IntValue);
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/* clear FDX, SPD, Link, INTR masks */
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IntValue &= ~(DM9161_FDX_MASK | DM9161_SPD_MASK |
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DM9161_LINK_MASK | DM9161_INTR_MASK);
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at91rm9200_EmacWritePhy (p_mac, DM9161_MDINTR, &IntValue);
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at91rm9200_EmacDisableMDIO (p_mac);
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return (ret);
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}
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/*
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* Name:
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* dm9161_AutoNegotiate
|
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* Description:
|
||||
* MAC Autonegotiates with the partner status of same is set in the
|
||||
* MAC configuration registers
|
||||
* Arguments:
|
||||
* dev - pointer to struct net_device
|
||||
* Return value:
|
||||
* TRUE - if link status set successfully
|
||||
* FALSE - if link status not set
|
||||
*/
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static UCHAR dm9161_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
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{
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unsigned short value;
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unsigned short PhyAnar;
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unsigned short PhyAnalpar;
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/* Set dm9161 control register */
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if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
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return FALSE;
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value &= ~DM9161_AUTONEG; /* remove autonegotiation enable */
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value |= DM9161_ISOLATE; /* Electrically isolate PHY */
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if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
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||||
return FALSE;
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||||
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||||
/* Set the Auto_negotiation Advertisement Register */
|
||||
/* MII advertising for Next page, 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */
|
||||
PhyAnar = DM9161_NP | DM9161_TX_FDX | DM9161_TX_HDX |
|
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DM9161_10_FDX | DM9161_10_HDX | DM9161_AN_IEEE_802_3;
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if (!at91rm9200_EmacWritePhy (p_mac, DM9161_ANAR, &PhyAnar))
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return FALSE;
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||||
|
||||
/* Read the Control Register */
|
||||
if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
|
||||
return FALSE;
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||||
|
||||
value |= DM9161_SPEED_SELECT | DM9161_AUTONEG | DM9161_DUPLEX_MODE;
|
||||
if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
|
||||
return FALSE;
|
||||
/* Restart Auto_negotiation */
|
||||
value |= DM9161_RESTART_AUTONEG;
|
||||
if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
|
||||
return FALSE;
|
||||
|
||||
/*check AutoNegotiate complete */
|
||||
udelay (10000);
|
||||
at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &value);
|
||||
if (!(value & DM9161_AUTONEG_COMP))
|
||||
return FALSE;
|
||||
|
||||
/* Get the AutoNeg Link partner base page */
|
||||
if (!at91rm9200_EmacReadPhy (p_mac, DM9161_ANLPAR, &PhyAnalpar))
|
||||
return FALSE;
|
||||
|
||||
if ((PhyAnar & DM9161_TX_FDX) && (PhyAnalpar & DM9161_TX_FDX)) {
|
||||
/*set MII for 100BaseTX and Full Duplex */
|
||||
p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
if ((PhyAnar & DM9161_10_FDX) && (PhyAnalpar & DM9161_10_FDX)) {
|
||||
/*set MII for 10BaseT and Full Duplex */
|
||||
p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
|
||||
~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
|
||||
| AT91C_EMAC_FD;
|
||||
return TRUE;
|
||||
}
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
|
||||
/*********** EMAC Phy layer Management functions *************************/
|
||||
/*
|
||||
* Name:
|
||||
|
|
@ -270,7 +75,7 @@ static UCHAR dm9161_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
|
|||
* Return value:
|
||||
* none
|
||||
*/
|
||||
static void at91rm9200_EmacEnableMDIO (AT91PS_EMAC p_mac)
|
||||
void at91rm9200_EmacEnableMDIO (AT91PS_EMAC p_mac)
|
||||
{
|
||||
/* Mac CTRL reg set for MDIO enable */
|
||||
p_mac->EMAC_CTL |= AT91C_EMAC_MPE; /* Management port enable */
|
||||
|
|
@ -286,7 +91,7 @@ static void at91rm9200_EmacEnableMDIO (AT91PS_EMAC p_mac)
|
|||
* Return value:
|
||||
* none
|
||||
*/
|
||||
static void at91rm9200_EmacDisableMDIO (AT91PS_EMAC p_mac)
|
||||
void at91rm9200_EmacDisableMDIO (AT91PS_EMAC p_mac)
|
||||
{
|
||||
/* Mac CTRL reg set for MDIO disable */
|
||||
p_mac->EMAC_CTL &= ~AT91C_EMAC_MPE; /* Management port disable */
|
||||
|
|
@ -305,7 +110,7 @@ static void at91rm9200_EmacDisableMDIO (AT91PS_EMAC p_mac)
|
|||
* Return value:
|
||||
* TRUE - if data read successfully
|
||||
*/
|
||||
static UCHAR at91rm9200_EmacReadPhy (AT91PS_EMAC p_mac,
|
||||
UCHAR at91rm9200_EmacReadPhy (AT91PS_EMAC p_mac,
|
||||
unsigned char RegisterAddress,
|
||||
unsigned short *pInput)
|
||||
{
|
||||
|
|
@ -334,7 +139,7 @@ static UCHAR at91rm9200_EmacReadPhy (AT91PS_EMAC p_mac,
|
|||
* Return value:
|
||||
* TRUE - if data read successfully
|
||||
*/
|
||||
static UCHAR at91rm9200_EmacWritePhy (AT91PS_EMAC p_mac,
|
||||
UCHAR at91rm9200_EmacWritePhy (AT91PS_EMAC p_mac,
|
||||
unsigned char RegisterAddress,
|
||||
unsigned short *pOutput)
|
||||
{
|
||||
|
|
@ -347,26 +152,6 @@ static UCHAR at91rm9200_EmacWritePhy (AT91PS_EMAC p_mac,
|
|||
return TRUE;
|
||||
}
|
||||
|
||||
/*
|
||||
* Name:
|
||||
* at91rm92000_GetPhyInterface
|
||||
* Description:
|
||||
* Initialise the interface functions to the PHY
|
||||
* Arguments:
|
||||
* None
|
||||
* Return value:
|
||||
* None
|
||||
*/
|
||||
void at91rm92000_GetPhyInterface (void)
|
||||
{
|
||||
AT91S_Dm9161Ops.Init = dm9161_InitPhy;
|
||||
AT91S_Dm9161Ops.IsPhyConnected = dm9161_IsPhyConnected;
|
||||
AT91S_Dm9161Ops.GetLinkSpeed = dm9161_GetLinkSpeed;
|
||||
AT91S_Dm9161Ops.AutoNegotiate = dm9161_AutoNegotiate;
|
||||
|
||||
pPhyOps = (AT91PS_PhyOps) & AT91S_Dm9161Ops;
|
||||
}
|
||||
|
||||
|
||||
rbf_t *rbfdt;
|
||||
rbf_t *rbfp;
|
||||
|
|
@ -423,14 +208,14 @@ int eth_init (bd_t * bd)
|
|||
|
||||
p_mac->EMAC_CTL |= AT91C_EMAC_TE | AT91C_EMAC_RE;
|
||||
|
||||
at91rm92000_GetPhyInterface ();
|
||||
at91rm92000_GetPhyInterface (& PhyOps);
|
||||
|
||||
if (!pPhyOps->IsPhyConnected (p_mac))
|
||||
if (!PhyOps.IsPhyConnected (p_mac))
|
||||
printf ("PHY not connected!!\n\r");
|
||||
|
||||
/* MII management start from here */
|
||||
if (!(p_mac->EMAC_SR & AT91C_EMAC_LINK)) {
|
||||
if (!(ret = pPhyOps->Init (p_mac))) {
|
||||
if (!(ret = PhyOps.Init (p_mac))) {
|
||||
printf ("MAC: error during MII initialization\n");
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -22,7 +22,6 @@
|
|||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include "dm9161.h"
|
||||
|
||||
#define FALSE 0
|
||||
#define TRUE 1
|
||||
|
|
@ -49,10 +48,10 @@ typedef struct _AT91S_PhyOps
|
|||
/****************** function prototypes **********************/
|
||||
|
||||
/* MII functions */
|
||||
static void at91rm9200_EmacEnableMDIO(AT91PS_EMAC p_mac);
|
||||
static void at91rm9200_EmacDisableMDIO(AT91PS_EMAC p_mac);
|
||||
static UCHAR at91rm9200_EmacReadPhy(AT91PS_EMAC p_mac, unsigned char RegisterAddress, unsigned short *pInput);
|
||||
static UCHAR at91rm9200_EmacWritePhy(AT91PS_EMAC p_mac, unsigned char RegisterAddress, unsigned short *pOutput);
|
||||
void at91rm92000_GetPhyInterface(void );
|
||||
void at91rm9200_EmacEnableMDIO(AT91PS_EMAC p_mac);
|
||||
void at91rm9200_EmacDisableMDIO(AT91PS_EMAC p_mac);
|
||||
UCHAR at91rm9200_EmacReadPhy(AT91PS_EMAC p_mac, unsigned char RegisterAddress, unsigned short *pInput);
|
||||
UCHAR at91rm9200_EmacWritePhy(AT91PS_EMAC p_mac, unsigned char RegisterAddress, unsigned short *pOutput);
|
||||
void at91rm92000_GetPhyInterface(AT91PS_PhyOps p_phyops);
|
||||
|
||||
#endif /* AT91RM9200_ETHERNET */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,246 @@
|
|||
/***********************************************************************
|
||||
*
|
||||
* Copyright (C) 2004 by FS Forth-Systeme GmbH.
|
||||
* All rights reserved.
|
||||
*
|
||||
* $Id: ns9750_eth.h,v 1.2 2004/02/24 13:25:39 mpietrek Exp $
|
||||
* @Author: Markus Pietrek
|
||||
* @References: [1] NS9750 Hardware Reference, December 2003
|
||||
* [2] Intel LXT971 Datasheet #249414 Rev. 02
|
||||
* [3] NS7520 Linux Ethernet Driver
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
***********************************************************************/
|
||||
|
||||
#ifndef __LXT971A_H__
|
||||
#define __LXT971A_H__
|
||||
|
||||
/* PHY definitions (LXT971A) [2] */
|
||||
#define PHY_COMMON_CTRL (0x00)
|
||||
#define PHY_COMMON_STAT (0x01)
|
||||
#define PHY_COMMON_ID1 (0x02)
|
||||
#define PHY_COMMON_ID2 (0x03)
|
||||
#define PHY_COMMON_AUTO_ADV (0x04)
|
||||
#define PHY_COMMON_AUTO_LNKB (0x05)
|
||||
#define PHY_COMMON_AUTO_EXP (0x06)
|
||||
#define PHY_COMMON_AUTO_NEXT (0x07)
|
||||
#define PHY_COMMON_AUTO_LNKN (0x08)
|
||||
#define PHY_LXT971_PORT_CFG (0x10)
|
||||
#define PHY_LXT971_STAT2 (0x11)
|
||||
#define PHY_LXT971_INT_ENABLE (0x12)
|
||||
#define PHY_LXT971_INT_STATUS (0x13)
|
||||
#define PHY_LXT971_LED_CFG (0x14)
|
||||
#define PHY_LXT971_DIG_CFG (0x1A)
|
||||
#define PHY_LXT971_TX_CTRL (0x1E)
|
||||
|
||||
/* CTRL PHY Control Register Bit Fields */
|
||||
#define PHY_COMMON_CTRL_RESET (0x8000)
|
||||
#define PHY_COMMON_CTRL_LOOPBACK (0x4000)
|
||||
#define PHY_COMMON_CTRL_SPD_MA (0x2040)
|
||||
#define PHY_COMMON_CTRL_SPD_10 (0x0000)
|
||||
#define PHY_COMMON_CTRL_SPD_100 (0x2000)
|
||||
#define PHY_COMMON_CTRL_SPD_1000 (0x0040)
|
||||
#define PHY_COMMON_CTRL_SPD_RES (0x2040)
|
||||
#define PHY_COMMON_CTRL_AUTO_NEG (0x1000)
|
||||
#define PHY_COMMON_CTRL_POWER_DN (0x0800)
|
||||
#define PHY_COMMON_CTRL_ISOLATE (0x0400)
|
||||
#define PHY_COMMON_CTRL_RES_AUTO (0x0200)
|
||||
#define PHY_COMMON_CTRL_DUPLEX (0x0100)
|
||||
#define PHY_COMMON_CTRL_COL_TEST (0x0080)
|
||||
#define PHY_COMMON_CTRL_RES1 (0x003F)
|
||||
|
||||
/* STAT Status Register Bit Fields */
|
||||
#define PHY_COMMON_STAT_100BT4 (0x8000)
|
||||
#define PHY_COMMON_STAT_100BXFD (0x4000)
|
||||
#define PHY_COMMON_STAT_100BXHD (0x2000)
|
||||
#define PHY_COMMON_STAT_10BTFD (0x1000)
|
||||
#define PHY_COMMON_STAT_10BTHD (0x0800)
|
||||
#define PHY_COMMON_STAT_100BT2FD (0x0400)
|
||||
#define PHY_COMMON_STAT_100BT2HD (0x0200)
|
||||
#define PHY_COMMON_STAT_EXT_STAT (0x0100)
|
||||
#define PHY_COMMON_STAT_RES1 (0x0080)
|
||||
#define PHY_COMMON_STAT_MF_PSUP (0x0040)
|
||||
#define PHY_COMMON_STAT_AN_COMP (0x0020)
|
||||
#define PHY_COMMON_STAT_RMT_FLT (0x0010)
|
||||
#define PHY_COMMON_STAT_AN_CAP (0x0008)
|
||||
#define PHY_COMMON_STAT_LNK_STAT (0x0004)
|
||||
#define PHY_COMMON_STAT_JAB_DTCT (0x0002)
|
||||
#define PHY_COMMON_STAT_EXT_CAP (0x0001)
|
||||
|
||||
/* AUTO_ADV Auto-neg Advert Register Bit Fields */
|
||||
#define PHY_COMMON_AUTO_ADV_NP (0x8000)
|
||||
#define PHY_COMMON_AUTO_ADV_RES1 (0x4000)
|
||||
#define PHY_COMMON_AUTO_ADV_RMT_FLT (0x2000)
|
||||
#define PHY_COMMON_AUTO_ADV_RES2 (0x1000)
|
||||
#define PHY_COMMON_AUTO_ADV_AS_PAUSE (0x0800)
|
||||
#define PHY_COMMON_AUTO_ADV_PAUSE (0x0400)
|
||||
#define PHY_COMMON_AUTO_ADV_100BT4 (0x0200)
|
||||
#define PHY_COMMON_AUTO_ADV_100BTXFD (0x0100)
|
||||
#define PHY_COMMON_AUTO_ADV_100BTX (0x0080)
|
||||
#define PHY_COMMON_AUTO_ADV_10BTFD (0x0040)
|
||||
#define PHY_COMMON_AUTO_ADV_10BT (0x0020)
|
||||
#define PHY_COMMON_AUTO_ADV_SEL_FLD_MA (0x001F)
|
||||
#define PHY_COMMON_AUTO_ADV_802_9 (0x0002)
|
||||
#define PHY_COMMON_AUTO_ADV_802_3 (0x0001)
|
||||
|
||||
/* AUTO_LNKB Auto-neg Link Ability Register Bit Fields */
|
||||
#define PHY_COMMON_AUTO_LNKB_NP (0x8000)
|
||||
#define PHY_COMMON_AUTO_LNKB_ACK (0x4000)
|
||||
#define PHY_COMMON_AUTO_LNKB_RMT_FLT (0x2000)
|
||||
#define PHY_COMMON_AUTO_LNKB_RES2 (0x1000)
|
||||
#define PHY_COMMON_AUTO_LNKB_AS_PAUSE (0x0800)
|
||||
#define PHY_COMMON_AUTO_LNKB_PAUSE (0x0400)
|
||||
#define PHY_COMMON_AUTO_LNKB_100BT4 (0x0200)
|
||||
#define PHY_COMMON_AUTO_LNKB_100BTXFD (0x0100)
|
||||
#define PHY_COMMON_AUTO_LNKB_100BTX (0x0080)
|
||||
#define PHY_COMMON_AUTO_LNKB_10BTFD (0x0040)
|
||||
#define PHY_COMMON_AUTO_LNKB_10BT (0x0020)
|
||||
#define PHY_COMMON_AUTO_LNKB_SEL_FLD_MA (0x001F)
|
||||
#define PHY_COMMON_AUTO_LNKB_802_9 (0x0002)
|
||||
#define PHY_COMMON_AUTO_LNKB_802_3 (0x0001)
|
||||
|
||||
/* AUTO_EXP Auto-neg Expansion Register Bit Fields */
|
||||
#define PHY_COMMON_AUTO_EXP_RES1 (0xFFC0)
|
||||
#define PHY_COMMON_AUTO_EXP_BASE_PAGE (0x0020)
|
||||
#define PHY_COMMON_AUTO_EXP_PAR_DT_FLT (0x0010)
|
||||
#define PHY_COMMON_AUTO_EXP_LNK_NP_CAP (0x0008)
|
||||
#define PHY_COMMON_AUTO_EXP_NP_CAP (0x0004)
|
||||
#define PHY_COMMON_AUTO_EXP_PAGE_REC (0x0002)
|
||||
#define PHY_COMMON_AUTO_EXP_LNK_AN_CAP (0x0001)
|
||||
|
||||
/* AUTO_NEXT Aut-neg Next Page Tx Register Bit Fields */
|
||||
#define PHY_COMMON_AUTO_NEXT_NP (0x8000)
|
||||
#define PHY_COMMON_AUTO_NEXT_RES1 (0x4000)
|
||||
#define PHY_COMMON_AUTO_NEXT_MSG_PAGE (0x2000)
|
||||
#define PHY_COMMON_AUTO_NEXT_ACK_2 (0x1000)
|
||||
#define PHY_COMMON_AUTO_NEXT_TOGGLE (0x0800)
|
||||
#define PHY_COMMON_AUTO_NEXT_MSG (0x07FF)
|
||||
|
||||
/* AUTO_LNKN Auto-neg Link Partner Rx Reg Bit Fields */
|
||||
#define PHY_COMMON_AUTO_LNKN_NP (0x8000)
|
||||
#define PHY_COMMON_AUTO_LNKN_ACK (0x4000)
|
||||
#define PHY_COMMON_AUTO_LNKN_MSG_PAGE (0x2000)
|
||||
#define PHY_COMMON_AUTO_LNKN_ACK_2 (0x1000)
|
||||
#define PHY_COMMON_AUTO_LNKN_TOGGLE (0x0800)
|
||||
#define PHY_COMMON_AUTO_LNKN_MSG (0x07FF)
|
||||
|
||||
/* PORT_CFG Port Configuration Register Bit Fields */
|
||||
#define PHY_LXT971_PORT_CFG_RES1 (0x8000)
|
||||
#define PHY_LXT971_PORT_CFG_FORCE_LNK (0x4000)
|
||||
#define PHY_LXT971_PORT_CFG_TX_DISABLE (0x2000)
|
||||
#define PHY_LXT971_PORT_CFG_BYPASS_SCR (0x1000)
|
||||
#define PHY_LXT971_PORT_CFG_RES2 (0x0800)
|
||||
#define PHY_LXT971_PORT_CFG_JABBER (0x0400)
|
||||
#define PHY_LXT971_PORT_CFG_SQE (0x0200)
|
||||
#define PHY_LXT971_PORT_CFG_TP_LOOPBACK (0x0100)
|
||||
#define PHY_LXT971_PORT_CFG_CRS_SEL (0x0080)
|
||||
#define PHY_LXT971_PORT_CFG_SLEEP_MODE (0x0040)
|
||||
#define PHY_LXT971_PORT_CFG_PRE_EN (0x0020)
|
||||
#define PHY_LXT971_PORT_CFG_SLEEP_T_MA (0x0018)
|
||||
#define PHY_LXT971_PORT_CFG_SLEEP_T_104 (0x0010)
|
||||
#define PHY_LXT971_PORT_CFG_SLEEP_T_200 (0x0001)
|
||||
#define PHY_LXT971_PORT_CFG_SLEEP_T_304 (0x0000)
|
||||
#define PHY_LXT971_PORT_CFG_FLT_CODE_EN (0x0004)
|
||||
#define PHY_LXT971_PORT_CFG_ALT_NP (0x0002)
|
||||
#define PHY_LXT971_PORT_CFG_FIBER_SEL (0x0001)
|
||||
|
||||
/* STAT2 Status Register #2 Bit Fields */
|
||||
#define PHY_LXT971_STAT2_RES1 (0x8000)
|
||||
#define PHY_LXT971_STAT2_100BTX (0x4000)
|
||||
#define PHY_LXT971_STAT2_TX_STATUS (0x2000)
|
||||
#define PHY_LXT971_STAT2_RX_STATUS (0x1000)
|
||||
#define PHY_LXT971_STAT2_COL_STATUS (0x0800)
|
||||
#define PHY_LXT971_STAT2_LINK (0x0400)
|
||||
#define PHY_LXT971_STAT2_DUPLEX_MODE (0x0200)
|
||||
#define PHY_LXT971_STAT2_AUTO_NEG (0x0100)
|
||||
#define PHY_LXT971_STAT2_AUTO_NEG_COMP (0x0080)
|
||||
#define PHY_LXT971_STAT2_RES2 (0x0040)
|
||||
#define PHY_LXT971_STAT2_POLARITY (0x0020)
|
||||
#define PHY_LXT971_STAT2_PAUSE (0x0010)
|
||||
#define PHY_LXT971_STAT2_ERROR (0x0008)
|
||||
#define PHY_LXT971_STAT2_RES3 (0x0007)
|
||||
|
||||
/* INT_ENABLE Interrupt Enable Register Bit Fields */
|
||||
#define PHY_LXT971_INT_ENABLE_RES1 (0xFF00)
|
||||
#define PHY_LXT971_INT_ENABLE_ANMSK (0x0080)
|
||||
#define PHY_LXT971_INT_ENABLE_SPEEDMSK (0x0040)
|
||||
#define PHY_LXT971_INT_ENABLE_DUPLEXMSK (0x0020)
|
||||
#define PHY_LXT971_INT_ENABLE_LINKMSK (0x0010)
|
||||
#define PHY_LXT971_INT_ENABLE_RES2 (0x000C)
|
||||
#define PHY_LXT971_INT_ENABLE_INTEN (0x0002)
|
||||
#define PHY_LXT971_INT_ENABLE_TINT (0x0001)
|
||||
|
||||
/* INT_STATUS Interrupt Status Register Bit Fields */
|
||||
#define PHY_LXT971_INT_STATUS_RES1 (0xFF00)
|
||||
#define PHY_LXT971_INT_STATUS_ANDONE (0x0080)
|
||||
#define PHY_LXT971_INT_STATUS_SPEEDCHG (0x0040)
|
||||
#define PHY_LXT971_INT_STATUS_DUPLEXCHG (0x0020)
|
||||
#define PHY_LXT971_INT_STATUS_LINKCHG (0x0010)
|
||||
#define PHY_LXT971_INT_STATUS_RES2 (0x0008)
|
||||
#define PHY_LXT971_INT_STATUS_MDINT (0x0004)
|
||||
#define PHY_LXT971_INT_STATUS_RES3 (0x0003)
|
||||
|
||||
/* LED_CFG Interrupt LED Configuration Register Bit Fields */
|
||||
#define PHY_LXT971_LED_CFG_SHIFT_LED1 (0x000C)
|
||||
#define PHY_LXT971_LED_CFG_SHIFT_LED2 (0x0008)
|
||||
#define PHY_LXT971_LED_CFG_SHIFT_LED3 (0x0004)
|
||||
#define PHY_LXT971_LED_CFG_LEDFREQ_MA (0x000C)
|
||||
#define PHY_LXT971_LED_CFG_LEDFREQ_RES (0x000C)
|
||||
#define PHY_LXT971_LED_CFG_LEDFREQ_100 (0x0008)
|
||||
#define PHY_LXT971_LED_CFG_LEDFREQ_60 (0x0004)
|
||||
#define PHY_LXT971_LED_CFG_LEDFREQ_30 (0x0000)
|
||||
#define PHY_LXT971_LED_CFG_PULSE_STR (0x0002)
|
||||
#define PHY_LXT971_LED_CFG_RES1 (0x0001)
|
||||
|
||||
/* only one of these values must be shifted for each SHIFT_LED? */
|
||||
#define PHY_LXT971_LED_CFG_UNUSED1 (0x000F)
|
||||
#define PHY_LXT971_LED_CFG_DUPLEX_COL (0x000E)
|
||||
#define PHY_LXT971_LED_CFG_LINK_ACT (0x000D)
|
||||
#define PHY_LXT971_LED_CFG_LINK_RX (0x000C)
|
||||
#define PHY_LXT971_LED_CFG_TEST_BLK_SLW (0x000B)
|
||||
#define PHY_LXT971_LED_CFG_TEST_BLK_FST (0x000A)
|
||||
#define PHY_LXT971_LED_CFG_TEST_OFF (0x0009)
|
||||
#define PHY_LXT971_LED_CFG_TEST_ON (0x0008)
|
||||
#define PHY_LXT971_LED_CFG_RX_OR_TX (0x0007)
|
||||
#define PHY_LXT971_LED_CFG_UNUSED2 (0x0006)
|
||||
#define PHY_LXT971_LED_CFG_DUPLEX (0x0005)
|
||||
#define PHY_LXT971_LED_CFG_LINK (0x0004)
|
||||
#define PHY_LXT971_LED_CFG_COLLISION (0x0003)
|
||||
#define PHY_LXT971_LED_CFG_RECEIVE (0x0002)
|
||||
#define PHY_LXT971_LED_CFG_TRANSMIT (0x0001)
|
||||
#define PHY_LXT971_LED_CFG_SPEED (0x0000)
|
||||
|
||||
/* DIG_CFG Digitial Configuration Register Bit Fields */
|
||||
#define PHY_LXT971_DIG_CFG_RES1 (0xF000)
|
||||
#define PHY_LXT971_DIG_CFG_MII_DRIVE (0x0800)
|
||||
#define PHY_LXT971_DIG_CFG_RES2 (0x0400)
|
||||
#define PHY_LXT971_DIG_CFG_SHOW_SYMBOL (0x0200)
|
||||
#define PHY_LXT971_DIG_CFG_RES3 (0x01FF)
|
||||
|
||||
#define PHY_LXT971_MDIO_MAX_CLK (8000000)
|
||||
#define PHY_MDIO_MAX_CLK (2500000)
|
||||
|
||||
/* TX_CTRL Transmit Control Register Bit Fields
|
||||
documentation is buggy for this register, therefore setting not included */
|
||||
|
||||
typedef enum
|
||||
{
|
||||
PHY_NONE = 0x0000, /* no PHY detected yet */
|
||||
PHY_LXT971A = 0x0013
|
||||
} PhyType;
|
||||
|
||||
#endif /* __LXT971A_H__ */
|
||||
|
|
@ -31,6 +31,8 @@
|
|||
|
||||
#ifdef CONFIG_DRIVER_NS9750_ETHERNET
|
||||
|
||||
#include "lxt971a.h"
|
||||
|
||||
#define NS9750_ETH_MODULE_BASE (0xA0600000)
|
||||
|
||||
#define get_eth_reg_addr(c) \
|
||||
|
|
@ -286,237 +288,6 @@
|
|||
#define NS9750_ETH_RXFREE_B (0x00000002)
|
||||
#define NS9750_ETH_RXFREE_A (0x00000001)
|
||||
|
||||
/* PHY definitions (LXT971A) [2] */
|
||||
|
||||
#define PHY_COMMON_CTRL (0x00)
|
||||
#define PHY_COMMON_STAT (0x01)
|
||||
#define PHY_COMMON_ID1 (0x02)
|
||||
#define PHY_COMMON_ID2 (0x03)
|
||||
#define PHY_COMMON_AUTO_ADV (0x04)
|
||||
#define PHY_COMMON_AUTO_LNKB (0x05)
|
||||
#define PHY_COMMON_AUTO_EXP (0x06)
|
||||
#define PHY_COMMON_AUTO_NEXT (0x07)
|
||||
#define PHY_COMMON_AUTO_LNKN (0x08)
|
||||
#define PHY_LXT971_PORT_CFG (0x10)
|
||||
#define PHY_LXT971_STAT2 (0x11)
|
||||
#define PHY_LXT971_INT_ENABLE (0x12)
|
||||
#define PHY_LXT971_INT_STATUS (0x13)
|
||||
#define PHY_LXT971_LED_CFG (0x14)
|
||||
#define PHY_LXT971_DIG_CFG (0x1A)
|
||||
#define PHY_LXT971_TX_CTRL (0x1E)
|
||||
|
||||
/* CTRL PHY Control Register Bit Fields */
|
||||
|
||||
#define PHY_COMMON_CTRL_RESET (0x8000)
|
||||
#define PHY_COMMON_CTRL_LOOPBACK (0x4000)
|
||||
#define PHY_COMMON_CTRL_SPD_MA (0x2040)
|
||||
#define PHY_COMMON_CTRL_SPD_10 (0x0000)
|
||||
#define PHY_COMMON_CTRL_SPD_100 (0x2000)
|
||||
#define PHY_COMMON_CTRL_SPD_1000 (0x0040)
|
||||
#define PHY_COMMON_CTRL_SPD_RES (0x2040)
|
||||
#define PHY_COMMON_CTRL_AUTO_NEG (0x1000)
|
||||
#define PHY_COMMON_CTRL_POWER_DN (0x0800)
|
||||
#define PHY_COMMON_CTRL_ISOLATE (0x0400)
|
||||
#define PHY_COMMON_CTRL_RES_AUTO (0x0200)
|
||||
#define PHY_COMMON_CTRL_DUPLEX (0x0100)
|
||||
#define PHY_COMMON_CTRL_COL_TEST (0x0080)
|
||||
#define PHY_COMMON_CTRL_RES1 (0x003F)
|
||||
|
||||
/* STAT Status Register Bit Fields */
|
||||
|
||||
#define PHY_COMMON_STAT_100BT4 (0x8000)
|
||||
#define PHY_COMMON_STAT_100BXFD (0x4000)
|
||||
#define PHY_COMMON_STAT_100BXHD (0x2000)
|
||||
#define PHY_COMMON_STAT_10BTFD (0x1000)
|
||||
#define PHY_COMMON_STAT_10BTHD (0x0800)
|
||||
#define PHY_COMMON_STAT_100BT2FD (0x0400)
|
||||
#define PHY_COMMON_STAT_100BT2HD (0x0200)
|
||||
#define PHY_COMMON_STAT_EXT_STAT (0x0100)
|
||||
#define PHY_COMMON_STAT_RES1 (0x0080)
|
||||
#define PHY_COMMON_STAT_MF_PSUP (0x0040)
|
||||
#define PHY_COMMON_STAT_AN_COMP (0x0020)
|
||||
#define PHY_COMMON_STAT_RMT_FLT (0x0010)
|
||||
#define PHY_COMMON_STAT_AN_CAP (0x0008)
|
||||
#define PHY_COMMON_STAT_LNK_STAT (0x0004)
|
||||
#define PHY_COMMON_STAT_JAB_DTCT (0x0002)
|
||||
#define PHY_COMMON_STAT_EXT_CAP (0x0001)
|
||||
|
||||
|
||||
/* AUTO_ADV Auto-neg Advert Register Bit Fields */
|
||||
|
||||
#define PHY_COMMON_AUTO_ADV_NP (0x8000)
|
||||
#define PHY_COMMON_AUTO_ADV_RES1 (0x4000)
|
||||
#define PHY_COMMON_AUTO_ADV_RMT_FLT (0x2000)
|
||||
#define PHY_COMMON_AUTO_ADV_RES2 (0x1000)
|
||||
#define PHY_COMMON_AUTO_ADV_AS_PAUSE (0x0800)
|
||||
#define PHY_COMMON_AUTO_ADV_PAUSE (0x0400)
|
||||
#define PHY_COMMON_AUTO_ADV_100BT4 (0x0200)
|
||||
#define PHY_COMMON_AUTO_ADV_100BTXFD (0x0100)
|
||||
#define PHY_COMMON_AUTO_ADV_100BTX (0x0080)
|
||||
#define PHY_COMMON_AUTO_ADV_10BTFD (0x0040)
|
||||
#define PHY_COMMON_AUTO_ADV_10BT (0x0020)
|
||||
#define PHY_COMMON_AUTO_ADV_SEL_FLD_MA (0x001F)
|
||||
#define PHY_COMMON_AUTO_ADV_802_9 (0x0002)
|
||||
#define PHY_COMMON_AUTO_ADV_802_3 (0x0001)
|
||||
|
||||
/* AUTO_LNKB Auto-neg Link Ability Register Bit Fields */
|
||||
|
||||
#define PHY_COMMON_AUTO_LNKB_NP (0x8000)
|
||||
#define PHY_COMMON_AUTO_LNKB_ACK (0x4000)
|
||||
#define PHY_COMMON_AUTO_LNKB_RMT_FLT (0x2000)
|
||||
#define PHY_COMMON_AUTO_LNKB_RES2 (0x1000)
|
||||
#define PHY_COMMON_AUTO_LNKB_AS_PAUSE (0x0800)
|
||||
#define PHY_COMMON_AUTO_LNKB_PAUSE (0x0400)
|
||||
#define PHY_COMMON_AUTO_LNKB_100BT4 (0x0200)
|
||||
#define PHY_COMMON_AUTO_LNKB_100BTXFD (0x0100)
|
||||
#define PHY_COMMON_AUTO_LNKB_100BTX (0x0080)
|
||||
#define PHY_COMMON_AUTO_LNKB_10BTFD (0x0040)
|
||||
#define PHY_COMMON_AUTO_LNKB_10BT (0x0020)
|
||||
#define PHY_COMMON_AUTO_LNKB_SEL_FLD_MA (0x001F)
|
||||
#define PHY_COMMON_AUTO_LNKB_802_9 (0x0002)
|
||||
#define PHY_COMMON_AUTO_LNKB_802_3 (0x0001)
|
||||
|
||||
/* AUTO_EXP Auto-neg Expansion Register Bit Fields */
|
||||
|
||||
#define PHY_COMMON_AUTO_EXP_RES1 (0xFFC0)
|
||||
#define PHY_COMMON_AUTO_EXP_BASE_PAGE (0x0020)
|
||||
#define PHY_COMMON_AUTO_EXP_PAR_DT_FLT (0x0010)
|
||||
#define PHY_COMMON_AUTO_EXP_LNK_NP_CAP (0x0008)
|
||||
#define PHY_COMMON_AUTO_EXP_NP_CAP (0x0004)
|
||||
#define PHY_COMMON_AUTO_EXP_PAGE_REC (0x0002)
|
||||
#define PHY_COMMON_AUTO_EXP_LNK_AN_CAP (0x0001)
|
||||
|
||||
/* AUTO_NEXT Aut-neg Next Page Tx Register Bit Fields */
|
||||
|
||||
#define PHY_COMMON_AUTO_NEXT_NP (0x8000)
|
||||
#define PHY_COMMON_AUTO_NEXT_RES1 (0x4000)
|
||||
#define PHY_COMMON_AUTO_NEXT_MSG_PAGE (0x2000)
|
||||
#define PHY_COMMON_AUTO_NEXT_ACK_2 (0x1000)
|
||||
#define PHY_COMMON_AUTO_NEXT_TOGGLE (0x0800)
|
||||
#define PHY_COMMON_AUTO_NEXT_MSG (0x07FF)
|
||||
|
||||
/* AUTO_LNKN Auto-neg Link Partner Rx Reg Bit Fields */
|
||||
|
||||
#define PHY_COMMON_AUTO_LNKN_NP (0x8000)
|
||||
#define PHY_COMMON_AUTO_LNKN_ACK (0x4000)
|
||||
#define PHY_COMMON_AUTO_LNKN_MSG_PAGE (0x2000)
|
||||
#define PHY_COMMON_AUTO_LNKN_ACK_2 (0x1000)
|
||||
#define PHY_COMMON_AUTO_LNKN_TOGGLE (0x0800)
|
||||
#define PHY_COMMON_AUTO_LNKN_MSG (0x07FF)
|
||||
|
||||
/* PORT_CFG Port Configuration Register Bit Fields */
|
||||
|
||||
#define PHY_LXT971_PORT_CFG_RES1 (0x8000)
|
||||
#define PHY_LXT971_PORT_CFG_FORCE_LNK (0x4000)
|
||||
#define PHY_LXT971_PORT_CFG_TX_DISABLE (0x2000)
|
||||
#define PHY_LXT971_PORT_CFG_BYPASS_SCR (0x1000)
|
||||
#define PHY_LXT971_PORT_CFG_RES2 (0x0800)
|
||||
#define PHY_LXT971_PORT_CFG_JABBER (0x0400)
|
||||
#define PHY_LXT971_PORT_CFG_SQE (0x0200)
|
||||
#define PHY_LXT971_PORT_CFG_TP_LOOPBACK (0x0100)
|
||||
#define PHY_LXT971_PORT_CFG_CRS_SEL (0x0080)
|
||||
#define PHY_LXT971_PORT_CFG_SLEEP_MODE (0x0040)
|
||||
#define PHY_LXT971_PORT_CFG_PRE_EN (0x0020)
|
||||
#define PHY_LXT971_PORT_CFG_SLEEP_T_MA (0x0018)
|
||||
#define PHY_LXT971_PORT_CFG_SLEEP_T_104 (0x0010)
|
||||
#define PHY_LXT971_PORT_CFG_SLEEP_T_200 (0x0001)
|
||||
#define PHY_LXT971_PORT_CFG_SLEEP_T_304 (0x0000)
|
||||
#define PHY_LXT971_PORT_CFG_FLT_CODE_EN (0x0004)
|
||||
#define PHY_LXT971_PORT_CFG_ALT_NP (0x0002)
|
||||
#define PHY_LXT971_PORT_CFG_FIBER_SEL (0x0001)
|
||||
|
||||
/* STAT2 Status Register #2 Bit Fields */
|
||||
|
||||
#define PHY_LXT971_STAT2_RES1 (0x8000)
|
||||
#define PHY_LXT971_STAT2_100BTX (0x4000)
|
||||
#define PHY_LXT971_STAT2_TX_STATUS (0x2000)
|
||||
#define PHY_LXT971_STAT2_RX_STATUS (0x1000)
|
||||
#define PHY_LXT971_STAT2_COL_STATUS (0x0800)
|
||||
#define PHY_LXT971_STAT2_LINK (0x0400)
|
||||
#define PHY_LXT971_STAT2_DUPLEX_MODE (0x0200)
|
||||
#define PHY_LXT971_STAT2_AUTO_NEG (0x0100)
|
||||
#define PHY_LXT971_STAT2_AUTO_NEG_COMP (0x0080)
|
||||
#define PHY_LXT971_STAT2_RES2 (0x0040)
|
||||
#define PHY_LXT971_STAT2_POLARITY (0x0020)
|
||||
#define PHY_LXT971_STAT2_PAUSE (0x0010)
|
||||
#define PHY_LXT971_STAT2_ERROR (0x0008)
|
||||
#define PHY_LXT971_STAT2_RES3 (0x0007)
|
||||
|
||||
/* INT_ENABLE Interrupt Enable Register Bit Fields */
|
||||
|
||||
#define PHY_LXT971_INT_ENABLE_RES1 (0xFF00)
|
||||
#define PHY_LXT971_INT_ENABLE_ANMSK (0x0080)
|
||||
#define PHY_LXT971_INT_ENABLE_SPEEDMSK (0x0040)
|
||||
#define PHY_LXT971_INT_ENABLE_DUPLEXMSK (0x0020)
|
||||
#define PHY_LXT971_INT_ENABLE_LINKMSK (0x0010)
|
||||
#define PHY_LXT971_INT_ENABLE_RES2 (0x000C)
|
||||
#define PHY_LXT971_INT_ENABLE_INTEN (0x0002)
|
||||
#define PHY_LXT971_INT_ENABLE_TINT (0x0001)
|
||||
|
||||
/* INT_STATUS Interrupt Status Register Bit Fields */
|
||||
|
||||
#define PHY_LXT971_INT_STATUS_RES1 (0xFF00)
|
||||
#define PHY_LXT971_INT_STATUS_ANDONE (0x0080)
|
||||
#define PHY_LXT971_INT_STATUS_SPEEDCHG (0x0040)
|
||||
#define PHY_LXT971_INT_STATUS_DUPLEXCHG (0x0020)
|
||||
#define PHY_LXT971_INT_STATUS_LINKCHG (0x0010)
|
||||
#define PHY_LXT971_INT_STATUS_RES2 (0x0008)
|
||||
#define PHY_LXT971_INT_STATUS_MDINT (0x0004)
|
||||
#define PHY_LXT971_INT_STATUS_RES3 (0x0003)
|
||||
|
||||
/* LED_CFG Interrupt LED Configuration Register Bit Fields */
|
||||
|
||||
#define PHY_LXT971_LED_CFG_SHIFT_LED1 (0x000C)
|
||||
#define PHY_LXT971_LED_CFG_SHIFT_LED2 (0x0008)
|
||||
#define PHY_LXT971_LED_CFG_SHIFT_LED3 (0x0004)
|
||||
#define PHY_LXT971_LED_CFG_LEDFREQ_MA (0x000C)
|
||||
#define PHY_LXT971_LED_CFG_LEDFREQ_RES (0x000C)
|
||||
#define PHY_LXT971_LED_CFG_LEDFREQ_100 (0x0008)
|
||||
#define PHY_LXT971_LED_CFG_LEDFREQ_60 (0x0004)
|
||||
#define PHY_LXT971_LED_CFG_LEDFREQ_30 (0x0000)
|
||||
#define PHY_LXT971_LED_CFG_PULSE_STR (0x0002)
|
||||
#define PHY_LXT971_LED_CFG_RES1 (0x0001)
|
||||
|
||||
/* only one of these values must be shifted for each SHIFT_LED? */
|
||||
|
||||
#define PHY_LXT971_LED_CFG_UNUSED1 (0x000F)
|
||||
#define PHY_LXT971_LED_CFG_DUPLEX_COL (0x000E)
|
||||
#define PHY_LXT971_LED_CFG_LINK_ACT (0x000D)
|
||||
#define PHY_LXT971_LED_CFG_LINK_RX (0x000C)
|
||||
#define PHY_LXT971_LED_CFG_TEST_BLK_SLW (0x000B)
|
||||
#define PHY_LXT971_LED_CFG_TEST_BLK_FST (0x000A)
|
||||
#define PHY_LXT971_LED_CFG_TEST_OFF (0x0009)
|
||||
#define PHY_LXT971_LED_CFG_TEST_ON (0x0008)
|
||||
#define PHY_LXT971_LED_CFG_RX_OR_TX (0x0007)
|
||||
#define PHY_LXT971_LED_CFG_UNUSED2 (0x0006)
|
||||
#define PHY_LXT971_LED_CFG_DUPLEX (0x0005)
|
||||
#define PHY_LXT971_LED_CFG_LINK (0x0004)
|
||||
#define PHY_LXT971_LED_CFG_COLLISION (0x0003)
|
||||
#define PHY_LXT971_LED_CFG_RECEIVE (0x0002)
|
||||
#define PHY_LXT971_LED_CFG_TRANSMIT (0x0001)
|
||||
#define PHY_LXT971_LED_CFG_SPEED (0x0000)
|
||||
|
||||
/* DIG_CFG Digitial Configuration Register Bit Fields */
|
||||
|
||||
#define PHY_LXT971_DIG_CFG_RES1 (0xF000)
|
||||
#define PHY_LXT971_DIG_CFG_MII_DRIVE (0x0800)
|
||||
#define PHY_LXT971_DIG_CFG_RES2 (0x0400)
|
||||
#define PHY_LXT971_DIG_CFG_SHOW_SYMBOL (0x0200)
|
||||
#define PHY_LXT971_DIG_CFG_RES3 (0x01FF)
|
||||
|
||||
#define PHY_LXT971_MDIO_MAX_CLK (8000000)
|
||||
|
||||
/* TX_CTRL Transmit Control Register Bit Fields
|
||||
documentation is buggy for this register, therefore setting not included */
|
||||
|
||||
typedef enum
|
||||
{
|
||||
PHY_NONE = 0x0000, /* no PHY detected yet */
|
||||
PHY_LXT971A = 0x0013
|
||||
} PhyType;
|
||||
|
||||
#define PHY_MDIO_MAX_CLK (2500000)
|
||||
|
||||
#ifndef NS9750_ETH_PHY_ADDRESS
|
||||
# define NS9750_ETH_PHY_ADDRESS (0x0001) /* suitable for UNC20 */
|
||||
#endif /* NETARM_ETH_PHY_ADDRESS */
|
||||
|
|
|
|||
Loading…
Reference in New Issue