brain-hackers_pepepper-mirror/u-boot-brain
1
0
Fork 0
mirror of https://github.com/brain-hackers/u-boot-brain synced 2024-07-07 19:56:18 +09:00
Code Issues Projects Releases Wiki Activity

mip405.c: Fix GCC 4.6 build warnings

Browse Source 
Fix:
mip405.c: In function 'init_sdram':
mip405.c:250:4: warning: variable 'tctp_clocks' set but not used [-Wunused-but-set-variable]
mip405.c: In function 'initdram':
mip405.c:629:9: warning: variable 'ds' set but not used [-Wunused-but-set-variable]

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2011-11-15 08:03:39 +00:00 committed by Wolfgang Denk
parent 80b68f70fd
commit 4233fafe9e
1 changed files with 3 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
board/mpl/mip405/mip405.c
View File

@ -246,8 +246,7 @@ int init_sdram (void)
unsigned char trp_clocks, unsigned char trp_clocks,
trcd_clocks, trcd_clocks,
tras_clocks, tras_clocks,
trc_clocks, trc_clocks;
tctp_clocks;
unsigned char cal_val; unsigned char cal_val;
unsigned char bc; unsigned char bc;
unsigned long sdram_tim, sdram_bank; unsigned long sdram_tim, sdram_bank;
@ -345,7 +344,6 @@ int init_sdram (void)
trcd_clocks = sdram_table[i].trcd; /* 20ns /7.5 ns (datain[29]) */ trcd_clocks = sdram_table[i].trcd; /* 20ns /7.5 ns (datain[29]) */
tras_clocks = sdram_table[i].tras; /* 44ns /7.5 ns (datain[30]) */ tras_clocks = sdram_table[i].tras; /* 44ns /7.5 ns (datain[30]) */
/* ctp = ((trp + tras) - trp - trcd) => tras - trcd */ /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */
tctp_clocks = sdram_table[i].tctp; /* 44 - 20ns = 24ns */
/* trc_clocks is sum of trp_clocks + tras_clocks */ /* trc_clocks is sum of trp_clocks + tras_clocks */
trc_clocks = trp_clocks + tras_clocks; trc_clocks = trp_clocks + tras_clocks;
/* get SDRAM timing register */ /* get SDRAM timing register */
@ -626,10 +624,9 @@ phys_size_t initdram (int board_type)
{ {
unsigned long bank_reg[4], tmp, bank_size; unsigned long bank_reg[4], tmp, bank_size;
int i, ds; int i;
unsigned long TotalSize; unsigned long TotalSize;
ds = 0;
/* since the DRAM controller is allready set up, calculate the size with the /* since the DRAM controller is allready set up, calculate the size with the
bank registers */ bank registers */
mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
@ -646,8 +643,7 @@ phys_size_t initdram (int board_type)
tmp = (bank_reg[i] >> 17) & 0x7; tmp = (bank_reg[i] >> 17) & 0x7;
bank_size = 4 << tmp; bank_size = 4 << tmp;
TotalSize += bank_size; TotalSize += bank_size;
} else }
ds = 1;
} }
mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
tmp = mfdcr (SDRAM0_CFGDATA); tmp = mfdcr (SDRAM0_CFGDATA);