brain-hackers_pepepper-mirror/u-boot-brain
1
0
Fork 0
mirror of https://github.com/brain-hackers/u-boot-brain synced 2024-06-09 23:36:03 +09:00
Code Issues Projects Releases Wiki Activity

powerpc: P1025: Remove macro CONFIG_P1025

Browse Source 
Replace CONFIG_P1025 with ARCH_P1025 in Kconfig and clean up
existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
This commit is contained in:
York Sun 2016-11-18 11:05:38 -08:00
parent 52b6f13d2c
commit 4167a67d5d
9 changed files with 14 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
arch/powerpc/cpu/mpc85xx/Kconfig
View File

@ -156,6 +156,7 @@ config TARGET_P1025RDB
bool "Support P1025RDB"
select SUPPORT_SPL
select SUPPORT_TPL
select ARCH_P1025
config TARGET_P2020RDB
bool "Support P2020RDB-PC"
@ -164,6 +165,7 @@ config TARGET_P2020RDB
config TARGET_P1_TWR
bool "Support p1_twr"
select ARCH_P1025
config TARGET_P2041RDB
bool "Support P2041RDB"
@ -301,6 +303,9 @@ config ARCH_P1023
config ARCH_P1024
bool
config ARCH_P1025
bool
source "board/freescale/b4860qds/Kconfig"
source "board/freescale/bsc9131rdb/Kconfig"
source "board/freescale/bsc9132qds/Kconfig"

2
arch/powerpc/cpu/mpc85xx/Makefile
View File

@ -79,7 +79,7 @@ obj-$(CONFIG_ARCH_P1021) += p1021_serdes.o
obj-$(CONFIG_ARCH_P1022) += p1022_serdes.o
obj-$(CONFIG_ARCH_P1023) += p1023_serdes.o
obj-$(CONFIG_ARCH_P1024) += p1021_serdes.o
obj-$(CONFIG_P1025) += p1021_serdes.o
obj-$(CONFIG_ARCH_P1025) += p1021_serdes.o
obj-$(CONFIG_P2010) += p2020_serdes.o
obj-$(CONFIG_P2020) += p2020_serdes.o
obj-$(CONFIG_PPC_P2041) += p2041_serdes.o

2
arch/powerpc/cpu/mpc85xx/speed.c
View File

@ -596,7 +596,7 @@ void get_sys_info(sys_info_t *sys_info)
#endif
#ifdef CONFIG_QE
#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_P1025)
#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
sys_info->freq_qe = sys_info->freq_systembus;
#else
qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)

2
arch/powerpc/include/asm/config_mpc85xx.h
View File

@ -265,7 +265,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A005125
/* P1025 is lower end variant of P1021 */
#elif defined(CONFIG_P1025)
#elif defined(CONFIG_ARCH_P1025)
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1

2
arch/powerpc/include/asm/immap_85xx.h
View File

@ -2488,7 +2488,7 @@ typedef struct ccsr_gur {
u8 res11a[76];
par_io_t qe_par_io[7];
u8 res11b[1600];
#elif defined(CONFIG_ARCH_P1021) || defined(CONFIG_P1025)
#elif defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
u8 res11a[12];
u32 iovselsr;
u8 res11b[60];

10
drivers/qe/uec.c
View File

@ -567,7 +567,7 @@ static void phy_change(struct eth_device *dev)
{
uec_private_t *uec = (uec_private_t *)dev->priv;
#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_P1025)
#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
/* QE9 and QE12 need to be set for enabling QE MII managment signals */
@ -578,7 +578,7 @@ static void phy_change(struct eth_device *dev)
/* Update the link, speed, duplex */
uec->mii_info->phyinfo->read_status(uec->mii_info);
#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_P1025)
#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
/*
* QE12 is muxed with LBCTL, it needs to be released for enabling
* LBCTL signal for LBC usage.
@ -1193,14 +1193,14 @@ static int uec_init(struct eth_device* dev, bd_t *bd)
uec_private_t *uec;
int err, i;
struct phy_info *curphy;
#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_P1025)
#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif
uec = (uec_private_t *)dev->priv;
if (uec->the_first_run == 0) {
#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_P1025)
#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
/* QE9 and QE12 need to be set for enabling QE MII managment signals */
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
@ -1232,7 +1232,7 @@ static int uec_init(struct eth_device* dev, bd_t *bd)
udelay(100000);
} while (1);
#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_P1025)
#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
/* QE12 needs to be released for enabling LBCTL signal*/
clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
#endif

1
include/configs/p1_p2_rdb_pc.h
View File

@ -128,7 +128,6 @@
#if defined(CONFIG_TARGET_P1025RDB)
#define CONFIG_BOARDNAME "P1025RDB"
#define CONFIG_NAND_FSL_ELBC
#define CONFIG_P1025
#define CONFIG_QE
#define CONFIG_SLIC

1
include/configs/p1_twr.h
View File

@ -12,7 +12,6 @@
#if defined(CONFIG_TWR_P1025)
#define CONFIG_BOARDNAME "TWR-P1025"
#define CONFIG_P1025
#define CONFIG_PHY_ATHEROS
#define CONFIG_QE
#define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */

1
scripts/config_whitelist.txt
View File

@ -3383,7 +3383,6 @@ CONFIG_OS2_ENV_ADDR
CONFIG_OS_ENV_ADDR
CONFIG_OTHBOOTARGS
CONFIG_OVERWRITE_ETHADDR_ONCE
CONFIG_P1025
CONFIG_P2020
CONFIG_P2041RDB
CONFIG_P3041DS