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clk: renesas: Only ever access documented bits in clock driver teardown

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The clock driver used a heavy-handed approach where it turned off
all available clocks, while also possibly setting bits which are not
documented in the R-Car datasheet. Update the tables so that only
the bits which are documented are set or cleared when tearing down
the clock driver.

Note that the only clock left running before booting Linux are now
MFIC, INTC-AP, INTC-EX and SCIF2 / SCIF0 on V3x.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
This commit is contained in:
Marek Vasut 2020-04-25 14:57:45 +02:00 committed by Stefan Roese
parent fbe127f7b5
commit 40c9728d24
7 changed files with 81 additions and 81 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
drivers/clk/renesas/r8a7795-cpg-mssr.c
View File

@ -327,17 +327,17 @@ static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
};
static const struct mstp_stop_table r8a7795_mstp_table[] = {
{ 0x00640800, 0x0, 0x00640800, 0 },
{ 0xF3EE9390, 0x0, 0xF3EE9390, 0 },
{ 0x340FAFDC, 0x2040, 0x340FAFDC, 0 },
{ 0xD80C7CDF, 0x400, 0xD80C7CDF, 0 },
{ 0x80000184, 0x180, 0x80000184, 0 },
{ 0x40BFFF46, 0x0, 0x40BFFF46, 0 },
{ 0xE5FBEECF, 0x0, 0xE5FBEECF, 0 },
{ 0x39FFFF0E, 0x0, 0x39FFFF0E, 0 },
{ 0x01F19FF4, 0x0, 0x01F19FF4, 0 },
{ 0xFFDFFFFF, 0x0, 0xFFDFFFFF, 0 },
{ 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
{ 0x00210000, 0x0, 0x00210000, 0 },
{ 0xc3ec13a0, 0x0, 0xc3ec13a0, 0 },
{ 0x040e2fdc, 0x2000, 0x040e2fdc, 0 },
{ 0xf4cc7cdf, 0x400, 0xf4cc7cdf, 0 },
{ 0x80000004, 0x180, 0x80000004, 0 },
{ 0x40dfff46, 0x0, 0x40dfff46, 0 },
{ 0xc5e8ccce, 0x0, 0xc5e8ccce, 0 },
{ 0x39ffdf3f, 0x0, 0x39ffdf3f, 0 },
{ 0x01f09ff6, 0x0, 0x01f09ff6, 0 },
{ 0xfddfdffe, 0x0, 0xfddfdffe, 0 },
{ 0xfffeffe0, 0x0, 0xfffeffe0, 0 },
{ 0x00000000, 0x0, 0x00000000, 0 },
};

22
drivers/clk/renesas/r8a7796-cpg-mssr.c
View File

@ -306,17 +306,17 @@ static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
static const struct mstp_stop_table r8a7796_mstp_table[] = {
{ 0x00200000, 0x0, 0x00200000, 0 },
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
{ 0x340E2FDC, 0x2040, 0x340E2FDC, 0 },
{ 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 },
{ 0x80000184, 0x180, 0x80000184, 0 },
{ 0xC3FFFFFF, 0x0, 0xC3FFFFFF, 0 },
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
{ 0x01F1FFF7, 0x0, 0x01F1FFF7, 0 },
{ 0xFFFFFFFE, 0x0, 0xFFFFFFFE, 0 },
{ 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
{ 0x000000B7, 0x0, 0x000000B7, 0 },
{ 0xd3e813a0, 0x0, 0xd3e813a0, 0 },
{ 0x040e2fdc, 0x2000, 0x040e2fdc, 0 },
{ 0xd00c7cdf, 0x400, 0xd00c7cdf, 0 },
{ 0x80000004, 0x180, 0x80000004, 0 },
{ 0x40dfff46, 0x0, 0x40dfff46, 0 },
{ 0x84ea888e, 0x0, 0x84ea888e, 0 },
{ 0x29df5e1c, 0x0, 0x29df5e1c, 0 },
{ 0x01c01ff7, 0x0, 0x01f01ff7, 0 },
{ 0xfddfdffe, 0x0, 0xfddfdffe, 0 },
{ 0xfffeffe0, 0x0, 0xfffeffe0, 0 },
{ 0x00000000, 0x0, 0x00000000, 0 },
};
static const void *r8a7796_get_pll_config(const u32 cpg_mode)

24
drivers/clk/renesas/r8a77965-cpg-mssr.c
View File

@ -303,18 +303,18 @@ static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
};
static const struct mstp_stop_table r8a77965_mstp_table[] = {
{ 0x00200000, 0x0, 0x00200000, 0 },
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
{ 0x340E2FDC, 0x2040, 0x340E2FDC, 0 },
{ 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 },
{ 0x80000184, 0x180, 0x80000184, 0 },
{ 0xC3FFFFFF, 0x0, 0xC3FFFFFF, 0 },
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
{ 0x01F1FFF7, 0x0, 0x01F1FFF7, 0 },
{ 0xFFFFFFFE, 0x0, 0xFFFFFFFE, 0 },
{ 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
{ 0x000000B7, 0x0, 0x000000B7, 0 },
{ 0x00210000, 0x0, 0x00210000, 0 },
{ 0xc3e813a0, 0x0, 0xc3e813a0, 0 },
{ 0x040e2fdc, 0x2000, 0x040e2fdc, 0 },
{ 0xd0cc7cdf, 0x400, 0xd0cc7cdf, 0 },
{ 0x80000004, 0x180, 0x80000004, 0 },
{ 0x40dfff46, 0x0, 0x40dfff46, 0 },
{ 0x84c8888c, 0x0, 0x84c8888c, 0 },
{ 0x29bf5d1c, 0x0, 0x29bf5d1c, 0 },
{ 0x00c09ff7, 0x0, 0x01c09ff7, 0 },
{ 0xfddfdffe, 0x0, 0xfddfdffe, 0 },
{ 0xfffeffe0, 0x0, 0xfffeffe0, 0 },
{ 0x00000000, 0x0, 0x00000000, 0 },
};
static const void *r8a77965_get_pll_config(const u32 cpg_mode)

22
drivers/clk/renesas/r8a77970-cpg-mssr.c
View File

@ -181,17 +181,17 @@ static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[8] = {
static const struct mstp_stop_table r8a77970_mstp_table[] = {
{ 0x00230000, 0x0, 0x00230000, 0 },
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
{ 0x14062FD8, 0x2040, 0x14062FD8, 0 },
{ 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 },
{ 0x80000184, 0x180, 0x80000184, 0 },
{ 0x83FFFFFF, 0x0, 0x83FFFFFF, 0 },
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
{ 0x7FF3FFF4, 0x0, 0x7FF3FFF4, 0 },
{ 0xFBF7FF97, 0x0, 0xFBF7FF97, 0 },
{ 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
{ 0x000000B7, 0x0, 0x000000B7, 0 },
{ 0x0be00000, 0x0, 0x0be00000, 0 },
{ 0x04062fd8, 0x2080, 0x04062fd8, 0 },
{ 0x00c0c0df, 0x0, 0x00c0c0df, 0 },
{ 0x80000004, 0x180, 0x80000004, 0 },
{ 0x00de0028, 0x0, 0x00de0028, 0 },
{ 0x00800008, 0x0, 0x00800008, 0 },
{ 0x09010000, 0x0, 0x09010000, 0 },
{ 0x7ff21f00, 0x0, 0x7ff21f00, 0 },
{ 0xf8025f84, 0x0, 0xf8025f84, 0 },
{ 0x00000000, 0x0, 0x00000000, 0 },
{ 0x00000000, 0x0, 0x00000000, 0 },
};
static const void *r8a77970_get_pll_config(const u32 cpg_mode)

24
drivers/clk/renesas/r8a77980-cpg-mssr.c
View File

@ -203,18 +203,18 @@ static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] = {
};
static const struct mstp_stop_table r8a77980_mstp_table[] = {
{ 0x00230000, 0x0, 0x00230000, 0 },
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
{ 0x14062FD8, 0x2040, 0x14062FD8, 0 },
{ 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 },
{ 0x80000184, 0x180, 0x80000184, 0 },
{ 0x83FFFFFF, 0x0, 0x83FFFFFF, 0 },
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
{ 0x7FF3FFF4, 0x0, 0x7FF3FFF4, 0 },
{ 0xFBF7FF97, 0x0, 0xFBF7FF97, 0 },
{ 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
{ 0x000000B7, 0x0, 0x000000B7, 0 },
{ 0x00230010, 0x0, 0x00230010, 0 },
{ 0x0be06c06, 0x0, 0x0be06c06, 0 },
{ 0x0006afd8, 0x2080, 0x0006afd8, 0 },
{ 0x00c8c0df, 0x0, 0x00c8c0df, 0 },
{ 0x80008004, 0x180, 0x80008004, 0 },
{ 0xbffe0021, 0x0, 0xbffe0021, 0 },
{ 0x1a841138, 0x0, 0x1a841138, 0 },
{ 0x090180c0, 0x0, 0x090180c0, 0 },
{ 0xfff27ff0, 0x0, 0xfff27ff0, 0 },
{ 0xf80a5f84, 0x0, 0xf80a5f84, 0 },
{ 0x0000001f, 0x0, 0x0000001f, 0 },
{ 0x00030000, 0x0, 0x00030000, 0 },
};
static const void *r8a77980_get_pll_config(const u32 cpg_mode)

24
drivers/clk/renesas/r8a77990-cpg-mssr.c
View File

@ -263,18 +263,18 @@ static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] = {
};
static const struct mstp_stop_table r8a77990_mstp_table[] = {
{ 0x00200000, 0x0, 0x00200000, 0 },
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
{ 0x340E2FDC, 0x2040, 0x340E2FDC, 0 },
{ 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 },
{ 0x80000184, 0x180, 0x80000184, 0 },
{ 0xC3FFFFFF, 0x0, 0xC3FFFFFF, 0 },
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
{ 0x01F1FFF7, 0x0, 0x01F1FFF7, 0 },
{ 0xFFFFFFFE, 0x0, 0xFFFFFFFE, 0 },
{ 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
{ 0x000000B7, 0x0, 0x000000B7, 0 },
{ 0x00210000, 0x0, 0x00210000, 0 },
{ 0xc3e81000, 0x0, 0xc3e81000, 0 },
{ 0x000e2fdc, 0x2000, 0x000e2fd8, 0 },
{ 0xd0c86cd7, 0x400, 0xd0c86cd7, 0 },
{ 0x80000004, 0x180, 0x80000004, 0 },
{ 0x40dfff44, 0x0, 0x40dfff44, 0 },
{ 0x84c8888c, 0x0, 0x84c8888c, 0 },
{ 0x09951c18, 0x0, 0x09951c18, 0 },
{ 0x008010c7, 0x0, 0x008010c7, 0 },
{ 0xfddfdfdc, 0x0, 0xfddfdfdc, 0 },
{ 0xfffeffe8, 0x0, 0xfffeffe8, 0 },
{ 0x00000000, 0x0, 0x00000000, 0 },
};
static const void *r8a77990_get_pll_config(const u32 cpg_mode)

24
drivers/clk/renesas/r8a77995-cpg-mssr.c
View File

@ -202,18 +202,18 @@ static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] = {
};
static const struct mstp_stop_table r8a77995_mstp_table[] = {
{ 0x00200000, 0x0, 0x00200000, 0 },
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
{ 0x340E2FDC, 0x2040, 0x340E2FDC, 0 },
{ 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 },
{ 0x80000184, 0x180, 0x80000184, 0 },
{ 0xC3FFFFFF, 0x0, 0xC3FFFFFF, 0 },
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
{ 0x01F1FFF7, 0x0, 0x01F1FFF7, 0 },
{ 0xFFFFFFFE, 0x0, 0xFFFFFFFE, 0 },
{ 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
{ 0x000000B7, 0x0, 0x000000B7, 0 },
{ 0x00210000, 0x0, 0x00210000, 0 },
{ 0x03e01000, 0x0, 0x03e01000, 0 },
{ 0x000e2fdc, 0x2000, 0x000e2fd8, 0 },
{ 0xc00014df, 0x400, 0xc00014df, 0 },
{ 0x80000004, 0x180, 0x80000004, 0 },
{ 0x40d20004, 0x0, 0x40d20004, 0 },
{ 0x08c0008c, 0x0, 0x08c0008c, 0 },
{ 0x09941c18, 0x0, 0x09941c18, 0 },
{ 0x00801087, 0x0, 0x00801087, 0 },
{ 0xf143dfc0, 0x0, 0xf143dfc0, 0 },
{ 0x063e1820, 0x0, 0x063e1820, 0 },
{ 0x00000000, 0x0, 0x00000000, 0 },
};
static const void *r8a77995_get_pll_config(const u32 cpg_mode)