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ARM: OMAP4470: Add voltage and dpll data
OMAP4470 reference design uses TWL6032 PMIC with a following connection scheme: VDD_CORE = TWL6032 SMPS2 VDD_MPU = TWL6032 SMPS1 VDD_IVA = TWL6032 SMPS5 Set voltage and frequency values according to OMAP4470 Data Manual Operating Condition Addendum v0.7 Signed-off-by: Taras Kondratiuk <taras@ti.com>
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@ -50,6 +50,7 @@ static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
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/*
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/*
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* dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
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* dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
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* OMAP4430 OPP_TURBO frequency
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* OMAP4430 OPP_TURBO frequency
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* OMAP4470 OPP_NOM frequency
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*/
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*/
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static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
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static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
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{200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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@ -76,6 +77,7 @@ static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
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};
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};
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/* OMAP4460 OPP_NOM frequency */
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/* OMAP4460 OPP_NOM frequency */
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/* OMAP4470 OPP_NOM (Low Power) frequency */
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static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
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static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
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{200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
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{200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
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{800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
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{800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
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@ -198,6 +200,20 @@ struct dplls omap4460_dplls = {
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.ddr = NULL
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.ddr = NULL
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};
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};
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struct dplls omap4470_dplls = {
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.mpu = mpu_dpll_params_1600mhz,
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.core = core_dpll_params_1600mhz,
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.per = per_dpll_params_1536mhz,
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.iva = iva_dpll_params_1862mhz,
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#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
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.abe = abe_dpll_params_sysclk_196608khz,
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#else
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.abe = &abe_dpll_params_32k_196608khz,
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#endif
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.usb = usb_dpll_params_1920mhz,
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.ddr = NULL
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};
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struct pmic_data twl6030_4430es1 = {
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struct pmic_data twl6030_4430es1 = {
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.base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV,
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.base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV,
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.step = 12660, /* 12.66 mV represented in uV */
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.step = 12660, /* 12.66 mV represented in uV */
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@ -208,6 +224,7 @@ struct pmic_data twl6030_4430es1 = {
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.pmic_write = omap_vc_bypass_send_value,
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.pmic_write = omap_vc_bypass_send_value,
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};
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};
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/* twl6030 struct is used for TWL6030 and TWL6032 PMIC */
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struct pmic_data twl6030 = {
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struct pmic_data twl6030 = {
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.base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV,
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.base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV,
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.step = 12660, /* 12.66 mV represented in uV */
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.step = 12660, /* 12.66 mV represented in uV */
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@ -271,6 +288,20 @@ struct vcores_data omap4460_volts = {
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.mm.pmic = &twl6030,
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.mm.pmic = &twl6030,
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};
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};
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struct vcores_data omap4470_volts = {
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.mpu.value = 1200,
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.mpu.addr = SMPS_REG_ADDR_SMPS1,
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.mpu.pmic = &twl6030,
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.core.value = 1126,
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.core.addr = SMPS_REG_ADDR_SMPS1,
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.core.pmic = &twl6030,
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.mm.value = 1137,
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.mm.addr = SMPS_REG_ADDR_SMPS1,
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.mm.pmic = &twl6030,
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};
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/*
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/*
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* Enable essential clock domains, modules and
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* Enable essential clock domains, modules and
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* do some additional special settings needed
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* do some additional special settings needed
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@ -476,6 +507,11 @@ void hw_data_init(void)
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*omap_vcores = &omap4460_volts;
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*omap_vcores = &omap4460_volts;
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break;
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break;
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case OMAP4470_ES1_0:
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*dplls_data = &omap4470_dplls;
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*omap_vcores = &omap4470_volts;
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break;
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default:
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default:
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printf("\n INVALID OMAP REVISION ");
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printf("\n INVALID OMAP REVISION ");
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}
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}
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@ -149,11 +149,16 @@
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/* PRM_VC_VAL_BYPASS */
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/* PRM_VC_VAL_BYPASS */
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#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400
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#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400
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/* SMPS */
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/* PMIC */
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#define SMPS_I2C_SLAVE_ADDR 0x12
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#define SMPS_I2C_SLAVE_ADDR 0x12
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/* TWL6030 SMPS */
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#define SMPS_REG_ADDR_VCORE1 0x55
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#define SMPS_REG_ADDR_VCORE1 0x55
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#define SMPS_REG_ADDR_VCORE2 0x5B
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#define SMPS_REG_ADDR_VCORE2 0x5B
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#define SMPS_REG_ADDR_VCORE3 0x61
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#define SMPS_REG_ADDR_VCORE3 0x61
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/* TWL6032 SMPS */
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#define SMPS_REG_ADDR_SMPS1 0x55
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#define SMPS_REG_ADDR_SMPS2 0x5B
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#define SMPS_REG_ADDR_SMPS5 0x49
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#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700
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#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700
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#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000
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#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000
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