mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-30 16:40:44 +09:00
imx8mp: Disables use of MR4 TUF flag (MR4[7]) bit
In uMCTL2 Databook, for LPDDR4, it is recommended to set this register to 1. This can avoid ddr bandwidth is lower after booting with running for a while. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jian Li <jian.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
parent
5865d14dde
commit
3f63d27c17
@ -11,7 +11,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
|
||||
{ 0x3d400304, 0x1 },
|
||||
{ 0x3d400030, 0x1 },
|
||||
{ 0x3d400000, 0xa3080020 },
|
||||
{ 0x3d400020, 0x323 },
|
||||
{ 0x3d400020, 0x1323 },
|
||||
{ 0x3d400024, 0x1e84800 },
|
||||
{ 0x3d400064, 0x7a0118 },
|
||||
{ 0x3d4000d0, 0xc00307a3 },
|
||||
|
Loading…
Reference in New Issue
Block a user