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https://github.com/brain-hackers/u-boot-brain
synced 2024-09-29 08:00:26 +09:00
vf610: refactor DDRMC code
The VF610 DDRMC driver code contains settings which are board-specific. Move these out to boards so that new boards can define their own without having to modify the driver. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
This commit is contained in:
parent
b9a1609915
commit
3f353ceccb
@ -12,9 +12,9 @@
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#include <asm/arch/iomux-vf610.h>
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#include <asm/arch/ddrmc-vf610.h>
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void ddrmc_setup_iomux(void)
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void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count)
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{
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static const iomux_v3_cfg_t ddr_pads[] = {
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static const iomux_v3_cfg_t default_pads[] = {
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VF610_PAD_DDR_A15__DDR_A_15,
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VF610_PAD_DDR_A14__DDR_A_14,
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VF610_PAD_DDR_A13__DDR_A_13,
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@ -65,76 +65,54 @@ void ddrmc_setup_iomux(void)
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VF610_PAD_DDR_RESETB,
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};
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imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
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if ((pads == NULL) || (pads_count == 0)) {
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pads = default_pads;
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pads_count = ARRAY_SIZE(default_pads);
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}
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imx_iomux_v3_setup_multiple_pads(pads, pads_count);
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}
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void ddrmc_phy_init(void)
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{
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struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
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static struct ddrmc_phy_setting default_phy_settings[] = {
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{ DDRMC_PHY_DQ_TIMING, 0 },
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{ DDRMC_PHY_DQ_TIMING, 16 },
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{ DDRMC_PHY_DQ_TIMING, 32 },
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writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[0]);
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writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[16]);
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writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[32]);
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{ DDRMC_PHY_DQS_TIMING, 1 },
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{ DDRMC_PHY_DQS_TIMING, 17 },
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writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[1]);
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writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[17]);
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{ DDRMC_PHY_CTRL, 2 },
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{ DDRMC_PHY_CTRL, 18 },
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{ DDRMC_PHY_CTRL, 34 },
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writel(DDRMC_PHY_CTRL, &ddrmr->phy[2]);
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writel(DDRMC_PHY_CTRL, &ddrmr->phy[18]);
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writel(DDRMC_PHY_CTRL, &ddrmr->phy[34]);
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{ DDRMC_PHY_MASTER_CTRL, 3 },
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{ DDRMC_PHY_MASTER_CTRL, 19 },
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{ DDRMC_PHY_MASTER_CTRL, 35 },
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writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[3]);
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writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[19]);
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writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[35]);
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writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[4]);
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writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[20]);
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writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[36]);
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{ DDRMC_PHY_SLAVE_CTRL, 4 },
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{ DDRMC_PHY_SLAVE_CTRL, 20 },
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{ DDRMC_PHY_SLAVE_CTRL, 36 },
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/* LPDDR2 only parameter */
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writel(DDRMC_PHY_OFF, &ddrmr->phy[49]);
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{ DDRMC_PHY_OFF, 49 },
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writel(DDRMC_PHY50_DDR3_MODE |
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DDRMC_PHY50_EN_SW_HALF_CYCLE, &ddrmr->phy[50]);
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{ DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, 50 },
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/* Processor Pad ODT settings */
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writel(DDRMC_PHY_PROC_PAD_ODT, &ddrmr->phy[52]);
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}
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{ DDRMC_PHY_PROC_PAD_ODT, 52 },
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static void ddrmc_ctrl_lvl_init(struct ddrmc_lvl_info *lvl)
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{
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struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
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u32 cr102 = 0, cr105 = 0, cr106 = 0, cr110 = 0;
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if (lvl->wrlvl_reg_en) {
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writel(DDRMC_CR97_WRLVL_EN, &ddrmr->cr[97]);
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writel(DDRMC_CR98_WRLVL_DL_0(lvl->wrlvl_dl_0), &ddrmr->cr[98]);
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writel(DDRMC_CR99_WRLVL_DL_1(lvl->wrlvl_dl_1), &ddrmr->cr[99]);
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}
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if (lvl->rdlvl_reg_en) {
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cr102 |= DDRMC_CR102_RDLVL_REG_EN;
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cr105 |= DDRMC_CR105_RDLVL_DL_0(lvl->rdlvl_dl_0);
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cr110 |= DDRMC_CR110_RDLVL_DL_1(lvl->rdlvl_dl_1);
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}
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if (lvl->rdlvl_gt_reg_en) {
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cr102 |= DDRMC_CR102_RDLVL_GT_REGEN;
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cr106 |= DDRMC_CR106_RDLVL_GTDL_0(lvl->rdlvl_gt_dl_0);
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cr110 |= DDRMC_CR110_RDLVL_GTDL_1(lvl->rdlvl_gt_dl_1);
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}
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writel(cr102, &ddrmr->cr[102]);
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writel(cr105, &ddrmr->cr[105]);
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writel(cr106, &ddrmr->cr[106]);
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writel(cr110, &ddrmr->cr[110]);
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}
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/* end marker */
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{ 0, -1 }
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};
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void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
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struct ddrmc_lvl_info *lvl,
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int col_diff, int row_diff)
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struct ddrmc_cr_setting *board_cr_settings,
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struct ddrmc_phy_setting *board_phy_settings,
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int col_diff, int row_diff)
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{
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struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
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struct ddrmc_cr_setting *cr_setting;
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struct ddrmc_phy_setting *phy_setting;
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writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]);
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writel(DDRMC_CR02_DRAM_TINIT(timings->tinit), &ddrmr->cr[2]);
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@ -144,7 +122,9 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
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writel(DDRMC_CR12_WRLAT(timings->wrlat) |
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DDRMC_CR12_CASLAT_LIN(timings->caslat_lin), &ddrmr->cr[12]);
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writel(DDRMC_CR13_TRC(timings->trc) | DDRMC_CR13_TRRD(timings->trrd) |
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DDRMC_CR13_TCCD(timings->tccd), &ddrmr->cr[13]);
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DDRMC_CR13_TCCD(timings->tccd) |
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DDRMC_CR13_TBST_INT_INTERVAL(timings->tbst_int_interval),
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&ddrmr->cr[13]);
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writel(DDRMC_CR14_TFAW(timings->tfaw) | DDRMC_CR14_TRP(timings->trp) |
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DDRMC_CR14_TWTR(timings->twtr) |
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DDRMC_CR14_TRAS_MIN(timings->tras_min), &ddrmr->cr[14]);
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@ -156,18 +136,19 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
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DDRMC_CR18_TCKE(timings->tcke), &ddrmr->cr[18]);
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writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]);
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writel(DDRMC_CR21_TRCD_INT(timings->trcd_int) |
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DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]);
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writel(DDRMC_CR21_TRCD_INT(timings->trcd_int) | DDRMC_CR21_CCMAP_EN |
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DDRMC_CR21_TRAS_LOCKOUT(timings->tras_lockout),
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&ddrmr->cr[21]);
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writel(DDRMC_CR22_TDAL(timings->tdal), &ddrmr->cr[22]);
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writel(DDRMC_CR23_BSTLEN(3) |
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writel(DDRMC_CR23_BSTLEN(timings->bstlen) |
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DDRMC_CR23_TDLL(timings->tdll), &ddrmr->cr[23]);
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writel(DDRMC_CR24_TRP_AB(timings->trp_ab), &ddrmr->cr[24]);
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writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]);
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writel(DDRMC_CR26_TREF(timings->tref) |
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DDRMC_CR26_TRFC(timings->trfc), &ddrmr->cr[26]);
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writel(DDRMC_CR28_TREF_INT(0), &ddrmr->cr[28]);
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writel(DDRMC_CR28_TREF_INT(timings->tref_int), &ddrmr->cr[28]);
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writel(DDRMC_CR29_TPDEX(timings->tpdex), &ddrmr->cr[29]);
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writel(DDRMC_CR30_TXPDLL(timings->txpdll), &ddrmr->cr[30]);
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@ -177,7 +158,7 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
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writel(DDRMC_CR34_CKSRX(timings->cksrx) |
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DDRMC_CR34_CKSRE(timings->cksre), &ddrmr->cr[34]);
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writel(DDRMC_CR38_FREQ_CHG_EN(0), &ddrmr->cr[38]);
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writel(DDRMC_CR38_FREQ_CHG_EN(timings->freq_chg_en), &ddrmr->cr[38]);
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writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) |
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DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]);
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@ -191,13 +172,14 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
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writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]);
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writel(DDRMC_CR70_REF_PER_ZQ(timings->ref_per_zq), &ddrmr->cr[70]);
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writel(DDRMC_CR72_ZQCS_ROTATE(0), &ddrmr->cr[72]);
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writel(DDRMC_CR72_ZQCS_ROTATE(timings->zqcs_rotate), &ddrmr->cr[72]);
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writel(DDRMC_CR73_APREBIT(timings->aprebit) |
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DDRMC_CR73_COL_DIFF(col_diff) |
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DDRMC_CR73_ROW_DIFF(row_diff), &ddrmr->cr[73]);
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writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN |
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DDRMC_CR74_CMD_AGE_CNT(64) | DDRMC_CR74_AGE_CNT(64),
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DDRMC_CR74_CMD_AGE_CNT(timings->cmd_age_cnt) |
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DDRMC_CR74_AGE_CNT(timings->age_cnt),
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&ddrmr->cr[74]);
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writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN |
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DDRMC_CR75_PLEN, &ddrmr->cr[75]);
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@ -205,13 +187,15 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
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DDRMC_CR76_W2R_SPLT_EN, &ddrmr->cr[76]);
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writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE |
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DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]);
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writel(DDRMC_CR78_Q_FULLNESS(7) |
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writel(DDRMC_CR78_Q_FULLNESS(timings->q_fullness) |
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DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]);
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writel(DDRMC_CR79_CTLUPD_AREF(0), &ddrmr->cr[79]);
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writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);
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writel(DDRMC_CR87_ODT_WR_MAPCS0, &ddrmr->cr[87]);
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writel(DDRMC_CR87_ODT_RD_MAPCS0(timings->odt_rd_mapcs0) |
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DDRMC_CR87_ODT_WR_MAPCS0(timings->odt_wr_mapcs0),
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&ddrmr->cr[87]);
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writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]);
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writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]);
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@ -219,58 +203,33 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
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writel(DDRMC_CR96_WLMRD(timings->wlmrd) |
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DDRMC_CR96_WLDQSEN(timings->wldqsen), &ddrmr->cr[96]);
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if (lvl != NULL)
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ddrmc_ctrl_lvl_init(lvl);
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/* execute custom CR setting sequence (may be NULL) */
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cr_setting = board_cr_settings;
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if (cr_setting != NULL)
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while (cr_setting->cr_rnum >= 0) {
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writel(cr_setting->setting,
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&ddrmr->cr[cr_setting->cr_rnum]);
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cr_setting++;
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}
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writel(DDRMC_CR117_AXI0_W_PRI(0) |
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DDRMC_CR117_AXI0_R_PRI(0), &ddrmr->cr[117]);
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writel(DDRMC_CR118_AXI1_W_PRI(1) |
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DDRMC_CR118_AXI1_R_PRI(1), &ddrmr->cr[118]);
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/* perform default PHY settings (may be overriden by custom settings */
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phy_setting = default_phy_settings;
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while (phy_setting->phy_rnum >= 0) {
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writel(phy_setting->setting,
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&ddrmr->phy[phy_setting->phy_rnum]);
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phy_setting++;
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}
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writel(DDRMC_CR120_AXI0_PRI1_RPRI(2) |
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DDRMC_CR120_AXI0_PRI0_RPRI(2), &ddrmr->cr[120]);
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writel(DDRMC_CR121_AXI0_PRI3_RPRI(2) |
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DDRMC_CR121_AXI0_PRI2_RPRI(2), &ddrmr->cr[121]);
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writel(DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
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DDRMC_CR122_AXI0_PRIRLX(100), &ddrmr->cr[122]);
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writel(DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
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DDRMC_CR123_AXI1_PRI2_RPRI(1), &ddrmr->cr[123]);
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writel(DDRMC_CR124_AXI1_PRIRLX(100), &ddrmr->cr[124]);
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writel(DDRMC_CR126_PHY_RDLAT(8), &ddrmr->cr[126]);
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writel(DDRMC_CR132_WRLAT_ADJ(5) |
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DDRMC_CR132_RDLAT_ADJ(6), &ddrmr->cr[132]);
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writel(DDRMC_CR137_PHYCTL_DL(2), &ddrmr->cr[137]);
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writel(DDRMC_CR138_PHY_WRLV_MXDL(256) |
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DDRMC_CR138_PHYDRAM_CK_EN(1), &ddrmr->cr[138]);
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writel(DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
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DDRMC_CR139_PHY_WRLV_DLL(3) |
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DDRMC_CR139_PHY_WRLV_EN(3), &ddrmr->cr[139]);
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writel(DDRMC_CR140_PHY_WRLV_WW(64), &ddrmr->cr[140]);
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writel(DDRMC_CR143_RDLV_GAT_MXDL(1536) |
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DDRMC_CR143_RDLV_MXDL(128), &ddrmr->cr[143]);
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writel(DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
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DDRMC_CR144_PHY_RDLV_DLL(3) |
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DDRMC_CR144_PHY_RDLV_EN(3), &ddrmr->cr[144]);
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writel(DDRMC_CR145_PHY_RDLV_RR(64), &ddrmr->cr[145]);
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writel(DDRMC_CR146_PHY_RDLVL_RESP(64), &ddrmr->cr[146]);
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writel(DDRMC_CR147_RDLV_RESP_MASK(983040), &ddrmr->cr[147]);
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writel(DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), &ddrmr->cr[148]);
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writel(DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
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DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), &ddrmr->cr[151]);
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writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
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DDRMC_CR154_PAD_ZQ_MODE(1) |
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DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
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DDRMC_CR154_PAD_ZQ_HW_FOR(1), &ddrmr->cr[154]);
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writel(DDRMC_CR155_PAD_ODT_BYTE1(2) |
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DDRMC_CR155_PAD_ODT_BYTE0(2), &ddrmr->cr[155]);
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writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]);
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writel(DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
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DDRMC_CR161_TODTH_WR(2), &ddrmr->cr[161]);
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ddrmc_phy_init();
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/* execute custom PHY setting sequence (may be NULL) */
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phy_setting = board_phy_settings;
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if (phy_setting != NULL)
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while (phy_setting->phy_rnum >= 0) {
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writel(phy_setting->setting,
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&ddrmr->phy[phy_setting->phy_rnum]);
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phy_setting++;
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}
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/* all inits done, start the DDR controller */
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writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]);
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while (!(readl(&ddrmr->cr[80]) && 0x100))
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@ -11,18 +11,6 @@
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#ifndef __ASM_ARCH_VF610_DDRMC_H
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#define __ASM_ARCH_VF610_DDRMC_H
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struct ddrmc_lvl_info {
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u16 wrlvl_reg_en;
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u16 wrlvl_dl_0;
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u16 wrlvl_dl_1;
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u16 rdlvl_gt_reg_en;
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u16 rdlvl_gt_dl_0;
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u16 rdlvl_gt_dl_1;
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u16 rdlvl_reg_en;
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u16 rdlvl_dl_0;
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u16 rdlvl_dl_1;
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};
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struct ddr3_jedec_timings {
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u8 tinit;
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u32 trst_pwron;
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@ -32,6 +20,7 @@ struct ddr3_jedec_timings {
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u8 trc;
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u8 trrd;
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u8 tccd;
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u8 tbst_int_interval;
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u8 tfaw;
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u8 trp;
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u8 twtr;
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@ -43,30 +32,51 @@ struct ddr3_jedec_timings {
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u8 tckesr;
|
||||
u8 tcke;
|
||||
u8 trcd_int;
|
||||
u8 tras_lockout;
|
||||
u8 tdal;
|
||||
u8 bstlen;
|
||||
u16 tdll;
|
||||
u8 trp_ab;
|
||||
u16 tref;
|
||||
u8 trfc;
|
||||
u16 tref_int;
|
||||
u8 tpdex;
|
||||
u8 txpdll;
|
||||
u8 txsnr;
|
||||
u16 txsr;
|
||||
u8 cksrx;
|
||||
u8 cksre;
|
||||
u8 freq_chg_en;
|
||||
u16 zqcl;
|
||||
u16 zqinit;
|
||||
u8 zqcs;
|
||||
u8 ref_per_zq;
|
||||
u8 zqcs_rotate;
|
||||
u8 aprebit;
|
||||
u8 cmd_age_cnt;
|
||||
u8 age_cnt;
|
||||
u8 q_fullness;
|
||||
u8 odt_rd_mapcs0;
|
||||
u8 odt_wr_mapcs0;
|
||||
u8 wlmrd;
|
||||
u8 wldqsen;
|
||||
};
|
||||
|
||||
void ddrmc_setup_iomux(void);
|
||||
struct ddrmc_cr_setting {
|
||||
u32 setting;
|
||||
int cr_rnum; /* CR register ; -1 for last entry */
|
||||
};
|
||||
|
||||
struct ddrmc_phy_setting {
|
||||
u32 setting;
|
||||
int phy_rnum; /* PHY register ; -1 for last entry */
|
||||
};
|
||||
|
||||
void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count);
|
||||
void ddrmc_phy_init(void);
|
||||
void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
|
||||
struct ddrmc_lvl_info *lvl,
|
||||
int col_diff, int row_diff);
|
||||
struct ddrmc_cr_setting *board_cr_settings,
|
||||
struct ddrmc_phy_setting *board_phy_settings,
|
||||
int col_diff, int row_diff);
|
||||
|
||||
#endif
|
||||
|
@ -148,7 +148,7 @@
|
||||
#define DDRMC_CR18_TCKE(v) ((v) & 0x7)
|
||||
#define DDRMC_CR20_AP_EN (1 << 24)
|
||||
#define DDRMC_CR21_TRCD_INT(v) (((v) & 0xff) << 16)
|
||||
#define DDRMC_CR21_TRAS_LOCKOUT (1 << 8)
|
||||
#define DDRMC_CR21_TRAS_LOCKOUT(v) ((v) << 8)
|
||||
#define DDRMC_CR21_CCMAP_EN 1
|
||||
#define DDRMC_CR22_TDAL(v) (((v) & 0x3f) << 16)
|
||||
#define DDRMC_CR23_BSTLEN(v) (((v) & 0x7) << 24)
|
||||
@ -200,8 +200,8 @@
|
||||
#define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) & 0xf)
|
||||
#define DDRMC_CR79_CTLUPD_AREF(v) (((v) & 0x1) << 24)
|
||||
#define DDRMC_CR82_INT_MASK 0x10000000
|
||||
#define DDRMC_CR87_ODT_WR_MAPCS0 (1 << 24)
|
||||
#define DDRMC_CR87_ODT_RD_MAPCS0 (1 << 16)
|
||||
#define DDRMC_CR87_ODT_WR_MAPCS0(v) ((v) << 24)
|
||||
#define DDRMC_CR87_ODT_RD_MAPCS0(v) ((v) << 16)
|
||||
#define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) << 16)
|
||||
#define DDRMC_CR89_AODT_RWSMCS(v) ((v) & 0xf)
|
||||
#define DDRMC_CR91_R2W_SMCSDL(v) (((v) & 0x7) << 16)
|
||||
|
@ -28,63 +28,117 @@ DECLARE_GLOBAL_DATA_PTR;
|
||||
#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
|
||||
PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
|
||||
|
||||
static struct ddrmc_cr_setting vf610twr_cr_settings[] = {
|
||||
/* levelling */
|
||||
{ DDRMC_CR97_WRLVL_EN, 97 },
|
||||
{ DDRMC_CR98_WRLVL_DL_0(0), 98 },
|
||||
{ DDRMC_CR99_WRLVL_DL_1(0), 99 },
|
||||
{ DDRMC_CR102_RDLVL_REG_EN | DDRMC_CR102_RDLVL_GT_REGEN, 102 },
|
||||
{ DDRMC_CR105_RDLVL_DL_0(0), 105 },
|
||||
{ DDRMC_CR106_RDLVL_GTDL_0(4), 106 },
|
||||
{ DDRMC_CR110_RDLVL_DL_1(0) | DDRMC_CR110_RDLVL_GTDL_1(4), 110 },
|
||||
/* AXI */
|
||||
{ DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 },
|
||||
{ DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
|
||||
{ DDRMC_CR120_AXI0_PRI1_RPRI(2) |
|
||||
DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
|
||||
{ DDRMC_CR121_AXI0_PRI3_RPRI(2) |
|
||||
DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
|
||||
{ DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
|
||||
DDRMC_CR122_AXI0_PRIRLX(100), 122 },
|
||||
{ DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
|
||||
DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 },
|
||||
{ DDRMC_CR124_AXI1_PRIRLX(100), 124 },
|
||||
{ DDRMC_CR126_PHY_RDLAT(8), 126 },
|
||||
{ DDRMC_CR132_WRLAT_ADJ(5) |
|
||||
DDRMC_CR132_RDLAT_ADJ(6), 132 },
|
||||
{ DDRMC_CR137_PHYCTL_DL(2), 137 },
|
||||
{ DDRMC_CR138_PHY_WRLV_MXDL(256) |
|
||||
DDRMC_CR138_PHYDRAM_CK_EN(1), 138 },
|
||||
{ DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
|
||||
DDRMC_CR139_PHY_WRLV_DLL(3) |
|
||||
DDRMC_CR139_PHY_WRLV_EN(3), 139 },
|
||||
{ DDRMC_CR140_PHY_WRLV_WW(64), 140 },
|
||||
{ DDRMC_CR143_RDLV_GAT_MXDL(1536) |
|
||||
DDRMC_CR143_RDLV_MXDL(128), 143 },
|
||||
{ DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
|
||||
DDRMC_CR144_PHY_RDLV_DLL(3) |
|
||||
DDRMC_CR144_PHY_RDLV_EN(3), 144 },
|
||||
{ DDRMC_CR145_PHY_RDLV_RR(64), 145 },
|
||||
{ DDRMC_CR146_PHY_RDLVL_RESP(64), 146 },
|
||||
{ DDRMC_CR147_RDLV_RESP_MASK(983040), 147 },
|
||||
{ DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), 148 },
|
||||
{ DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
|
||||
DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), 151 },
|
||||
|
||||
{ DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
|
||||
DDRMC_CR154_PAD_ZQ_MODE(1) |
|
||||
DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
|
||||
DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 },
|
||||
{ DDRMC_CR155_PAD_ODT_BYTE1(1) | DDRMC_CR155_PAD_ODT_BYTE0(1), 155 },
|
||||
{ DDRMC_CR158_TWR(6), 158 },
|
||||
{ DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
|
||||
DDRMC_CR161_TODTH_WR(2), 161 },
|
||||
/* end marker */
|
||||
{ 0, -1 }
|
||||
};
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
struct ddrmc_lvl_info lvl = {
|
||||
.wrlvl_reg_en = 1,
|
||||
.wrlvl_dl_0 = 0,
|
||||
.wrlvl_dl_1 = 0,
|
||||
.rdlvl_gt_reg_en = 1,
|
||||
.rdlvl_gt_dl_0 = 4,
|
||||
.rdlvl_gt_dl_1 = 4,
|
||||
.rdlvl_reg_en = 1,
|
||||
.rdlvl_dl_0 = 0,
|
||||
.rdlvl_dl_1 = 0,
|
||||
};
|
||||
|
||||
static const struct ddr3_jedec_timings timings = {
|
||||
.tinit = 5,
|
||||
.trst_pwron = 80000,
|
||||
.cke_inactive = 200000,
|
||||
.wrlat = 5,
|
||||
.caslat_lin = 12,
|
||||
.trc = 21,
|
||||
.trrd = 4,
|
||||
.tccd = 4,
|
||||
.tfaw = 20,
|
||||
.trp = 6,
|
||||
.twtr = 4,
|
||||
.tras_min = 15,
|
||||
.tmrd = 4,
|
||||
.trtp = 4,
|
||||
.tras_max = 28080,
|
||||
.tmod = 12,
|
||||
.tckesr = 4,
|
||||
.tcke = 3,
|
||||
.trcd_int = 6,
|
||||
.tdal = 12,
|
||||
.tdll = 512,
|
||||
.trp_ab = 6,
|
||||
.tref = 3120,
|
||||
.trfc = 44,
|
||||
.tpdex = 3,
|
||||
.txpdll = 10,
|
||||
.txsnr = 48,
|
||||
.txsr = 468,
|
||||
.cksrx = 5,
|
||||
.cksre = 5,
|
||||
.zqcl = 256,
|
||||
.zqinit = 512,
|
||||
.zqcs = 64,
|
||||
.ref_per_zq = 64,
|
||||
.aprebit = 10,
|
||||
.wlmrd = 40,
|
||||
.wldqsen = 25,
|
||||
.tinit = 5,
|
||||
.trst_pwron = 80000,
|
||||
.cke_inactive = 200000,
|
||||
.wrlat = 5,
|
||||
.caslat_lin = 12,
|
||||
.trc = 21,
|
||||
.trrd = 4,
|
||||
.tccd = 4,
|
||||
.tbst_int_interval = 0,
|
||||
.tfaw = 20,
|
||||
.trp = 6,
|
||||
.twtr = 4,
|
||||
.tras_min = 15,
|
||||
.tmrd = 4,
|
||||
.trtp = 4,
|
||||
.tras_max = 28080,
|
||||
.tmod = 12,
|
||||
.tckesr = 4,
|
||||
.tcke = 3,
|
||||
.trcd_int = 6,
|
||||
.tras_lockout = 0,
|
||||
.tdal = 12,
|
||||
.bstlen = 0,
|
||||
.tdll = 512,
|
||||
.trp_ab = 6,
|
||||
.tref = 3120,
|
||||
.trfc = 44,
|
||||
.tref_int = 0,
|
||||
.tpdex = 3,
|
||||
.txpdll = 10,
|
||||
.txsnr = 48,
|
||||
.txsr = 468,
|
||||
.cksrx = 5,
|
||||
.cksre = 5,
|
||||
.freq_chg_en = 0,
|
||||
.zqcl = 256,
|
||||
.zqinit = 512,
|
||||
.zqcs = 64,
|
||||
.ref_per_zq = 64,
|
||||
.zqcs_rotate = 0,
|
||||
.aprebit = 10,
|
||||
.cmd_age_cnt = 64,
|
||||
.age_cnt = 64,
|
||||
.q_fullness = 7,
|
||||
.odt_rd_mapcs0 = 0,
|
||||
.odt_wr_mapcs0 = 1,
|
||||
.wlmrd = 40,
|
||||
.wldqsen = 25,
|
||||
};
|
||||
|
||||
ddrmc_setup_iomux();
|
||||
ddrmc_setup_iomux(NULL, 0);
|
||||
|
||||
ddrmc_ctrl_init_ddr3(&timings, &lvl, 1, 3);
|
||||
ddrmc_ctrl_init_ddr3(&timings, vf610twr_cr_settings, NULL, 1, 3);
|
||||
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
|
||||
|
||||
return 0;
|
||||
|
@ -35,6 +35,61 @@ DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define USB_PEN_GPIO 83
|
||||
|
||||
static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
|
||||
/* levelling */
|
||||
{ DDRMC_CR97_WRLVL_EN, 97 },
|
||||
{ DDRMC_CR98_WRLVL_DL_0(0), 98 },
|
||||
{ DDRMC_CR99_WRLVL_DL_1(0), 99 },
|
||||
{ DDRMC_CR102_RDLVL_REG_EN | DDRMC_CR102_RDLVL_GT_REGEN, 102 },
|
||||
{ DDRMC_CR105_RDLVL_DL_0(0), 105 },
|
||||
{ DDRMC_CR106_RDLVL_GTDL_0(4), 106 },
|
||||
{ DDRMC_CR110_RDLVL_DL_1(0) | DDRMC_CR110_RDLVL_GTDL_1(4), 110 },
|
||||
/* AXI */
|
||||
{ DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 },
|
||||
{ DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
|
||||
{ DDRMC_CR120_AXI0_PRI1_RPRI(2) |
|
||||
DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
|
||||
{ DDRMC_CR121_AXI0_PRI3_RPRI(2) |
|
||||
DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
|
||||
{ DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
|
||||
DDRMC_CR122_AXI0_PRIRLX(100), 122 },
|
||||
{ DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
|
||||
DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 },
|
||||
{ DDRMC_CR124_AXI1_PRIRLX(100), 124 },
|
||||
{ DDRMC_CR126_PHY_RDLAT(8), 126 },
|
||||
{ DDRMC_CR132_WRLAT_ADJ(5) |
|
||||
DDRMC_CR132_RDLAT_ADJ(6), 132 },
|
||||
{ DDRMC_CR137_PHYCTL_DL(2), 137 },
|
||||
{ DDRMC_CR138_PHY_WRLV_MXDL(256) |
|
||||
DDRMC_CR138_PHYDRAM_CK_EN(1), 138 },
|
||||
{ DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
|
||||
DDRMC_CR139_PHY_WRLV_DLL(3) |
|
||||
DDRMC_CR139_PHY_WRLV_EN(3), 139 },
|
||||
{ DDRMC_CR140_PHY_WRLV_WW(64), 140 },
|
||||
{ DDRMC_CR143_RDLV_GAT_MXDL(1536) |
|
||||
DDRMC_CR143_RDLV_MXDL(128), 143 },
|
||||
{ DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
|
||||
DDRMC_CR144_PHY_RDLV_DLL(3) |
|
||||
DDRMC_CR144_PHY_RDLV_EN(3), 144 },
|
||||
{ DDRMC_CR145_PHY_RDLV_RR(64), 145 },
|
||||
{ DDRMC_CR146_PHY_RDLVL_RESP(64), 146 },
|
||||
{ DDRMC_CR147_RDLV_RESP_MASK(983040), 147 },
|
||||
{ DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), 148 },
|
||||
{ DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
|
||||
DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), 151 },
|
||||
|
||||
{ DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
|
||||
DDRMC_CR154_PAD_ZQ_MODE(1) |
|
||||
DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
|
||||
DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 },
|
||||
{ DDRMC_CR155_PAD_ODT_BYTE1(1) | DDRMC_CR155_PAD_ODT_BYTE0(1), 155 },
|
||||
{ DDRMC_CR158_TWR(6), 158 },
|
||||
{ DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
|
||||
DDRMC_CR161_TODTH_WR(2), 161 },
|
||||
/* end marker */
|
||||
{ 0, -1 }
|
||||
};
|
||||
|
||||
static const iomux_v3_cfg_t usb_pads[] = {
|
||||
VF610_PAD_PTD4__GPIO_83,
|
||||
};
|
||||
@ -42,48 +97,59 @@ static const iomux_v3_cfg_t usb_pads[] = {
|
||||
int dram_init(void)
|
||||
{
|
||||
static const struct ddr3_jedec_timings timings = {
|
||||
.tinit = 5,
|
||||
.trst_pwron = 80000,
|
||||
.cke_inactive = 200000,
|
||||
.wrlat = 5,
|
||||
.caslat_lin = 12,
|
||||
.trc = 21,
|
||||
.trrd = 4,
|
||||
.tccd = 4,
|
||||
.tfaw = 20,
|
||||
.trp = 6,
|
||||
.twtr = 4,
|
||||
.tras_min = 15,
|
||||
.tmrd = 4,
|
||||
.trtp = 4,
|
||||
.tras_max = 28080,
|
||||
.tmod = 12,
|
||||
.tckesr = 4,
|
||||
.tcke = 3,
|
||||
.trcd_int = 6,
|
||||
.tdal = 12,
|
||||
.tdll = 512,
|
||||
.trp_ab = 6,
|
||||
.tref = 3120,
|
||||
.trfc = 64,
|
||||
.tpdex = 3,
|
||||
.txpdll = 10,
|
||||
.txsnr = 48,
|
||||
.txsr = 468,
|
||||
.cksrx = 5,
|
||||
.cksre = 5,
|
||||
.zqcl = 256,
|
||||
.zqinit = 512,
|
||||
.zqcs = 64,
|
||||
.ref_per_zq = 64,
|
||||
.aprebit = 10,
|
||||
.wlmrd = 40,
|
||||
.wldqsen = 25,
|
||||
.tinit = 5,
|
||||
.trst_pwron = 80000,
|
||||
.cke_inactive = 200000,
|
||||
.wrlat = 5,
|
||||
.caslat_lin = 12,
|
||||
.trc = 21,
|
||||
.trrd = 4,
|
||||
.tccd = 4,
|
||||
.tbst_int_interval = 0,
|
||||
.tfaw = 20,
|
||||
.trp = 6,
|
||||
.twtr = 4,
|
||||
.tras_min = 15,
|
||||
.tmrd = 4,
|
||||
.trtp = 4,
|
||||
.tras_max = 28080,
|
||||
.tmod = 12,
|
||||
.tckesr = 4,
|
||||
.tcke = 3,
|
||||
.trcd_int = 6,
|
||||
.tras_lockout = 0,
|
||||
.tdal = 12,
|
||||
.bstlen = 0,
|
||||
.tdll = 512,
|
||||
.trp_ab = 6,
|
||||
.tref = 3120,
|
||||
.trfc = 64,
|
||||
.tref_int = 0,
|
||||
.tpdex = 3,
|
||||
.txpdll = 10,
|
||||
.txsnr = 48,
|
||||
.txsr = 468,
|
||||
.cksrx = 5,
|
||||
.cksre = 5,
|
||||
.freq_chg_en = 0,
|
||||
.zqcl = 256,
|
||||
.zqinit = 512,
|
||||
.zqcs = 64,
|
||||
.ref_per_zq = 64,
|
||||
.zqcs_rotate = 0,
|
||||
.aprebit = 10,
|
||||
.cmd_age_cnt = 64,
|
||||
.age_cnt = 64,
|
||||
.q_fullness = 7,
|
||||
.odt_rd_mapcs0 = 0,
|
||||
.odt_wr_mapcs0 = 1,
|
||||
.wlmrd = 40,
|
||||
.wldqsen = 25,
|
||||
};
|
||||
|
||||
ddrmc_setup_iomux();
|
||||
ddrmc_setup_iomux(NULL, 0);
|
||||
|
||||
ddrmc_ctrl_init_ddr3(&timings, NULL, 1, 2);
|
||||
ddrmc_ctrl_init_ddr3(&timings, colibri_vf_cr_settings, NULL, 1, 2);
|
||||
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
|
||||
|
||||
return 0;
|
||||
|
Loading…
Reference in New Issue
Block a user