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https://github.com/brain-hackers/u-boot-brain
synced 2024-09-29 16:10:24 +09:00
arm: dts: enable MTK SPI NOR controller driver
1. Enable MTK SPI NOR controller driver on mt7622 & mt7629. 2. Enable quad mode for read and single mode for write. Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
This commit is contained in:
parent
7a49d61742
commit
3f1250a9e2
@ -19,7 +19,7 @@
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};
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};
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aliases {
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aliases {
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spi0 = &snfi;
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spi0 = &snor;
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};
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};
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memory@40000000 {
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memory@40000000 {
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@ -165,11 +165,25 @@
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pinctrl-names = "default", "snfi";
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pinctrl-names = "default", "snfi";
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pinctrl-0 = <&snor_pins>;
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pinctrl-0 = <&snor_pins>;
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pinctrl-1 = <&snfi_pins>;
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pinctrl-1 = <&snfi_pins>;
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status = "disabled";
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spi-flash@0{
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compatible = "jedec,spi-nor";
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reg = <0>;
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u-boot,dm-pre-reloc;
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};
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};
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&snor {
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pinctrl-names = "default";
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pinctrl-0 = <&snor_pins>;
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status = "okay";
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status = "okay";
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spi-flash@0{
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spi-flash@0{
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compatible = "jedec,spi-nor";
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compatible = "jedec,spi-nor";
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reg = <0>;
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reg = <0>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <4>;
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u-boot,dm-pre-reloc;
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u-boot,dm-pre-reloc;
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};
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};
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};
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};
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@ -53,6 +53,17 @@
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#size-cells = <0>;
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#size-cells = <0>;
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};
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};
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snor: snor@11014000 {
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compatible = "mediatek,mtk-snor";
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reg = <0x11014000 0x1000>;
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clocks = <&pericfg CLK_PERI_FLASH_PD>,
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<&topckgen CLK_TOP_FLASH_SEL>;
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clock-names = "spi", "sf";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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timer {
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timer {
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compatible = "arm,armv8-timer";
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupt-parent = <&gic>;
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@ -14,7 +14,7 @@
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compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
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compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
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aliases {
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aliases {
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spi0 = &snfi;
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spi0 = &snor;
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};
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};
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chosen {
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chosen {
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@ -69,11 +69,25 @@
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pinctrl-names = "default", "snfi";
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pinctrl-names = "default", "snfi";
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pinctrl-0 = <&snor_pins>;
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pinctrl-0 = <&snor_pins>;
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pinctrl-1 = <&snfi_pins>;
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pinctrl-1 = <&snfi_pins>;
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status = "disabled";
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spi-flash@0{
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compatible = "jedec,spi-nor";
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reg = <0>;
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u-boot,dm-pre-reloc;
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};
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};
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&snor {
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pinctrl-names = "default";
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pinctrl-0 = <&snor_pins>;
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status = "okay";
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status = "okay";
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spi-flash@0{
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spi-flash@0{
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compatible = "jedec,spi-nor";
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compatible = "jedec,spi-nor";
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reg = <0>;
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reg = <0>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <4>;
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u-boot,dm-pre-reloc;
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u-boot,dm-pre-reloc;
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};
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};
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};
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};
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@ -223,6 +223,17 @@
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#size-cells = <0>;
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#size-cells = <0>;
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};
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};
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snor: snor@11014000 {
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compatible = "mediatek,mtk-snor";
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reg = <0x11014000 0x1000>;
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clocks = <&pericfg CLK_PERI_FLASH_PD>,
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<&topckgen CLK_TOP_FLASH_SEL>;
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clock-names = "spi", "sf";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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ssusbsys: ssusbsys@1a000000 {
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ssusbsys: ssusbsys@1a000000 {
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compatible = "mediatek,mt7629-ssusbsys", "syscon";
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compatible = "mediatek,mt7629-ssusbsys", "syscon";
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reg = <0x1a000000 0x1000>;
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reg = <0x1a000000 0x1000>;
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@ -49,7 +49,8 @@ CONFIG_DM_SERIAL=y
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CONFIG_MTK_SERIAL=y
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CONFIG_MTK_SERIAL=y
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CONFIG_SPI=y
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CONFIG_SPI=y
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CONFIG_DM_SPI=y
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CONFIG_DM_SPI=y
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CONFIG_MTK_SNFI_SPI=y
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# CONFIG_MTK_SNFI_SPI is not set
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CONFIG_MTK_SNOR=y
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CONFIG_SYSRESET_WATCHDOG=y
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CONFIG_SYSRESET_WATCHDOG=y
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CONFIG_TIMER=y
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CONFIG_TIMER=y
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CONFIG_MTK_TIMER=y
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CONFIG_MTK_TIMER=y
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@ -75,7 +75,8 @@ CONFIG_DM_SERIAL=y
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CONFIG_MTK_SERIAL=y
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CONFIG_MTK_SERIAL=y
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CONFIG_SPI=y
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CONFIG_SPI=y
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CONFIG_DM_SPI=y
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CONFIG_DM_SPI=y
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CONFIG_MTK_SNFI_SPI=y
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# CONFIG_MTK_SNFI_SPI is not set
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CONFIG_MTK_SNOR=y
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CONFIG_SYSRESET=y
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CONFIG_SYSRESET=y
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CONFIG_SPL_SYSRESET=y
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CONFIG_SPL_SYSRESET=y
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CONFIG_SYSRESET_WATCHDOG=y
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CONFIG_SYSRESET_WATCHDOG=y
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