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https://github.com/brain-hackers/u-boot-brain
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arm: freescale: Rename initdram() to fsl_initdram()
This function name shadows a global name but is in fact different. This is very confusing. Rename it to help with the following refactoring. Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
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6bacc73621
commit
3eace37e50
@ -5,6 +5,7 @@
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*/
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*/
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#include <common.h>
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#include <common.h>
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#include <fsl_ddr_sdram.h>
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#include <asm/io.h>
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#include <asm/io.h>
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#include <linux/errno.h>
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#include <linux/errno.h>
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#include <asm/system.h>
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#include <asm/system.h>
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@ -876,7 +877,7 @@ void update_early_mmu_table(void)
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__weak int dram_init(void)
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__weak int dram_init(void)
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{
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{
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initdram();
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fsl_initdram();
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#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
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#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
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/* This will break-before-make MMU for DDR */
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/* This will break-before-make MMU for DDR */
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update_early_mmu_table();
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update_early_mmu_table();
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@ -164,7 +164,7 @@ void board_mem_sleep_setup(void)
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}
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}
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#endif
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#endif
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int initdram(void)
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int fsl_initdram(void)
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{
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{
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phys_size_t dram_size;
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phys_size_t dram_size;
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@ -162,7 +162,7 @@ int dram_init(void)
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* before accessing DDR SPD.
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* before accessing DDR SPD.
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*/
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*/
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select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
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select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
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return initdram();
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return fsl_initdram();
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}
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}
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#ifdef CONFIG_FSL_ESDHC
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#ifdef CONFIG_FSL_ESDHC
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@ -108,7 +108,7 @@ found:
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#endif
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#endif
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}
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}
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int initdram(void)
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int fsl_initdram(void)
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{
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{
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phys_size_t dram_size;
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phys_size_t dram_size;
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@ -7,6 +7,7 @@
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#include <common.h>
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#include <common.h>
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#include <i2c.h>
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#include <i2c.h>
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#include <fdt_support.h>
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#include <fdt_support.h>
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#include <fsl_ddr_sdram.h>
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#include <asm/io.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/fsl_serdes.h>
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@ -153,7 +154,7 @@ int dram_init(void)
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* before accessing DDR SPD.
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* before accessing DDR SPD.
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*/
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*/
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select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
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select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
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initdram();
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fsl_initdram();
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#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
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#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
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/* This will break-before-make MMU for DDR */
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/* This will break-before-make MMU for DDR */
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update_early_mmu_table();
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update_early_mmu_table();
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@ -170,7 +170,7 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
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}
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}
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#endif
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#endif
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int initdram(void)
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int fsl_initdram(void)
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{
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{
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phys_size_t dram_size;
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phys_size_t dram_size;
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@ -92,7 +92,7 @@ found:
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popts->cpo_sample = 0x70;
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popts->cpo_sample = 0x70;
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}
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}
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int initdram(void)
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int fsl_initdram(void)
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{
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{
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phys_size_t dram_size;
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phys_size_t dram_size;
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@ -7,6 +7,7 @@
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#include <common.h>
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#include <common.h>
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#include <i2c.h>
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#include <i2c.h>
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#include <fdt_support.h>
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#include <fdt_support.h>
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#include <fsl_ddr_sdram.h>
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#include <asm/io.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/fsl_serdes.h>
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@ -149,7 +150,7 @@ int dram_init(void)
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* before accessing DDR SPD.
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* before accessing DDR SPD.
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*/
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*/
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select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
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select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
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initdram();
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fsl_initdram();
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#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
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#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
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/* This will break-before-make MMU for DDR */
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/* This will break-before-make MMU for DDR */
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update_early_mmu_table();
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update_early_mmu_table();
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@ -96,7 +96,7 @@ found:
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popts->cpo_sample = 0x70;
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popts->cpo_sample = 0x70;
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}
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}
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int initdram(void)
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int fsl_initdram(void)
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{
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{
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phys_size_t dram_size;
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phys_size_t dram_size;
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@ -158,7 +158,8 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
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return 0;
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return 0;
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}
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}
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#endif
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#endif
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int initdram(void)
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int fsl_initdram(void)
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{
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{
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puts("Initializing DDR....");
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puts("Initializing DDR....");
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@ -155,7 +155,7 @@ found:
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}
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}
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}
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}
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int initdram(void)
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int fsl_initdram(void)
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{
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{
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#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
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#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
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gd->ram_size = fsl_ddr_sdram_size();
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gd->ram_size = fsl_ddr_sdram_size();
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@ -158,7 +158,7 @@ found:
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}
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}
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}
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}
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int initdram(void)
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int fsl_initdram(void)
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{
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{
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#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
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#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
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gd->ram_size = fsl_ddr_sdram_size();
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gd->ram_size = fsl_ddr_sdram_size();
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@ -477,4 +477,12 @@ typedef struct fixed_ddr_parm{
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int max_freq;
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int max_freq;
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fsl_ddr_cfg_regs_t *ddr_settings;
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fsl_ddr_cfg_regs_t *ddr_settings;
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} fixed_ddr_parm_t;
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} fixed_ddr_parm_t;
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/**
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* fsl_initdram() - Set up the SDRAM
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*
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* @return 0 if OK, -ve on error
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*/
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int fsl_initdram(void);
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#endif
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#endif
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