brain-hackers_pepepper-mirror/u-boot-brain
1
0
Fork 0
mirror of https://github.com/brain-hackers/u-boot-brain synced 2024-06-09 23:36:03 +09:00
Code Issues Projects Releases Wiki Activity

mpc83xx: don't set SICRH_TSOBI1 to RMII/RTBI operation

Browse Source 
In GMII mode (which operates at 3.3V) both SICRH TSEC1/2 output buffer
impedance bits should be clear, i.e., SICRH[TSIOB1] = 0 and SICRH[TSIOB2] = 0.
SICRH[TSIOB1] was erroneously being set high.

U-Boot always operated this PHY interface in GMII mode.  It is assumed this
was missed in the clean up by the original board porters, and copied along
to the TQM and sbc boards.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Acked-by: Ira Snyder <iws@ovro.caltech.edu>
Reviewed-by: David Hawkins <dwh@ovro.caltech.edu>
Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com>
CC: Dave Liu <DaveLiu@freescale.com>
This commit is contained in:
Kim Phillips 2009-06-05 14:11:33 -05:00
parent 3bc8556f9b
commit 3c9b1ee17e
3 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
include/configs/MPC8349EMDS.h
View File

@ -598,7 +598,7 @@
#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
/* System IO Config */
#define CONFIG_SYS_SICRH SICRH_TSOBI1
#define CONFIG_SYS_SICRH 0
#define CONFIG_SYS_SICRL SICRL_LDP_A
#define CONFIG_SYS_HID0_INIT 0x000000000

2
include/configs/TQM834x.h
View File

@ -393,7 +393,7 @@ extern int tqm834x_num_flash_banks;
#endif
/* System IO Config */
#define CONFIG_SYS_SICRH SICRH_TSOBI1
#define CONFIG_SYS_SICRH 0
#define CONFIG_SYS_SICRL SICRL_LDP_A
/* i-cache and d-cache disabled */

2
include/configs/sbc8349.h
View File

@ -519,7 +519,7 @@
#endif
/* System IO Config */
#define CONFIG_SYS_SICRH SICRH_TSOBI1
#define CONFIG_SYS_SICRH 0
#define CONFIG_SYS_SICRL SICRL_LDP_A
#define CONFIG_SYS_HID0_INIT 0x000000000