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imx8m: add eqos clk

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Add imx_eqos_txclk_set_rate/imx_get_eqos_csr_clk to override the
weak function in driver

Add set_clk_eqos to configure eQoS clk

Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Peng Fan 2020-07-09 13:14:20 +08:00
parent 3c1c28d4e0
commit 3c9221ad27
1 changed files with 90 additions and 0 deletions
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90
arch/arm/mach-imx/imx8m/clock_imx8mm.c
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@ -788,6 +788,96 @@ u32 mxc_get_clock(enum mxc_clock clk)
return 0;
}
#ifdef CONFIG_DWC_ETH_QOS
int set_clk_eqos(enum enet_freq type)
{
u32 target;
u32 enet1_ref;
switch (type) {
case ENET_125MHZ:
enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
break;
case ENET_50MHZ:
enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
break;
case ENET_25MHZ:
enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
break;
default:
return -EINVAL;
}
/* disable the clock first */
clock_enable(CCGR_QOS_ETHENET, 0);
clock_enable(CCGR_SDMA2, 0);
/* set enet axi clock 266Mhz */
target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
clock_set_target_val(ENET_AXI_CLK_ROOT, target);
target = CLK_ROOT_ON | enet1_ref |
CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
clock_set_target_val(ENET_QOS_CLK_ROOT, target);
target = CLK_ROOT_ON |
ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
clock_set_target_val(ENET_QOS_TIMER_CLK_ROOT, target);
/* enable clock */
clock_enable(CCGR_QOS_ETHENET, 1);
clock_enable(CCGR_SDMA2, 1);
return 0;
}
int imx_eqos_txclk_set_rate(u32 rate)
{
u32 val;
u32 eqos_post_div;
/* disable the clock first */
clock_enable(CCGR_QOS_ETHENET, 0);
clock_enable(CCGR_SDMA2, 0);
switch (rate) {
case 125000000:
eqos_post_div = 1;
break;
case 25000000:
eqos_post_div = 125000000 / 25000000;
break;
case 2500000:
eqos_post_div = 125000000 / 2500000;
break;
default:
return -EINVAL;
}
clock_get_target_val(ENET_QOS_CLK_ROOT, &val);
val &= ~(CLK_ROOT_PRE_DIV_MASK | CLK_ROOT_POST_DIV_MASK);
val |= CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
CLK_ROOT_POST_DIV(eqos_post_div - 1);
clock_set_target_val(ENET_QOS_CLK_ROOT, val);
/* enable clock */
clock_enable(CCGR_QOS_ETHENET, 1);
clock_enable(CCGR_SDMA2, 1);
return 0;
}
u32 imx_get_eqos_csr_clk(void)
{
return get_root_clk(ENET_AXI_CLK_ROOT);
}
#endif
#ifdef CONFIG_FEC_MXC
int set_clk_enet(enum enet_freq type)
{