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https://github.com/brain-hackers/u-boot-brain
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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
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commit
3c92217732
@ -47,7 +47,6 @@ void fsl_sgmii_riser_fdt_fixup(void *fdt)
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const char *model;
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const char *path;
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printf("Updating PHY address for %s\n", dev->name);
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if (!strstr(dev->name, "eTSEC"))
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continue;
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@ -64,7 +63,6 @@ void fsl_sgmii_riser_fdt_fixup(void *fdt)
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model = fdt_getprop(fdt, enet_node, "model", NULL);
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printf("%s's model is %s\n", enet, model);
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/*
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* We only want to do this to eTSECs. On some platforms
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* there are more than one type of gianfar-style ethernet
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@ -84,7 +82,6 @@ void fsl_sgmii_riser_fdt_fixup(void *fdt)
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priv = dev->priv;
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printf("Device flags are %x\n", priv->flags);
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if (priv->flags & TSEC_SGMII)
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fdt_setprop_cell(fdt, phynode, "reg", priv->phyaddr);
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}
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@ -79,8 +79,8 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
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out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
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out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
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/* Do not enable the memory */
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temp_sdram_cfg = in_be32(&ddr->sdram_cfg);
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/* Set, but do not enable the memory */
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temp_sdram_cfg = regs->ddr_sdram_cfg;
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temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
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out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
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/*
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@ -1624,7 +1624,7 @@ struct phy_info *phy_info[] = {
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&phy_info_VSC8601,
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&phy_info_dp83865,
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&phy_info_rtl8211b,
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&phy_info_generic,
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&phy_info_generic, /* must be last; has ID 0 and 32 bit mask */
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NULL
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};
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@ -1656,9 +1656,8 @@ struct phy_info *get_phy_info(struct eth_device *dev)
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}
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}
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if (theInfo == NULL) {
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printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID);
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return NULL;
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if (theInfo == &phy_info_generic) {
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printf("%s: No support for PHY id %x; assuming generic\n", dev->name, phy_ID);
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} else {
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debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID);
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}
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@ -1667,7 +1667,7 @@ typedef struct ccsr_gur {
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uint lbiuiplldcr0; /* 0xe0f1c -- LBIU PLL Debug Reg 0 */
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uint lbiuiplldcr1; /* 0xe0f20 -- LBIU PLL Debug Reg 1 */
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uint ddrioovcr; /* 0xe0f24 - DDR IO Override Control */
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uint res14; /* 0xe0f28 */
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uint tsec12ioovcr; /* 0xe0f28 - eTSEC 1/2 IO override control */
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uint tsec34ioovcr; /* 0xe0f2c - eTSEC 3/4 IO override control */
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char res15[61648]; /* 0xe0f30 to 0xefffff */
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} ccsr_gur_t;
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