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armv8: LS2080A: Consolidate LS2080A and LS2085A
LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
This commit is contained in:
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@ -25,10 +25,6 @@ ifneq ($(CONFIG_LS2080A),)
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obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o
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obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o
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endif
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endif
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ifneq ($(CONFIG_LS2085A),)
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obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o
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endif
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ifneq ($(CONFIG_LS1043A),)
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ifneq ($(CONFIG_LS1043A),)
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obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
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obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
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endif
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endif
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@ -538,12 +538,12 @@ int print_cpuinfo(void)
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struct sys_info sysinfo;
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struct sys_info sysinfo;
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char buf[32];
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char buf[32];
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unsigned int i, core;
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unsigned int i, core;
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u32 type, rcw;
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u32 type, rcw, svr = gur_in32(&gur->svr);
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puts("SoC: ");
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puts("SoC: ");
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cpu_name(buf);
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cpu_name(buf);
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printf(" %s (0x%x)\n", buf, gur_in32(&gur->svr));
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printf(" %s (0x%x)\n", buf, svr);
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memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
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memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
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get_sys_info(&sysinfo);
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get_sys_info(&sysinfo);
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puts("Clock Configuration:");
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puts("Clock Configuration:");
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@ -564,7 +564,10 @@ int print_cpuinfo(void)
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printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
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printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
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#endif
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#endif
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#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
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#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
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printf(" DP-DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus2));
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if (soc_has_dp_ddr()) {
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printf(" DP-DDR: %-4s MT/s",
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strmhz(buf, sysinfo.freq_ddrbus2));
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}
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#endif
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#endif
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puts("\n");
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puts("\n");
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@ -97,9 +97,13 @@ void get_sys_info(struct sys_info *sys_info)
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FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
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FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
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FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
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FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
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#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
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#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
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sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >>
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if (soc_has_dp_ddr()) {
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sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >>
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FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) &
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FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) &
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FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK;
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FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK;
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} else {
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sys_info->freq_ddrbus2 = 0;
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}
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#endif
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#endif
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for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
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for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
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@ -20,7 +20,7 @@ ENTRY(lowlevel_init)
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#ifdef CONFIG_FSL_LSCH3
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#ifdef CONFIG_FSL_LSCH3
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/* Set Wuo bit for RN-I 20 */
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/* Set Wuo bit for RN-I 20 */
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#if defined(CONFIG_LS2085A) || defined (CONFIG_LS2080A)
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#ifdef CONFIG_LS2080A
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ldr x0, =CCI_AUX_CONTROL_BASE(20)
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ldr x0, =CCI_AUX_CONTROL_BASE(20)
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ldr x1, =0x00000010
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ldr x1, =0x00000010
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bl ccn504_set_aux
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bl ccn504_set_aux
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@ -18,7 +18,31 @@
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
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bool soc_has_dp_ddr(void)
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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u32 svr = gur_in32(&gur->svr);
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/* LS2085A has DP_DDR */
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if (SVR_SOC_VER(svr) == SVR_LS2085)
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return true;
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return false;
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}
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bool soc_has_aiop(void)
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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u32 svr = gur_in32(&gur->svr);
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/* LS2085A has AIOP */
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if (SVR_SOC_VER(svr) == SVR_LS2085)
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return true;
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return false;
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}
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#ifdef CONFIG_LS2080A
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/*
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/*
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* This erratum requires setting a value to eddrtqcr1 to
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* This erratum requires setting a value to eddrtqcr1 to
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* optimal the DDR performance.
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* optimal the DDR performance.
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@ -46,7 +46,7 @@ void board_init_f(ulong dummy)
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{
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{
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/* Clear global data */
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/* Clear global data */
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memset((void *)gd, 0, sizeof(gd_t));
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memset((void *)gd, 0, sizeof(gd_t));
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#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
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#ifdef CONFIG_LS2080A
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arch_cpu_init();
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arch_cpu_init();
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#endif
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#endif
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#ifdef CONFIG_FSL_IFC
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#ifdef CONFIG_FSL_IFC
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@ -54,7 +54,7 @@ void board_init_f(ulong dummy)
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#endif
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#endif
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board_early_init_f();
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board_early_init_f();
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timer_init();
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timer_init();
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#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
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#ifdef CONFIG_LS2080A
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env_init();
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env_init();
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#endif
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#endif
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get_clocks();
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get_clocks();
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@ -23,16 +23,11 @@
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*/
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*/
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#define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */
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#define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */
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#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
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#ifdef CONFIG_LS2080A
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#define CONFIG_MAX_CPUS 16
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#define CONFIG_MAX_CPUS 16
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
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#ifdef CONFIG_LS2080A
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#define CONFIG_NUM_DDR_CONTROLLERS 2
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#endif
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#ifdef CONFIG_LS2085A
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#define CONFIG_NUM_DDR_CONTROLLERS 3
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#define CONFIG_NUM_DDR_CONTROLLERS 3
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#define CONFIG_SYS_FSL_HAS_DP_DDR
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#define CONFIG_SYS_FSL_HAS_DP_DDR /* Runtime check to confirm */
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#endif
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#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
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#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
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#define SRDS_MAX_LANES 8
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#define SRDS_MAX_LANES 8
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#define CONFIG_SYS_FSL_SRDS_1
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#define CONFIG_SYS_FSL_SRDS_1
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@ -206,7 +206,7 @@ static const struct sys_mmu_table final_mmu_table[] = {
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{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
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{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
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CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE,
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CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE,
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
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#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
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#ifdef CONFIG_LS2080A
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{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
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{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
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CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE,
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CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE,
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
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@ -9,7 +9,7 @@
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#include <config.h>
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#include <config.h>
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#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
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#ifdef CONFIG_LS2080A
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enum srds_prtcl {
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enum srds_prtcl {
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NONE = 0,
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NONE = 0,
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PCIE1,
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PCIE1,
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@ -94,4 +94,7 @@ void cpu_name(char *name);
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#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
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#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
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void erratum_a009635(void);
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void erratum_a009635(void);
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#endif
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#endif
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bool soc_has_dp_ddr(void);
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bool soc_has_aiop(void);
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#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */
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#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */
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@ -44,15 +44,14 @@
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#endif
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#endif
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#if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A) ||\
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#if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A)
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defined(CONFIG_LS2085A)
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/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit
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/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit
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* Similiarly for LS2080 and LS2085
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* Similiarly for LS2080
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*/
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*/
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#define CONFIG_ESBC_ADDR_64BIT
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#define CONFIG_ESBC_ADDR_64BIT
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#endif
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#endif
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#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
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#ifdef CONFIG_LS2080A
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#define CONFIG_EXTRA_ENV \
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#define CONFIG_EXTRA_ENV \
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"setenv fdt_high 0xa0000000;" \
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"setenv fdt_high 0xa0000000;" \
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"setenv initrd_high 0xcfffffff;" \
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"setenv initrd_high 0xcfffffff;" \
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@ -66,12 +65,11 @@
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/* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from
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/* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from
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* Non-XIP Memory (Nand/SD)*/
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* Non-XIP Memory (Nand/SD)*/
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#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A) ||\
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#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A)
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defined(CONFIG_LS2085A)
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#define CONFIG_BOOTSCRIPT_COPY_RAM
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#define CONFIG_BOOTSCRIPT_COPY_RAM
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#endif
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#endif
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/* The address needs to be modified according to NOR and DDR memory map */
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/* The address needs to be modified according to NOR and DDR memory map */
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#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
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#ifdef CONFIG_LS2080A
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#define CONFIG_BS_HDR_ADDR_FLASH 0x583920000
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#define CONFIG_BS_HDR_ADDR_FLASH 0x583920000
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#define CONFIG_BS_ADDR_FLASH 0x583900000
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#define CONFIG_BS_ADDR_FLASH 0x583900000
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#define CONFIG_BS_HDR_ADDR_RAM 0xa3920000
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#define CONFIG_BS_HDR_ADDR_RAM 0xa3920000
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@ -6,5 +6,3 @@ F: include/configs/ls2080a_emu.h
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F: configs/ls2080a_emu_defconfig
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F: configs/ls2080a_emu_defconfig
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F: include/configs/ls2080a_simu.h
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F: include/configs/ls2080a_simu.h
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F: configs/ls2080a_simu_defconfig
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F: configs/ls2080a_simu_defconfig
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F: configs/ls2085a_emu_defconfig
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F: configs/ls2085a_simu_defconfig
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@ -7,6 +7,7 @@
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#include <common.h>
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#include <common.h>
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#include <fsl_ddr_sdram.h>
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#include <fsl_ddr_sdram.h>
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#include <fsl_ddr_dimm_params.h>
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#include <fsl_ddr_dimm_params.h>
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#include <asm/arch/soc.h>
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#include "ddr.h"
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#include "ddr.h"
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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@ -201,22 +202,24 @@ void dram_init_banksize(void)
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}
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}
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#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
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#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
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/* initialize DP-DDR here */
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if (soc_has_dp_ddr()) {
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puts("DP-DDR: ");
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/* initialize DP-DDR here */
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/*
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puts("DP-DDR: ");
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* DDR controller use 0 as the base address for binding.
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/*
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* It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
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* DDR controller use 0 as the base address for binding.
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*/
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* It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
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dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
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*/
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dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
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CONFIG_DP_DDR_CTRL,
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CONFIG_DP_DDR_CTRL,
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CONFIG_DP_DDR_NUM_CTRLS,
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CONFIG_DP_DDR_NUM_CTRLS,
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CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
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CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
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NULL, NULL, NULL);
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NULL, NULL, NULL);
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if (dp_ddr_size) {
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if (dp_ddr_size) {
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gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
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gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
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gd->bd->bi_dram[2].size = dp_ddr_size;
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gd->bd->bi_dram[2].size = dp_ddr_size;
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} else {
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} else {
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puts("Not detected");
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puts("Not detected");
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}
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}
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}
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#endif
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#endif
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}
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}
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@ -42,7 +42,7 @@ void detail_board_ddr_info(void)
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print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
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print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
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print_ddr_info(0);
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print_ddr_info(0);
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#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
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#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
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if (gd->bd->bi_dram[2].size) {
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if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
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puts("\nDP-DDR ");
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puts("\nDP-DDR ");
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print_size(gd->bd->bi_dram[2].size, "");
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print_size(gd->bd->bi_dram[2].size, "");
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print_ddr_info(CONFIG_DP_DDR_CTRL);
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print_ddr_info(CONFIG_DP_DDR_CTRL);
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@ -6,11 +6,8 @@ F: board/freescale/ls2080a/ls2080aqds.c
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F: include/configs/ls2080aqds.h
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F: include/configs/ls2080aqds.h
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F: configs/ls2080aqds_defconfig
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F: configs/ls2080aqds_defconfig
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F: configs/ls2080aqds_nand_defconfig
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F: configs/ls2080aqds_nand_defconfig
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F: configs/ls2085aqds_defconfig
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F: configs/ls2085aqds_nand_defconfig
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LS2080A_SECURE_BOOT BOARD
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LS2080A_SECURE_BOOT BOARD
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M: Saksham Jain <saksham.jain@nxp.freescale.com>
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M: Saksham Jain <saksham.jain@nxp.freescale.com>
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S: Maintained
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S: Maintained
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F: configs/ls2080aqds_SECURE_BOOT_defconfig
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F: configs/ls2080aqds_SECURE_BOOT_defconfig
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F: configs/ls2085aqds_SECURE_BOOT_defconfig
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@ -7,6 +7,7 @@
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#include <common.h>
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#include <common.h>
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#include <fsl_ddr_sdram.h>
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#include <fsl_ddr_sdram.h>
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#include <fsl_ddr_dimm_params.h>
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#include <fsl_ddr_dimm_params.h>
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#include <asm/arch/soc.h>
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#include "ddr.h"
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#include "ddr.h"
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DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
@ -201,22 +202,24 @@ void dram_init_banksize(void)
|
|||||||
}
|
}
|
||||||
|
|
||||||
#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
|
#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
|
||||||
/* initialize DP-DDR here */
|
if (soc_has_dp_ddr()) {
|
||||||
puts("DP-DDR: ");
|
/* initialize DP-DDR here */
|
||||||
/*
|
puts("DP-DDR: ");
|
||||||
* DDR controller use 0 as the base address for binding.
|
/*
|
||||||
* It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
|
* DDR controller use 0 as the base address for binding.
|
||||||
*/
|
* It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
|
||||||
dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
|
*/
|
||||||
|
dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
|
||||||
CONFIG_DP_DDR_CTRL,
|
CONFIG_DP_DDR_CTRL,
|
||||||
CONFIG_DP_DDR_NUM_CTRLS,
|
CONFIG_DP_DDR_NUM_CTRLS,
|
||||||
CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
|
CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
|
||||||
NULL, NULL, NULL);
|
NULL, NULL, NULL);
|
||||||
if (dp_ddr_size) {
|
if (dp_ddr_size) {
|
||||||
gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
|
gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
|
||||||
gd->bd->bi_dram[2].size = dp_ddr_size;
|
gd->bd->bi_dram[2].size = dp_ddr_size;
|
||||||
} else {
|
} else {
|
||||||
puts("Not detected");
|
puts("Not detected");
|
||||||
|
}
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
@ -228,7 +228,7 @@ void detail_board_ddr_info(void)
|
|||||||
print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
|
print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
|
||||||
print_ddr_info(0);
|
print_ddr_info(0);
|
||||||
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
|
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
|
||||||
if (gd->bd->bi_dram[2].size) {
|
if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
|
||||||
puts("\nDP-DDR ");
|
puts("\nDP-DDR ");
|
||||||
print_size(gd->bd->bi_dram[2].size, "");
|
print_size(gd->bd->bi_dram[2].size, "");
|
||||||
print_ddr_info(CONFIG_DP_DDR_CTRL);
|
print_ddr_info(CONFIG_DP_DDR_CTRL);
|
||||||
|
@ -6,11 +6,8 @@ F: board/freescale/ls2080a/ls2080ardb.c
|
|||||||
F: include/configs/ls2080ardb.h
|
F: include/configs/ls2080ardb.h
|
||||||
F: configs/ls2080ardb_defconfig
|
F: configs/ls2080ardb_defconfig
|
||||||
F: configs/ls2080ardb_nand_defconfig
|
F: configs/ls2080ardb_nand_defconfig
|
||||||
F: configs/ls2085ardb_defconfig
|
|
||||||
F: configs/ls2085ardb_nand_defconfig
|
|
||||||
|
|
||||||
LS2080A_SECURE_BOOT BOARD
|
LS2080A_SECURE_BOOT BOARD
|
||||||
M: Saksham Jain <saksham.jain@nxp.freescale.com>
|
M: Saksham Jain <saksham.jain@nxp.freescale.com>
|
||||||
S: Maintained
|
S: Maintained
|
||||||
F: configs/ls2080ardb_SECURE_BOOT_defconfig
|
F: configs/ls2080ardb_SECURE_BOOT_defconfig
|
||||||
F: configs/ls2085ardb_SECURE_BOOT_defconfig
|
|
||||||
|
@ -7,6 +7,7 @@
|
|||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <fsl_ddr_sdram.h>
|
#include <fsl_ddr_sdram.h>
|
||||||
#include <fsl_ddr_dimm_params.h>
|
#include <fsl_ddr_dimm_params.h>
|
||||||
|
#include <asm/arch/soc.h>
|
||||||
#include "ddr.h"
|
#include "ddr.h"
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
@ -201,22 +202,24 @@ void dram_init_banksize(void)
|
|||||||
}
|
}
|
||||||
|
|
||||||
#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
|
#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
|
||||||
/* initialize DP-DDR here */
|
if (soc_has_dp_ddr()) {
|
||||||
puts("DP-DDR: ");
|
/* initialize DP-DDR here */
|
||||||
/*
|
puts("DP-DDR: ");
|
||||||
* DDR controller use 0 as the base address for binding.
|
/*
|
||||||
* It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
|
* DDR controller use 0 as the base address for binding.
|
||||||
*/
|
* It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
|
||||||
dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
|
*/
|
||||||
|
dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
|
||||||
CONFIG_DP_DDR_CTRL,
|
CONFIG_DP_DDR_CTRL,
|
||||||
CONFIG_DP_DDR_NUM_CTRLS,
|
CONFIG_DP_DDR_NUM_CTRLS,
|
||||||
CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
|
CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
|
||||||
NULL, NULL, NULL);
|
NULL, NULL, NULL);
|
||||||
if (dp_ddr_size) {
|
if (dp_ddr_size) {
|
||||||
gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
|
gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
|
||||||
gd->bd->bi_dram[2].size = dp_ddr_size;
|
gd->bd->bi_dram[2].size = dp_ddr_size;
|
||||||
} else {
|
} else {
|
||||||
puts("Not detected");
|
puts("Not detected");
|
||||||
|
}
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
@ -207,7 +207,7 @@ void detail_board_ddr_info(void)
|
|||||||
print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
|
print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
|
||||||
print_ddr_info(0);
|
print_ddr_info(0);
|
||||||
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
|
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
|
||||||
if (gd->bd->bi_dram[2].size) {
|
if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
|
||||||
puts("\nDP-DDR ");
|
puts("\nDP-DDR ");
|
||||||
print_size(gd->bd->bi_dram[2].size, "");
|
print_size(gd->bd->bi_dram[2].size, "");
|
||||||
print_ddr_info(CONFIG_DP_DDR_CTRL);
|
print_ddr_info(CONFIG_DP_DDR_CTRL);
|
||||||
|
@ -1,20 +0,0 @@
|
|||||||
CONFIG_ARM=y
|
|
||||||
CONFIG_TARGET_LS2080A_EMU=y
|
|
||||||
CONFIG_FIT=y
|
|
||||||
CONFIG_FIT_VERBOSE=y
|
|
||||||
CONFIG_OF_BOARD_SETUP=y
|
|
||||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
|
||||||
CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4, LS2085A"
|
|
||||||
# CONFIG_CMD_CONSOLE is not set
|
|
||||||
# CONFIG_CMD_IMLS is not set
|
|
||||||
# CONFIG_CMD_XIMG is not set
|
|
||||||
# CONFIG_CMD_EDITENV is not set
|
|
||||||
# CONFIG_CMD_ENV_EXISTS is not set
|
|
||||||
# CONFIG_CMD_LOADS is not set
|
|
||||||
# CONFIG_CMD_FPGA is not set
|
|
||||||
# CONFIG_CMD_ITEST is not set
|
|
||||||
# CONFIG_CMD_SETEXPR is not set
|
|
||||||
# CONFIG_CMD_NFS is not set
|
|
||||||
# CONFIG_CMD_MISC is not set
|
|
||||||
CONFIG_SYS_NS16550=y
|
|
||||||
CONFIG_OF_LIBFDT=y
|
|
@ -1,21 +0,0 @@
|
|||||||
CONFIG_ARM=y
|
|
||||||
CONFIG_TARGET_LS2080A_SIMU=y
|
|
||||||
CONFIG_FIT=y
|
|
||||||
CONFIG_FIT_VERBOSE=y
|
|
||||||
CONFIG_OF_BOARD_SETUP=y
|
|
||||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
|
||||||
CONFIG_SYS_EXTRA_OPTIONS="SIMU, LS2085A"
|
|
||||||
# CONFIG_CMD_CONSOLE is not set
|
|
||||||
# CONFIG_CMD_IMLS is not set
|
|
||||||
# CONFIG_CMD_XIMG is not set
|
|
||||||
# CONFIG_CMD_EDITENV is not set
|
|
||||||
# CONFIG_CMD_ENV_EXISTS is not set
|
|
||||||
# CONFIG_CMD_LOADS is not set
|
|
||||||
# CONFIG_CMD_FPGA is not set
|
|
||||||
# CONFIG_CMD_ITEST is not set
|
|
||||||
# CONFIG_CMD_SETEXPR is not set
|
|
||||||
# CONFIG_CMD_NFS is not set
|
|
||||||
# CONFIG_CMD_MISC is not set
|
|
||||||
CONFIG_NET_RANDOM_ETHADDR=y
|
|
||||||
CONFIG_SYS_NS16550=y
|
|
||||||
CONFIG_OF_LIBFDT=y
|
|
@ -1,20 +0,0 @@
|
|||||||
CONFIG_ARM=y
|
|
||||||
CONFIG_TARGET_LS2080AQDS=y
|
|
||||||
# CONFIG_SYS_MALLOC_F is not set
|
|
||||||
CONFIG_DM_SPI=y
|
|
||||||
CONFIG_DM_SPI_FLASH=y
|
|
||||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
|
|
||||||
CONFIG_FIT=y
|
|
||||||
CONFIG_FIT_VERBOSE=y
|
|
||||||
CONFIG_OF_BOARD_SETUP=y
|
|
||||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
|
||||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2085A, SECURE_BOOT"
|
|
||||||
# CONFIG_CMD_SETEXPR is not set
|
|
||||||
CONFIG_OF_CONTROL=y
|
|
||||||
CONFIG_NET_RANDOM_ETHADDR=y
|
|
||||||
CONFIG_DM=y
|
|
||||||
CONFIG_NETDEVICES=y
|
|
||||||
CONFIG_E1000=y
|
|
||||||
CONFIG_SYS_NS16550=y
|
|
||||||
CONFIG_FSL_DSPI=y
|
|
||||||
CONFIG_RSA=y
|
|
@ -1,19 +0,0 @@
|
|||||||
CONFIG_ARM=y
|
|
||||||
CONFIG_TARGET_LS2080AQDS=y
|
|
||||||
# CONFIG_SYS_MALLOC_F is not set
|
|
||||||
CONFIG_DM_SPI=y
|
|
||||||
CONFIG_DM_SPI_FLASH=y
|
|
||||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
|
|
||||||
CONFIG_FIT=y
|
|
||||||
CONFIG_FIT_VERBOSE=y
|
|
||||||
CONFIG_OF_BOARD_SETUP=y
|
|
||||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
|
||||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2085A"
|
|
||||||
# CONFIG_CMD_SETEXPR is not set
|
|
||||||
CONFIG_OF_CONTROL=y
|
|
||||||
CONFIG_NET_RANDOM_ETHADDR=y
|
|
||||||
CONFIG_DM=y
|
|
||||||
CONFIG_NETDEVICES=y
|
|
||||||
CONFIG_E1000=y
|
|
||||||
CONFIG_SYS_NS16550=y
|
|
||||||
CONFIG_FSL_DSPI=y
|
|
@ -1,14 +0,0 @@
|
|||||||
CONFIG_ARM=y
|
|
||||||
CONFIG_TARGET_LS2080AQDS=y
|
|
||||||
CONFIG_SPL=y
|
|
||||||
CONFIG_FIT=y
|
|
||||||
CONFIG_FIT_VERBOSE=y
|
|
||||||
CONFIG_OF_BOARD_SETUP=y
|
|
||||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
|
||||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND,LS2085A"
|
|
||||||
# CONFIG_CMD_SETEXPR is not set
|
|
||||||
CONFIG_NET_RANDOM_ETHADDR=y
|
|
||||||
CONFIG_NETDEVICES=y
|
|
||||||
CONFIG_E1000=y
|
|
||||||
CONFIG_SYS_NS16550=y
|
|
||||||
CONFIG_OF_LIBFDT=y
|
|
@ -1,20 +0,0 @@
|
|||||||
CONFIG_ARM=y
|
|
||||||
CONFIG_TARGET_LS2080ARDB=y
|
|
||||||
# CONFIG_SYS_MALLOC_F is not set
|
|
||||||
CONFIG_DM_SPI=y
|
|
||||||
CONFIG_DM_SPI_FLASH=y
|
|
||||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
|
|
||||||
CONFIG_FIT=y
|
|
||||||
CONFIG_FIT_VERBOSE=y
|
|
||||||
CONFIG_OF_BOARD_SETUP=y
|
|
||||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
|
||||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2085A, SECURE_BOOT"
|
|
||||||
# CONFIG_CMD_SETEXPR is not set
|
|
||||||
CONFIG_OF_CONTROL=y
|
|
||||||
CONFIG_NET_RANDOM_ETHADDR=y
|
|
||||||
CONFIG_DM=y
|
|
||||||
CONFIG_NETDEVICES=y
|
|
||||||
CONFIG_E1000=y
|
|
||||||
CONFIG_SYS_NS16550=y
|
|
||||||
CONFIG_FSL_DSPI=y
|
|
||||||
CONFIG_RSA=y
|
|
@ -1,19 +0,0 @@
|
|||||||
CONFIG_ARM=y
|
|
||||||
CONFIG_TARGET_LS2080ARDB=y
|
|
||||||
# CONFIG_SYS_MALLOC_F is not set
|
|
||||||
CONFIG_DM_SPI=y
|
|
||||||
CONFIG_DM_SPI_FLASH=y
|
|
||||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
|
|
||||||
CONFIG_FIT=y
|
|
||||||
CONFIG_FIT_VERBOSE=y
|
|
||||||
CONFIG_OF_BOARD_SETUP=y
|
|
||||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
|
||||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2085A"
|
|
||||||
# CONFIG_CMD_SETEXPR is not set
|
|
||||||
CONFIG_OF_CONTROL=y
|
|
||||||
CONFIG_NET_RANDOM_ETHADDR=y
|
|
||||||
CONFIG_DM=y
|
|
||||||
CONFIG_NETDEVICES=y
|
|
||||||
CONFIG_E1000=y
|
|
||||||
CONFIG_SYS_NS16550=y
|
|
||||||
CONFIG_FSL_DSPI=y
|
|
@ -1,14 +0,0 @@
|
|||||||
CONFIG_ARM=y
|
|
||||||
CONFIG_TARGET_LS2080ARDB=y
|
|
||||||
CONFIG_SPL=y
|
|
||||||
CONFIG_FIT=y
|
|
||||||
CONFIG_FIT_VERBOSE=y
|
|
||||||
CONFIG_OF_BOARD_SETUP=y
|
|
||||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
|
||||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND,LS2085A"
|
|
||||||
# CONFIG_CMD_SETEXPR is not set
|
|
||||||
CONFIG_NET_RANDOM_ETHADDR=y
|
|
||||||
CONFIG_NETDEVICES=y
|
|
||||||
CONFIG_E1000=y
|
|
||||||
CONFIG_SYS_NS16550=y
|
|
||||||
CONFIG_OF_LIBFDT=y
|
|
@ -53,7 +53,7 @@ Note:
|
|||||||
|
|
||||||
Represents a single port that is compatible with the DUART found
|
Represents a single port that is compatible with the DUART found
|
||||||
on many Freescale chips (examples include mpc8349, mpc8548,
|
on many Freescale chips (examples include mpc8349, mpc8548,
|
||||||
mpc8641d, p4080 and ls2085a).
|
mpc8641d, p4080 and ls2080a).
|
||||||
|
|
||||||
Example:
|
Example:
|
||||||
|
|
||||||
|
@ -545,12 +545,12 @@ int sec_init(void)
|
|||||||
|
|
||||||
/*
|
/*
|
||||||
* Modifying CAAM Read/Write Attributes
|
* Modifying CAAM Read/Write Attributes
|
||||||
* For LS2080A and LS2085A
|
* For LS2080A
|
||||||
* For AXI Write - Cacheable, Write Back, Write allocate
|
* For AXI Write - Cacheable, Write Back, Write allocate
|
||||||
* For AXI Read - Cacheable, Read allocate
|
* For AXI Read - Cacheable, Read allocate
|
||||||
* Only For LS2080a and LS2085a, to solve CAAM coherency issues
|
* Only For LS2080a, to solve CAAM coherency issues
|
||||||
*/
|
*/
|
||||||
#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
|
#ifdef CONFIG_LS2080A
|
||||||
mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0xb << MCFGR_AWCACHE_SHIFT);
|
mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0xb << MCFGR_AWCACHE_SHIFT);
|
||||||
mcr = (mcr & ~MCFGR_ARCACHE_MASK) | (0x6 << MCFGR_ARCACHE_SHIFT);
|
mcr = (mcr & ~MCFGR_ARCACHE_MASK) | (0x6 << MCFGR_ARCACHE_SHIFT);
|
||||||
#else
|
#else
|
||||||
|
@ -356,6 +356,12 @@ static unsigned long get_mc_boot_timeout_ms(void)
|
|||||||
}
|
}
|
||||||
|
|
||||||
#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
|
#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
|
||||||
|
|
||||||
|
__weak bool soc_has_aiop(void)
|
||||||
|
{
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
static int load_mc_aiop_img(u64 aiop_fw_addr)
|
static int load_mc_aiop_img(u64 aiop_fw_addr)
|
||||||
{
|
{
|
||||||
u64 mc_ram_addr = mc_get_dram_addr();
|
u64 mc_ram_addr = mc_get_dram_addr();
|
||||||
@ -363,6 +369,9 @@ static int load_mc_aiop_img(u64 aiop_fw_addr)
|
|||||||
void *aiop_img;
|
void *aiop_img;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
/* Check if AIOP is available */
|
||||||
|
if (!soc_has_aiop())
|
||||||
|
return -ENODEV;
|
||||||
/*
|
/*
|
||||||
* Load the MC AIOP image in the MC private DRAM block:
|
* Load the MC AIOP image in the MC private DRAM block:
|
||||||
*/
|
*/
|
||||||
@ -1235,6 +1244,7 @@ static int do_fsl_mc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
|||||||
aiop_fw_addr = simple_strtoull(argv[3], NULL,
|
aiop_fw_addr = simple_strtoull(argv[3], NULL,
|
||||||
16);
|
16);
|
||||||
|
|
||||||
|
/* if SoC doesn't have AIOP, err = -ENODEV */
|
||||||
err = load_mc_aiop_img(aiop_fw_addr);
|
err = load_mc_aiop_img(aiop_fw_addr);
|
||||||
if (!err)
|
if (!err)
|
||||||
printf("fsl-mc: AIOP FW applied\n");
|
printf("fsl-mc: AIOP FW applied\n");
|
||||||
|
@ -7,4 +7,3 @@
|
|||||||
obj-y += ldpaa_wriop.o
|
obj-y += ldpaa_wriop.o
|
||||||
obj-y += ldpaa_eth.o
|
obj-y += ldpaa_eth.o
|
||||||
obj-$(CONFIG_LS2080A) += ls2080a.o
|
obj-$(CONFIG_LS2080A) += ls2080a.o
|
||||||
obj-$(CONFIG_LS2085A) += ls2080a.o
|
|
||||||
|
@ -171,10 +171,9 @@ unsigned long long get_qixis_addr(void);
|
|||||||
#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
|
#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
|
||||||
#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
|
#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
|
||||||
#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
|
#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
|
||||||
#ifdef CONFIG_LS2085A
|
/* For LS2085A */
|
||||||
#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
|
#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
|
||||||
#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
|
#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
|
||||||
#endif
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Carve out a DDR region which will not be used by u-boot/Linux
|
* Carve out a DDR region which will not be used by u-boot/Linux
|
||||||
@ -198,10 +197,6 @@ unsigned long long get_qixis_addr(void);
|
|||||||
#define FSL_PCIE_COMPAT "fsl,ls2080a-pcie"
|
#define FSL_PCIE_COMPAT "fsl,ls2080a-pcie"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_LS2085A
|
|
||||||
#define FSL_PCIE_COMPAT "fsl,ls2085a-pcie"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define CONFIG_SYS_PCI_64BIT
|
#define CONFIG_SYS_PCI_64BIT
|
||||||
|
|
||||||
#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
|
#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
|
||||||
|
@ -9,15 +9,8 @@
|
|||||||
|
|
||||||
#include "ls2080a_common.h"
|
#include "ls2080a_common.h"
|
||||||
|
|
||||||
#ifdef CONFIG_LS2080A
|
|
||||||
#define CONFIG_IDENT_STRING " LS2080A-EMU"
|
#define CONFIG_IDENT_STRING " LS2080A-EMU"
|
||||||
#define CONFIG_BOOTP_VCI_STRING "U-Boot.LS2080A-EMU"
|
#define CONFIG_BOOTP_VCI_STRING "U-Boot.LS2080A-EMU"
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef CONFIG_LS2085A
|
|
||||||
#define CONFIG_IDENT_STRING " LS2085A-EMU"
|
|
||||||
#define CONFIG_BOOTP_VCI_STRING "U-Boot.LS2085A-EMU"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define CONFIG_SYS_CLK_FREQ 100000000
|
#define CONFIG_SYS_CLK_FREQ 100000000
|
||||||
#define CONFIG_DDR_CLK_FREQ 133333333
|
#define CONFIG_DDR_CLK_FREQ 133333333
|
||||||
|
@ -9,15 +9,8 @@
|
|||||||
|
|
||||||
#include "ls2080a_common.h"
|
#include "ls2080a_common.h"
|
||||||
|
|
||||||
#ifdef CONFIG_LS2080A
|
|
||||||
#define CONFIG_IDENT_STRING " LS2080A-SIMU"
|
#define CONFIG_IDENT_STRING " LS2080A-SIMU"
|
||||||
#define CONFIG_BOOTP_VCI_STRING "U-Boot.LS2080A-SIMU"
|
#define CONFIG_BOOTP_VCI_STRING "U-Boot.LS2080A-SIMU"
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef CONFIG_LS2085A
|
|
||||||
#define CONFIG_IDENT_STRING " LS2085A-SIMU"
|
|
||||||
#define CONFIG_BOOTP_VCI_STRING "U-Boot.LS2085A-SIMU"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define CONFIG_SYS_CLK_FREQ 100000000
|
#define CONFIG_SYS_CLK_FREQ 100000000
|
||||||
#define CONFIG_DDR_CLK_FREQ 133333333
|
#define CONFIG_DDR_CLK_FREQ 133333333
|
||||||
|
@ -55,7 +55,7 @@ struct fsl_xhci {
|
|||||||
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
|
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
|
||||||
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
|
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
|
||||||
#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
|
#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
|
||||||
#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
|
#elif defined(CONFIG_LS2080A)
|
||||||
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR
|
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR
|
||||||
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR
|
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR
|
||||||
#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
|
#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
|
||||||
|
Loading…
Reference in New Issue
Block a user