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Merge branch 'master' of /home/wd/git/u-boot/master/

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This commit is contained in:
Wolfgang Denk 2008-01-09 21:34:46 +01:00
commit 3b93020d74
160 changed files with 12441 additions and 5034 deletions
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32
.gitignore vendored
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@ -1,13 +1,41 @@
#
# NOTE! Don't add files that are generated in specific
# subdirectories here. Add them in the ".gitignore" file
# in that subdirectory instead.
#
# Normal rules
#
*.rej
*.orig
*.a
*.o
*.depend
System.map
#
# Top-level generic files
#
/System.map
/u-boot
/u-boot.map
/u-boot.bin
/u-boot.srec
#
# Generated files
#
*.depend
/LOG
/errlog
/reloc_off
# stgit generated dirs
patches-*
# quilt's files
patches
series
# cscope files
cscope.*

2810
CHANGELOG
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File diff suppressed because it is too large Load Diff

5
CREDITS
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@ -303,6 +303,11 @@ D: Support for Nios Stratix Development Kit (DK-1S10)
D: Support for SSV ADNP/ESC1 (Nios Cyclone)
W: http://www.li-pro.net
N: Dave Liu
E: daveliu@freescale.com
D: Support for MPC832x, MPC8360, MPC837x
W: www.freescale.com
N: Raymond Lo
E: lo@routefree.com
D: Support for DOS partitions

2
MAINTAINERS
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@ -227,7 +227,9 @@ The LEOX team <team@leox.org>
Dave Liu <daveliu@freescale.com>
MPC832XEMDS MPC832x
MPC8360EMDS MPC8360
MPC837XEMDS MPC837x
Nye Liu <nyet@zumanetworks.com>

3
MAKEALL
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@ -313,6 +313,7 @@ LIST_83xx=" \
MPC8349ITXGP \
MPC8360EMDS \
MPC8360EMDS_ATM \
MPC837XEMDS \
sbc8349 \
TQM834x \
"
@ -348,6 +349,7 @@ LIST_85xx=" \
#########################################################################
LIST_86xx=" \
MPC8610HPCD \
MPC8641HPCN \
sbc8641d \
"
@ -483,6 +485,7 @@ LIST_ARM10=" \
LIST_ARM11=" \
cp1136 \
omap2420h4 \
apollon \
"
#########################################################################

18
Makefile
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@ -1922,6 +1922,16 @@ MPC8360EMDS_ATM_config: unconfig
fi ;
@$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds freescale
MPC837XEMDS_config \
MPC837XEMDS_HOST_config: unconfig
@mkdir -p $(obj)include
@echo "" >$(obj)include/config.h ; \
if [ "$(findstring _HOST_,$@)" ] ; then \
echo -n "... PCI HOST " ; \
echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \
fi ;
@$(MKCONFIG) -a MPC837XEMDS ppc mpc83xx mpc837xemds freescale
sbc8349_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc83xx sbc8349
@ -2061,6 +2071,9 @@ TQM8560_config: unconfig
## MPC86xx Systems
#########################################################################
MPC8610HPCD_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8610hpcd freescale
MPC8641HPCN_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8641hpcn freescale
@ -2448,9 +2461,12 @@ zylonite_config :
#########################################################################
## ARM1136 Systems
#########################################################################
omap2420h4_config : unconfig
omap2420h4_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4
apollon_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm1136 apollon
#========================================================================
# i386
#========================================================================

21
README
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@ -1377,15 +1377,24 @@ The following options need to be configured:
SPI configuration items (port pins to use, etc). For
an example, see include/configs/sacsng.h.
- FPGA Support: CONFIG_FPGA_COUNT
- FPGA Support: CONFIG_FPGA
Enables FPGA subsystem.
CONFIG_FPGA_<vendor>
Enables support for specific chip vendors.
(ALTERA, XILINX)
CONFIG_FPGA_<family>
Enables support for FPGA family.
(SPARTAN2, SPARTAN3, VIRTEX2, CYCLONE2, ACEX1K, ACEX)
CONFIG_FPGA_COUNT
Specify the number of FPGA devices to support.
CONFIG_FPGA
Used to specify the types of FPGA devices. For example,
#define CONFIG_FPGA CFG_XILINX_VIRTEX2
CFG_FPGA_PROG_FEEDBACK
Enable printing of hash marks during FPGA configuration.

14
board/amcc/katmai/katmai.c
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@ -1,5 +1,5 @@
/*
* (C) Copyright 2007
* (C) Copyright 2007-2008
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
@ -246,6 +246,18 @@ int checkboard (void)
return 0;
}
/*
* Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
* board specific values.
*/
u32 ddr_wrdtr(u32 default_val) {
return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
}
u32 ddr_clktr(u32 default_val) {
return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
}
#if defined(CFG_DRAM_TEST)
int testdram (void)
{

344
board/amcc/sequoia/sdram.c
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@ -33,343 +33,11 @@
#include <asm/io.h>
#include <ppc440.h>
#include "sdram.h"
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
defined(CONFIG_DDR_DATA_EYE)
/*-----------------------------------------------------------------------------+
* wait_for_dlllock.
+----------------------------------------------------------------------------*/
static int wait_for_dlllock(void)
{
unsigned long val;
int wait = 0;
/* -----------------------------------------------------------+
* Wait for the DCC master delay line to finish calibration
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_17);
val = DDR0_17_DLLLOCKREG_UNLOCKED;
while (wait != 0xffff) {
val = mfdcr(ddrcfgd);
if ((val & DDR0_17_DLLLOCKREG_MASK) == DDR0_17_DLLLOCKREG_LOCKED)
/* dlllockreg bit on */
return 0;
else
wait++;
}
debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val);
debug("Waiting for dlllockreg bit to raise\n");
return -1;
}
#endif
#if defined(CONFIG_DDR_DATA_EYE)
/*-----------------------------------------------------------------------------+
* wait_for_dram_init_complete.
+----------------------------------------------------------------------------*/
int wait_for_dram_init_complete(void)
{
unsigned long val;
int wait = 0;
/* --------------------------------------------------------------+
* Wait for 'DRAM initialization complete' bit in status register
* -------------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_00);
while (wait != 0xffff) {
val = mfdcr(ddrcfgd);
if ((val & DDR0_00_INT_STATUS_BIT6) == DDR0_00_INT_STATUS_BIT6)
/* 'DRAM initialization complete' bit */
return 0;
else
wait++;
}
debug("DRAM initialization complete bit in status register did not rise\n");
return -1;
}
#define NUM_TRIES 64
#define NUM_READS 10
/*-----------------------------------------------------------------------------+
* denali_core_search_data_eye.
+----------------------------------------------------------------------------*/
void denali_core_search_data_eye(unsigned long memory_size)
{
int k, j;
u32 val;
u32 wr_dqs_shift, dqs_out_shift, dll_dqs_delay_X;
u32 max_passing_cases = 0, wr_dqs_shift_with_max_passing_cases = 0;
u32 passing_cases = 0, dll_dqs_delay_X_sw_val = 0;
u32 dll_dqs_delay_X_start_window = 0, dll_dqs_delay_X_end_window = 0;
volatile u32 *ram_pointer;
u32 test[NUM_TRIES] = {
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
ram_pointer = (volatile u32 *)(CFG_SDRAM_BASE);
for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) {
/*for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) {*/
/* -----------------------------------------------------------+
* De-assert 'start' parameter.
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_02);
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
mtdcr(ddrcfgd, val);
/* -----------------------------------------------------------+
* Set 'wr_dqs_shift'
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_09);
val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
mtdcr(ddrcfgd, val);
/* -----------------------------------------------------------+
* Set 'dqs_out_shift' = wr_dqs_shift + 32
* ----------------------------------------------------------*/
dqs_out_shift = wr_dqs_shift + 32;
mtdcr(ddrcfga, DDR0_22);
val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
mtdcr(ddrcfgd, val);
passing_cases = 0;
for (dll_dqs_delay_X = 1; dll_dqs_delay_X < 64; dll_dqs_delay_X++) {
/*for (dll_dqs_delay_X=1; dll_dqs_delay_X<128; dll_dqs_delay_X++) {*/
/* -----------------------------------------------------------+
* Set 'dll_dqs_delay_X'.
* ----------------------------------------------------------*/
/* dll_dqs_delay_0 */
mtdcr(ddrcfga, DDR0_17);
val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
/* dll_dqs_delay_1 to dll_dqs_delay_4 */
mtdcr(ddrcfga, DDR0_18);
val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
/* dll_dqs_delay_5 to dll_dqs_delay_8 */
mtdcr(ddrcfga, DDR0_19);
val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
ppcMsync();
ppcMbar();
/* -----------------------------------------------------------+
* Assert 'start' parameter.
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_02);
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
mtdcr(ddrcfgd, val);
ppcMsync();
ppcMbar();
/* -----------------------------------------------------------+
* Wait for the DCC master delay line to finish calibration
* ----------------------------------------------------------*/
if (wait_for_dlllock() != 0) {
printf("dlllock did not occur !!!\n");
printf("denali_core_search_data_eye!!!\n");
printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
wr_dqs_shift, dll_dqs_delay_X);
hang();
}
ppcMsync();
ppcMbar();
if (wait_for_dram_init_complete() != 0) {
printf("dram init complete did not occur !!!\n");
printf("denali_core_search_data_eye!!!\n");
printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
wr_dqs_shift, dll_dqs_delay_X);
hang();
}
udelay(100); /* wait 100us to ensure init is really completed !!! */
/* write values */
for (j=0; j<NUM_TRIES; j++) {
ram_pointer[j] = test[j];
/* clear any cache at ram location */
__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
}
/* read values back */
for (j=0; j<NUM_TRIES; j++) {
for (k=0; k<NUM_READS; k++) {
/* clear any cache at ram location */
__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
if (ram_pointer[j] != test[j])
break;
}
/* read error */
if (k != NUM_READS)
break;
}
/* See if the dll_dqs_delay_X value passed.*/
if (j < NUM_TRIES) {
/* Failed */
passing_cases = 0;
/* break; */
} else {
/* Passed */
if (passing_cases == 0)
dll_dqs_delay_X_sw_val = dll_dqs_delay_X;
passing_cases++;
if (passing_cases >= max_passing_cases) {
max_passing_cases = passing_cases;
wr_dqs_shift_with_max_passing_cases = wr_dqs_shift;
dll_dqs_delay_X_start_window = dll_dqs_delay_X_sw_val;
dll_dqs_delay_X_end_window = dll_dqs_delay_X;
}
}
/* -----------------------------------------------------------+
* De-assert 'start' parameter.
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_02);
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
mtdcr(ddrcfgd, val);
} /* for (dll_dqs_delay_X=0; dll_dqs_delay_X<128; dll_dqs_delay_X++) */
} /* for (wr_dqs_shift=0; wr_dqs_shift<96; wr_dqs_shift++) */
/* -----------------------------------------------------------+
* Largest passing window is now detected.
* ----------------------------------------------------------*/
/* Compute dll_dqs_delay_X value */
dll_dqs_delay_X = (dll_dqs_delay_X_end_window + dll_dqs_delay_X_start_window) / 2;
wr_dqs_shift = wr_dqs_shift_with_max_passing_cases;
debug("DQS calibration - Window detected:\n");
debug("max_passing_cases = %d\n", max_passing_cases);
debug("wr_dqs_shift = %d\n", wr_dqs_shift);
debug("dll_dqs_delay_X = %d\n", dll_dqs_delay_X);
debug("dll_dqs_delay_X window = %d - %d\n",
dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window);
/* -----------------------------------------------------------+
* De-assert 'start' parameter.
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_02);
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
mtdcr(ddrcfgd, val);
/* -----------------------------------------------------------+
* Set 'wr_dqs_shift'
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_09);
val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
mtdcr(ddrcfgd, val);
debug("DDR0_09=0x%08lx\n", val);
/* -----------------------------------------------------------+
* Set 'dqs_out_shift' = wr_dqs_shift + 32
* ----------------------------------------------------------*/
dqs_out_shift = wr_dqs_shift + 32;
mtdcr(ddrcfga, DDR0_22);
val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
mtdcr(ddrcfgd, val);
debug("DDR0_22=0x%08lx\n", val);
/* -----------------------------------------------------------+
* Set 'dll_dqs_delay_X'.
* ----------------------------------------------------------*/
/* dll_dqs_delay_0 */
mtdcr(ddrcfga, DDR0_17);
val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
debug("DDR0_17=0x%08lx\n", val);
/* dll_dqs_delay_1 to dll_dqs_delay_4 */
mtdcr(ddrcfga, DDR0_18);
val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
debug("DDR0_18=0x%08lx\n", val);
/* dll_dqs_delay_5 to dll_dqs_delay_8 */
mtdcr(ddrcfga, DDR0_19);
val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
debug("DDR0_19=0x%08lx\n", val);
/* -----------------------------------------------------------+
* Assert 'start' parameter.
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_02);
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
mtdcr(ddrcfgd, val);
ppcMsync();
ppcMbar();
/* -----------------------------------------------------------+
* Wait for the DCC master delay line to finish calibration
* ----------------------------------------------------------*/
if (wait_for_dlllock() != 0) {
printf("dlllock did not occur !!!\n");
hang();
}
ppcMsync();
ppcMbar();
if (wait_for_dram_init_complete() != 0) {
printf("dram init complete did not occur !!!\n");
hang();
}
udelay(100); /* wait 100us to ensure init is really completed !!! */
}
#endif /* CONFIG_DDR_DATA_EYE */
* Prototypes
*-----------------------------------------------------------------------------*/
extern int denali_wait_for_dlllock(void);
extern void denali_core_search_data_eye(void);
#if defined(CONFIG_NAND_SPL)
/* Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big
@ -428,14 +96,14 @@ long int initdram (int board_type)
mtsdram(DDR0_44, 0x00000003);
mtsdram(DDR0_02, 0x00000001);
wait_for_dlllock();
denali_wait_for_dlllock();
#endif /* #ifndef CONFIG_NAND_U_BOOT */
#ifdef CONFIG_DDR_DATA_EYE
/* -----------------------------------------------------------+
* Perform data eye search if requested.
* ----------------------------------------------------------*/
denali_core_search_data_eye(CFG_MBYTES_SDRAM << 20);
denali_core_search_data_eye();
#endif
return (CFG_MBYTES_SDRAM << 20);

505
board/amcc/sequoia/sdram.h
View File

@ -1,505 +0,0 @@
/*
* (C) Copyright 2006
* Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
* Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
* Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _SPD_SDRAM_DENALI_H_
#define _SPD_SDRAM_DENALI_H_
#define ppcMsync sync
#define ppcMbar eieio
/* General definitions */
#define MAX_SPD_BYTE 128 /* highest SPD byte # to read */
#define DENALI_REG_NUMBER 45 /* 45 Regs in PPC440EPx Denali Core */
#define SUPPORTED_DIMMS_NB 7 /* Number of supported DIMM modules types */
#define SDRAM_NONE 0 /* No DIMM detected in Slot */
#define MAXRANKS 2 /* 2 ranks maximum */
/* Supported PLB Frequencies */
#define PLB_FREQ_133MHZ 133333333
#define PLB_FREQ_152MHZ 152000000
#define PLB_FREQ_160MHZ 160000000
#define PLB_FREQ_166MHZ 166666666
/* Denali Core Registers */
#define SDRAM_DCR_BASE 0x10
#define DDR_DCR_BASE 0x10
#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */
#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */
/*-----------------------------------------------------------------------------+
| Values for ddrcfga register - indirect addressing of these regs
+-----------------------------------------------------------------------------*/
#define DDR0_00 0x00
#define DDR0_00_INT_ACK_MASK 0x7F000000 /* Write only */
#define DDR0_00_INT_ACK_ALL 0x7F000000
#define DDR0_00_INT_ACK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
#define DDR0_00_INT_ACK_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
/* Status */
#define DDR0_00_INT_STATUS_MASK 0x00FF0000 /* Read only */
/* Bit0. A single access outside the defined PHYSICAL memory space detected. */
#define DDR0_00_INT_STATUS_BIT0 0x00010000
/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */
#define DDR0_00_INT_STATUS_BIT1 0x00020000
/* Bit2. Single correctable ECC event detected */
#define DDR0_00_INT_STATUS_BIT2 0x00040000
/* Bit3. Multiple correctable ECC events detected. */
#define DDR0_00_INT_STATUS_BIT3 0x00080000
/* Bit4. Single uncorrectable ECC event detected. */
#define DDR0_00_INT_STATUS_BIT4 0x00100000
/* Bit5. Multiple uncorrectable ECC events detected. */
#define DDR0_00_INT_STATUS_BIT5 0x00200000
/* Bit6. DRAM initialization complete. */
#define DDR0_00_INT_STATUS_BIT6 0x00400000
/* Bit7. Logical OR of all lower bits. */
#define DDR0_00_INT_STATUS_BIT7 0x00800000
#define DDR0_00_INT_STATUS_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
#define DDR0_00_INT_STATUS_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
#define DDR0_00_DLL_INCREMENT_MASK 0x00007F00
#define DDR0_00_DLL_INCREMENT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_00_DLL_INCREMENT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_00_DLL_START_POINT_MASK 0x0000007F
#define DDR0_00_DLL_START_POINT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_00_DLL_START_POINT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_01 0x01
#define DDR0_01_PLB0_DB_CS_LOWER_MASK 0x1F000000
#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
#define DDR0_01_PLB0_DB_CS_UPPER_MASK 0x001F0000
#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n) ((((unsigned long)(n))>>16)&0x1F)
#define DDR0_01_OUT_OF_RANGE_TYPE_MASK 0x00000700 /* Read only */
#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
#define DDR0_01_INT_MASK_MASK 0x000000FF
#define DDR0_01_INT_MASK_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
#define DDR0_01_INT_MASK_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
#define DDR0_01_INT_MASK_ALL_ON 0x000000FF
#define DDR0_01_INT_MASK_ALL_OFF 0x00000000
#define DDR0_02 0x02
#define DDR0_02_MAX_CS_REG_MASK 0x02000000 /* Read only */
#define DDR0_02_MAX_CS_REG_ENCODE(n) ((((unsigned long)(n))&0x2)<<24)
#define DDR0_02_MAX_CS_REG_DECODE(n) ((((unsigned long)(n))>>24)&0x2)
#define DDR0_02_MAX_COL_REG_MASK 0x000F0000 /* Read only */
#define DDR0_02_MAX_COL_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<16)
#define DDR0_02_MAX_COL_REG_DECODE(n) ((((unsigned long)(n))>>16)&0xF)
#define DDR0_02_MAX_ROW_REG_MASK 0x00000F00 /* Read only */
#define DDR0_02_MAX_ROW_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
#define DDR0_02_MAX_ROW_REG_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
#define DDR0_02_START_MASK 0x00000001
#define DDR0_02_START_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
#define DDR0_02_START_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
#define DDR0_02_START_OFF 0x00000000
#define DDR0_02_START_ON 0x00000001
#define DDR0_03 0x03
#define DDR0_03_BSTLEN_MASK 0x07000000
#define DDR0_03_BSTLEN_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
#define DDR0_03_BSTLEN_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
#define DDR0_03_CASLAT_MASK 0x00070000
#define DDR0_03_CASLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
#define DDR0_03_CASLAT_LIN_MASK 0x00000F00
#define DDR0_03_CASLAT_LIN_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
#define DDR0_03_CASLAT_LIN_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
#define DDR0_03_INITAREF_MASK 0x0000000F
#define DDR0_03_INITAREF_ENCODE(n) ((((unsigned long)(n))&0xF)<<0)
#define DDR0_03_INITAREF_DECODE(n) ((((unsigned long)(n))>>0)&0xF)
#define DDR0_04 0x04
#define DDR0_04_TRC_MASK 0x1F000000
#define DDR0_04_TRC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
#define DDR0_04_TRC_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
#define DDR0_04_TRRD_MASK 0x00070000
#define DDR0_04_TRRD_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
#define DDR0_04_TRRD_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
#define DDR0_04_TRTP_MASK 0x00000700
#define DDR0_04_TRTP_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
#define DDR0_04_TRTP_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
#define DDR0_05 0x05
#define DDR0_05_TMRD_MASK 0x1F000000
#define DDR0_05_TMRD_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
#define DDR0_05_TMRD_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
#define DDR0_05_TEMRS_MASK 0x00070000
#define DDR0_05_TEMRS_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
#define DDR0_05_TEMRS_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
#define DDR0_05_TRP_MASK 0x00000F00
#define DDR0_05_TRP_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
#define DDR0_05_TRP_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
#define DDR0_05_TRAS_MIN_MASK 0x000000FF
#define DDR0_05_TRAS_MIN_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
#define DDR0_05_TRAS_MIN_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
#define DDR0_06 0x06
#define DDR0_06_WRITEINTERP_MASK 0x01000000
#define DDR0_06_WRITEINTERP_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
#define DDR0_06_WRITEINTERP_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
#define DDR0_06_TWTR_MASK 0x00070000
#define DDR0_06_TWTR_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
#define DDR0_06_TWTR_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
#define DDR0_06_TDLL_MASK 0x0000FF00
#define DDR0_06_TDLL_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
#define DDR0_06_TDLL_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
#define DDR0_06_TRFC_MASK 0x0000007F
#define DDR0_06_TRFC_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_06_TRFC_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_07 0x07
#define DDR0_07_NO_CMD_INIT_MASK 0x01000000
#define DDR0_07_NO_CMD_INIT_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
#define DDR0_07_NO_CMD_INIT_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
#define DDR0_07_TFAW_MASK 0x001F0000
#define DDR0_07_TFAW_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
#define DDR0_07_TFAW_DECODE(n) ((((unsigned long)(n))>>16)&0x1F)
#define DDR0_07_AUTO_REFRESH_MODE_MASK 0x00000100
#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
#define DDR0_07_AREFRESH_MASK 0x00000001
#define DDR0_07_AREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
#define DDR0_07_AREFRESH_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
#define DDR0_08 0x08
#define DDR0_08_WRLAT_MASK 0x07000000
#define DDR0_08_WRLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
#define DDR0_08_WRLAT_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
#define DDR0_08_TCPD_MASK 0x00FF0000
#define DDR0_08_TCPD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
#define DDR0_08_TCPD_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
#define DDR0_08_DQS_N_EN_MASK 0x00000100
#define DDR0_08_DQS_N_EN_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
#define DDR0_08_DQS_N_EN_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
#define DDR0_08_DDRII_SDRAM_MODE_MASK 0x00000001
#define DDR0_08_DDRII_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
#define DDR0_08_DDRII_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
#define DDR0_09 0x09
#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK 0x1F000000
#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
#define DDR0_09_RTT_0_MASK 0x00030000
#define DDR0_09_RTT_0_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
#define DDR0_09_RTT_0_DECODE(n) ((((unsigned long)(n))>>16)&0x3)
#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK 0x00007F00
#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_09_WR_DQS_SHIFT_MASK 0x0000007F
#define DDR0_09_WR_DQS_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_09_WR_DQS_SHIFT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_10 0x0A
#define DDR0_10_WRITE_MODEREG_MASK 0x00010000 /* Write only */
#define DDR0_10_WRITE_MODEREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
#define DDR0_10_WRITE_MODEREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
#define DDR0_10_CS_MAP_MASK 0x00000300
#define DDR0_10_CS_MAP_NO_MEM 0x00000000
#define DDR0_10_CS_MAP_RANK0_INSTALLED 0x00000100
#define DDR0_10_CS_MAP_RANK1_INSTALLED 0x00000200
#define DDR0_10_CS_MAP_ENCODE(n) ((((unsigned long)(n))&0x3)<<8)
#define DDR0_10_CS_MAP_DECODE(n) ((((unsigned long)(n))>>8)&0x3)
#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK 0x0000001F
#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<0)
#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x1F)
#define DDR0_11 0x0B
#define DDR0_11_SREFRESH_MASK 0x01000000
#define DDR0_11_SREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
#define DDR0_11_SREFRESH_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
#define DDR0_11_TXSNR_MASK 0x00FF0000
#define DDR0_11_TXSNR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
#define DDR0_11_TXSNR_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
#define DDR0_11_TXSR_MASK 0x0000FF00
#define DDR0_11_TXSR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
#define DDR0_11_TXSR_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
#define DDR0_12 0x0C
#define DDR0_12_TCKE_MASK 0x0000007
#define DDR0_12_TCKE_ENCODE(n) ((((unsigned long)(n))&0x7)<<0)
#define DDR0_12_TCKE_DECODE(n) ((((unsigned long)(n))>>0)&0x7)
#define DDR0_13 0x0D
#define DDR0_14 0x0E
#define DDR0_14_DLL_BYPASS_MODE_MASK 0x01000000
#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
#define DDR0_14_DLL_BYPASS_MODE_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
#define DDR0_14_REDUC_MASK 0x00010000
#define DDR0_14_REDUC_64BITS 0x00000000
#define DDR0_14_REDUC_32BITS 0x00010000
#define DDR0_14_REDUC_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
#define DDR0_14_REDUC_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
#define DDR0_14_REG_DIMM_ENABLE_MASK 0x00000100
#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
#define DDR0_14_REG_DIMM_ENABLE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
#define DDR0_15 0x0F
#define DDR0_16 0x10
#define DDR0_17 0x11
#define DDR0_17_DLL_DQS_DELAY_0_MASK 0x7F000000
#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */
#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000
#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000
#define DDR0_17_DLLLOCKREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
#define DDR0_17_DLLLOCKREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
#define DDR0_17_DLL_LOCK_MASK 0x00007F00 /* Read only */
#define DDR0_17_DLL_LOCK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_17_DLL_LOCK_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_18 0x12
#define DDR0_18_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
#define DDR0_18_DLL_DQS_DELAY_4_MASK 0x7F000000
#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
#define DDR0_18_DLL_DQS_DELAY_3_MASK 0x007F0000
#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
#define DDR0_18_DLL_DQS_DELAY_2_MASK 0x00007F00
#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_18_DLL_DQS_DELAY_1_MASK 0x0000007F
#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_19 0x13
#define DDR0_19_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
#define DDR0_19_DLL_DQS_DELAY_8_MASK 0x7F000000
#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
#define DDR0_19_DLL_DQS_DELAY_7_MASK 0x007F0000
#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
#define DDR0_19_DLL_DQS_DELAY_6_MASK 0x00007F00
#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_19_DLL_DQS_DELAY_5_MASK 0x0000007F
#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_20 0x14
#define DDR0_20_DLL_DQS_BYPASS_3_MASK 0x7F000000
#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
#define DDR0_20_DLL_DQS_BYPASS_2_MASK 0x007F0000
#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
#define DDR0_20_DLL_DQS_BYPASS_1_MASK 0x00007F00
#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_20_DLL_DQS_BYPASS_0_MASK 0x0000007F
#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_21 0x15
#define DDR0_21_DLL_DQS_BYPASS_7_MASK 0x7F000000
#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
#define DDR0_21_DLL_DQS_BYPASS_6_MASK 0x007F0000
#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
#define DDR0_21_DLL_DQS_BYPASS_5_MASK 0x00007F00
#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_21_DLL_DQS_BYPASS_4_MASK 0x0000007F
#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_22 0x16
/* ECC */
#define DDR0_22_CTRL_RAW_MASK 0x03000000
#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not being used */
#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC checking is on, but no attempts to correct*/
#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* No ECC RAM storage available */
#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC checking and correcting on */
#define DDR0_22_CTRL_RAW_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
#define DDR0_22_CTRL_RAW_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000
#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
#define DDR0_22_DQS_OUT_SHIFT_MASK 0x00007F00
#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_22_DQS_OUT_SHIFT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_22_DLL_DQS_BYPASS_8_MASK 0x0000007F
#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_23 0x17
#define DDR0_23_ODT_RD_MAP_CS0_MASK 0x03000000
#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
#define DDR0_23_ECC_C_SYND_MASK 0x00FF0000 /* Read only */
#define DDR0_23_ECC_C_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
#define DDR0_23_ECC_C_SYND_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
#define DDR0_23_ECC_U_SYND_MASK 0x0000FF00 /* Read only */
#define DDR0_23_ECC_U_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
#define DDR0_23_ECC_U_SYND_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
#define DDR0_23_FWC_MASK 0x00000001 /* Write only */
#define DDR0_23_FWC_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
#define DDR0_23_FWC_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
#define DDR0_24 0x18
#define DDR0_24_RTT_PAD_TERMINATION_MASK 0x03000000
#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
#define DDR0_24_ODT_WR_MAP_CS1_MASK 0x00030000
#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>16)&0x3)
#define DDR0_24_ODT_RD_MAP_CS1_MASK 0x00000300
#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<8)
#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>8)&0x3)
#define DDR0_24_ODT_WR_MAP_CS0_MASK 0x00000003
#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<0)
#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>0)&0x3)
#define DDR0_25 0x19
#define DDR0_25_VERSION_MASK 0xFFFF0000 /* Read only */
#define DDR0_25_VERSION_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
#define DDR0_25_VERSION_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK 0x000003FF /* Read only */
#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
#define DDR0_26 0x1A
#define DDR0_26_TRAS_MAX_MASK 0xFFFF0000
#define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
#define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
#define DDR0_26_TREF_MASK 0x00003FFF
#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0)
#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF)
#define DDR0_27 0x1B
#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000
#define DDR0_27_EMRS_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16)
#define DDR0_27_EMRS_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF)
#define DDR0_27_TINIT_MASK 0x0000FFFF
#define DDR0_27_TINIT_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0)
#define DDR0_27_TINIT_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF)
#define DDR0_28 0x1C
#define DDR0_28_EMRS3_DATA_MASK 0x3FFF0000
#define DDR0_28_EMRS3_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16)
#define DDR0_28_EMRS3_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF)
#define DDR0_28_EMRS2_DATA_MASK 0x00003FFF
#define DDR0_28_EMRS2_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0)
#define DDR0_28_EMRS2_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF)
#define DDR0_29 0x1D
#define DDR0_30 0x1E
#define DDR0_31 0x1F
#define DDR0_31_XOR_CHECK_BITS_MASK 0x0000FFFF
#define DDR0_31_XOR_CHECK_BITS_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0)
#define DDR0_31_XOR_CHECK_BITS_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF)
#define DDR0_32 0x20
#define DDR0_32_OUT_OF_RANGE_ADDR_MASK 0xFFFFFFFF /* Read only */
#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
#define DDR0_33 0x21
#define DDR0_33_OUT_OF_RANGE_ADDR_MASK 0x00000001 /* Read only */
#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
#define DDR0_34 0x22
#define DDR0_34_ECC_U_ADDR_MASK 0xFFFFFFFF /* Read only */
#define DDR0_34_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
#define DDR0_34_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
#define DDR0_35 0x23
#define DDR0_35_ECC_U_ADDR_MASK 0x00000001 /* Read only */
#define DDR0_35_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
#define DDR0_35_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
#define DDR0_36 0x24
#define DDR0_36_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
#define DDR0_36_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
#define DDR0_36_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
#define DDR0_37 0x25
#define DDR0_37_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
#define DDR0_37_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
#define DDR0_37_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
#define DDR0_38 0x26
#define DDR0_38_ECC_C_ADDR_MASK 0xFFFFFFFF /* Read only */
#define DDR0_38_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
#define DDR0_38_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
#define DDR0_39 0x27
#define DDR0_39_ECC_C_ADDR_MASK 0x00000001 /* Read only */
#define DDR0_39_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
#define DDR0_39_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
#define DDR0_40 0x28
#define DDR0_40_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
#define DDR0_40_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
#define DDR0_40_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
#define DDR0_41 0x29
#define DDR0_41_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
#define DDR0_41_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
#define DDR0_41_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
#define DDR0_42 0x2A
#define DDR0_42_ADDR_PINS_MASK 0x07000000
#define DDR0_42_ADDR_PINS_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
#define DDR0_42_ADDR_PINS_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
#define DDR0_42_CASLAT_LIN_GATE_MASK 0x0000000F
#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n) ((((unsigned long)(n))&0xF)<<0)
#define DDR0_42_CASLAT_LIN_GATE_DECODE(n) ((((unsigned long)(n))>>0)&0xF)
#define DDR0_43 0x2B
#define DDR0_43_TWR_MASK 0x07000000
#define DDR0_43_TWR_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
#define DDR0_43_TWR_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
#define DDR0_43_APREBIT_MASK 0x000F0000
#define DDR0_43_APREBIT_ENCODE(n) ((((unsigned long)(n))&0xF)<<16)
#define DDR0_43_APREBIT_DECODE(n) ((((unsigned long)(n))>>16)&0xF)
#define DDR0_43_COLUMN_SIZE_MASK 0x00000700
#define DDR0_43_COLUMN_SIZE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
#define DDR0_43_COLUMN_SIZE_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
#define DDR0_43_EIGHT_BANK_MODE_MASK 0x00000001
#define DDR0_43_EIGHT_BANK_MODE_8_BANKS 0x00000001
#define DDR0_43_EIGHT_BANK_MODE_4_BANKS 0x00000000
#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
#define DDR0_43_EIGHT_BANK_MODE_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
#define DDR0_44 0x2C
#define DDR0_44_TRCD_MASK 0x000000FF
#define DDR0_44_TRCD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
#define DDR0_44_TRCD_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
#endif /* _SPD_SDRAM_DENALI_H_ */

45
board/amcc/sequoia/sequoia.c
View File

@ -26,8 +26,10 @@
#include <libfdt.h>
#include <fdt_support.h>
#include <ppc440.h>
#include <asm/gpio.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/ppc4xx-intvec.h>
DECLARE_GLOBAL_DATA_PTR;
@ -44,36 +46,6 @@ int board_early_init_f(void)
mtdcr(ebccfga, xbcfg);
mtdcr(ebccfgd, 0xb8400000);
/*--------------------------------------------------------------------
* Setup the GPIO pins
*-------------------------------------------------------------------*/
/* test-only: take GPIO init from pcs440ep ???? in config file */
out_be32((u32 *) GPIO0_OR, 0x00000000);
out_be32((u32 *) GPIO0_TCR, 0x0000000f);
out_be32((u32 *) GPIO0_OSRL, 0x50015400);
out_be32((u32 *) GPIO0_OSRH, 0x550050aa);
out_be32((u32 *) GPIO0_TSRL, 0x50015400);
out_be32((u32 *) GPIO0_TSRH, 0x55005000);
out_be32((u32 *) GPIO0_ISR1L, 0x50000000);
out_be32((u32 *) GPIO0_ISR1H, 0x00000000);
out_be32((u32 *) GPIO0_ISR2L, 0x00000000);
out_be32((u32 *) GPIO0_ISR2H, 0x00000100);
out_be32((u32 *) GPIO0_ISR3L, 0x00000000);
out_be32((u32 *) GPIO0_ISR3H, 0x00000000);
out_be32((u32 *) GPIO1_OR, 0x00000000);
out_be32((u32 *) GPIO1_TCR, 0xc2000000);
out_be32((u32 *) GPIO1_OSRL, 0x5c280000);
out_be32((u32 *) GPIO1_OSRH, 0x00000000);
out_be32((u32 *) GPIO1_TSRL, 0x0c000000);
out_be32((u32 *) GPIO1_TSRH, 0x00000000);
out_be32((u32 *) GPIO1_ISR1L, 0x00005550);
out_be32((u32 *) GPIO1_ISR1H, 0x00000000);
out_be32((u32 *) GPIO1_ISR2L, 0x00050000);
out_be32((u32 *) GPIO1_ISR2H, 0x00000000);
out_be32((u32 *) GPIO1_ISR3L, 0x01400000);
out_be32((u32 *) GPIO1_ISR3H, 0x00000000);
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
@ -416,6 +388,16 @@ int testdram(void)
}
#endif
#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
/*
* Assign interrupts to PCI devices.
*/
void sequoia_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
{
pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIR2);
}
#endif
/*************************************************************************
* pci_pre_init
*
@ -467,6 +449,9 @@ int pci_pre_init(struct pci_controller *hose)
addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
mtdcr(plb1_acr, addr);
#ifdef CONFIG_PCI_PNP
hose->fixup_irq = sequoia_pci_fixup_irq;
#endif
return 1;
}
#endif /* defined(CONFIG_PCI) */

48
board/apollon/Makefile Normal file
View File

@ -0,0 +1,48 @@
#
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := apollon.o mem.o sys_info.o
SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
include $(SRCTREE)/rules.mk
sinclude $(obj).depend

472
board/apollon/apollon.c Normal file
View File

@ -0,0 +1,472 @@
/*
* (C) Copyright 2005-2007
* Samsung Electronics.
* Kyungmin Park <kyungmin.park@samsung.com>
*
* Derived from omap2420
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/omap2420.h>
#include <asm/io.h>
#include <asm/arch/bits.h>
#include <asm/arch/mux.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/sys_info.h>
#include <asm/arch/mem.h>
#include <asm/mach-types.h>
void wait_for_command_complete(unsigned int wd_base);
DECLARE_GLOBAL_DATA_PTR;
#define write_config_reg(reg, value) \
do { \
writeb(value, reg); \
} while (0)
#define mask_config_reg(reg, mask) \
do { \
char value = readb(reg) & ~(mask); \
writeb(value, reg); \
} while (0)
/*******************************************************
* Routine: delay
* Description: spinning delay to use before udelay works
******************************************************/
static inline void delay(unsigned long loops)
{
__asm__("1:\n" "subs %0, %1, #1\n"
"bne 1b":"=r" (loops):"0"(loops));
}
/*****************************************
* Routine: board_init
* Description: Early hardware init.
*****************************************/
int board_init(void)
{
gpmc_init(); /* in SRAM or SDRM, finish GPMC */
gd->bd->bi_arch_number = 919;
/* adress of boot parameters */
gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0 + 0x100);
return 0;
}
/**********************************************************
* Routine: s_init
* Description: Does early system init of muxing and clocks.
* - Called path is with sram stack.
**********************************************************/
void s_init(void)
{
watchdog_init();
set_muxconf_regs();
delay(100);
peripheral_enable();
icache_enable();
}
/*******************************************************
* Routine: misc_init_r
* Description: Init ethernet (done here so udelay works)
********************************************************/
int misc_init_r(void)
{
ether_init(); /* better done here so timers are init'ed */
return (0);
}
/****************************************
* Routine: watchdog_init
* Description: Shut down watch dogs
*****************************************/
void watchdog_init(void)
{
/* There are 4 watch dogs. 1 secure, and 3 general purpose.
* The ROM takes care of the secure one. Of the 3 GP ones,
* 1 can reset us directly, the other 2 only generate MPU interrupts.
*/
__raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
wait_for_command_complete(WD2_BASE);
__raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
#define MPU_WD_CLOCKED 1
#if MPU_WD_CLOCKED
/* value 0x10 stick on aptix, BIT4 polarity seems oppsite */
__raw_writel(WD_UNLOCK1, WD3_BASE + WSPR);
wait_for_command_complete(WD3_BASE);
__raw_writel(WD_UNLOCK2, WD3_BASE + WSPR);
__raw_writel(WD_UNLOCK1, WD4_BASE + WSPR);
wait_for_command_complete(WD4_BASE);
__raw_writel(WD_UNLOCK2, WD4_BASE + WSPR);
#endif
}
/******************************************************
* Routine: wait_for_command_complete
* Description: Wait for posting to finish on watchdog
******************************************************/
void wait_for_command_complete(unsigned int wd_base)
{
int pending = 1;
do {
pending = __raw_readl(wd_base + WWPS);
} while (pending);
}
/*******************************************************************
* Routine:ether_init
* Description: take the Ethernet controller out of reset and wait
* for the EEPROM load to complete.
******************************************************************/
void ether_init(void)
{
#ifdef CONFIG_DRIVER_LAN91C96
int cnt = 20;
__raw_writeb(0x03, OMAP2420_CTRL_BASE + 0x0f2); /*protect->gpio74 */
__raw_writew(0x0, LAN_RESET_REGISTER);
do {
__raw_writew(0x1, LAN_RESET_REGISTER);
udelay(100);
if (cnt == 0) {
printf("1. eth reset err\n");
goto eth_reset_err_out;
}
--cnt;
} while (__raw_readw(LAN_RESET_REGISTER) != 0x1);
cnt = 20;
do {
__raw_writew(0x0, LAN_RESET_REGISTER);
udelay(100);
if (cnt == 0) {
printf("2. eth reset err\n");
goto eth_reset_err_out;
}
--cnt;
} while (__raw_readw(LAN_RESET_REGISTER) != 0x0000);
udelay(1000);
mask_config_reg(ETH_CONTROL_REG, 0x01);
udelay(1000);
eth_reset_err_out:
return;
#endif
}
/**********************************************
* Routine: dram_init
* Description: sets uboots idea of sdram size
**********************************************/
int dram_init(void)
{
unsigned int size0 = 0, size1 = 0;
u32 mtype, btype, rev = 0, cpu = 0;
#define NOT_EARLY 0
btype = get_board_type();
mtype = get_mem_type();
rev = get_cpu_rev();
cpu = get_cpu_type();
display_board_info(btype);
if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
/* init other chip select */
do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY);
}
size0 = get_sdr_cs_size(SDRC_CS0_OSET);
size1 = get_sdr_cs_size(SDRC_CS1_OSET);
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = size0;
#if CONFIG_NR_DRAM_BANKS > 1
gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + size0;
gd->bd->bi_dram[1].size = size1;
#endif
return 0;
}
/**********************************************************
* Routine: set_muxconf_regs
* Description: Setting up the configuration Mux registers
* specific to the hardware
*********************************************************/
void set_muxconf_regs(void)
{
muxSetupSDRC();
muxSetupGPMC();
muxSetupUsb0(); /* USB Device */
muxSetupUsbHost(); /* USB Host */
muxSetupUART1();
muxSetupLCD();
muxSetupMMCSD();
muxSetupTouchScreen();
}
/*****************************************************************
* Routine: peripheral_enable
* Description: Enable the clks & power for perifs (GPT2, UART1,...)
******************************************************************/
void peripheral_enable(void)
{
unsigned int v, if_clks = 0, func_clks = 0;
/* Enable GP2 timer. */
if_clks |= BIT4 | BIT3;
func_clks |= BIT4 | BIT3;
/* Sys_clk input OMAP2420_GPT2 */
v = __raw_readl(CM_CLKSEL2_CORE) | 0x4 | 0x2;
__raw_writel(v, CM_CLKSEL2_CORE);
__raw_writel(0x1, CM_CLKSEL_WKUP);
#ifdef CFG_NS16550
/* Enable UART1 clock */
func_clks |= BIT21;
if_clks |= BIT21;
#endif
/* Interface clocks on */
v = __raw_readl(CM_ICLKEN1_CORE) | if_clks;
__raw_writel(v, CM_ICLKEN1_CORE);
/* Functional Clocks on */
v = __raw_readl(CM_FCLKEN1_CORE) | func_clks;
__raw_writel(v, CM_FCLKEN1_CORE);
delay(1000);
#ifndef KERNEL_UPDATED
{
#define V1 0xffffffff
#define V2 0x00000007
__raw_writel(V1, CM_FCLKEN1_CORE);
__raw_writel(V2, CM_FCLKEN2_CORE);
__raw_writel(V1, CM_ICLKEN1_CORE);
__raw_writel(V1, CM_ICLKEN2_CORE);
}
#endif
}
/****************************************
* Routine: muxSetupUsb0 (ostboot)
* Description: Setup usb muxing
*****************************************/
void muxSetupUsb0(void)
{
mask_config_reg(CONTROL_PADCONF_USB0_PUEN, 0x1f);
mask_config_reg(CONTROL_PADCONF_USB0_VP, 0x1f);
mask_config_reg(CONTROL_PADCONF_USB0_VM, 0x1f);
mask_config_reg(CONTROL_PADCONF_USB0_RCV, 0x1f);
mask_config_reg(CONTROL_PADCONF_USB0_TXEN, 0x1f);
mask_config_reg(CONTROL_PADCONF_USB0_SE0, 0x1f);
mask_config_reg(CONTROL_PADCONF_USB0_DAT, 0x1f);
}
/****************************************
* Routine: muxSetupUSBHost (ostboot)
* Description: Setup USB Host muxing
*****************************************/
void muxSetupUsbHost(void)
{
/* V19 */
write_config_reg(CONTROL_PADCONF_USB1_RCV, 1);
/* W20 */
write_config_reg(CONTROL_PADCONF_USB1_TXEN, 1);
/* N14 */
write_config_reg(CONTROL_PADCONF_GPIO69, 3);
/* P15 */
write_config_reg(CONTROL_PADCONF_GPIO70, 3);
/* L18 */
write_config_reg(CONTROL_PADCONF_GPIO102, 3);
/* L19 */
write_config_reg(CONTROL_PADCONF_GPIO103, 3);
/* K15 */
write_config_reg(CONTROL_PADCONF_GPIO104, 3);
/* K14 */
write_config_reg(CONTROL_PADCONF_GPIO105, 3);
}
/****************************************
* Routine: muxSetupUART1 (ostboot)
* Description: Set up uart1 muxing
*****************************************/
void muxSetupUART1(void)
{
/* UART1_CTS pin configuration, PIN = D21, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_UART1_CTS, 0);
/* UART1_RTS pin configuration, PIN = H21, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_UART1_RTS, 0);
/* UART1_TX pin configuration, PIN = L20, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_UART1_TX, 0);
/* UART1_RX pin configuration, PIN = T21, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_UART1_RX, 0);
}
/****************************************
* Routine: muxSetupLCD (ostboot)
* Description: Setup lcd muxing
*****************************************/
void muxSetupLCD(void)
{
/* LCD_D0 pin configuration, PIN = Y7, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_D0, 0);
/* LCD_D1 pin configuration, PIN = P10 , Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_D1, 0);
/* LCD_D2 pin configuration, PIN = V8, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_D2, 0);
/* LCD_D3 pin configuration, PIN = Y8, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_D3, 0);
/* LCD_D4 pin configuration, PIN = W8, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_D4, 0);
/* LCD_D5 pin configuration, PIN = R10, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_D5, 0);
/* LCD_D6 pin configuration, PIN = Y9, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_D6, 0);
/* LCD_D7 pin configuration, PIN = V9, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_D7, 0);
/* LCD_D8 pin configuration, PIN = W9, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_D8, 0);
/* LCD_D9 pin configuration, PIN = P11, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_D9, 0);
/* LCD_D10 pin configuration, PIN = V10, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_D10, 0);
/* LCD_D11 pin configuration, PIN = Y10, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_D11, 0);
/* LCD_D12 pin configuration, PIN = W10, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_D12, 0);
/* LCD_D13 pin configuration, PIN = R11, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_D13, 0);
/* LCD_D14 pin configuration, PIN = V11, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_D14, 0);
/* LCD_D15 pin configuration, PIN = W11, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_D15, 0);
/* LCD_D16 pin configuration, PIN = P12, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_D16, 0);
/* LCD_D17 pin configuration, PIN = R12, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_D17, 0);
/* LCD_PCLK pin configuration, PIN = W6, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_PCLK, 0);
/* LCD_VSYNC pin configuration, PIN = V7, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_VSYNC, 0);
/* LCD_HSYNC pin configuration, PIN = Y6, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_HSYNC, 0);
/* LCD_ACBIAS pin configuration, PIN = W7, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_ACBIAS, 0);
}
/****************************************
* Routine: muxSetupMMCSD (ostboot)
* Description: set up MMC muxing
*****************************************/
void muxSetupMMCSD(void)
{
/* SDMMC_CLKI pin configuration, PIN = H15, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_MMC_CLKI, 0);
/* SDMMC_CLKO pin configuration, PIN = G19, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_MMC_CLKO, 0);
/* SDMMC_CMD pin configuration, PIN = H18, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_MMC_CMD, 0);
/* SDMMC_DAT0 pin configuration, PIN = F20, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_MMC_DAT0, 0);
/* SDMMC_DAT1 pin configuration, PIN = H14, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_MMC_DAT1, 0);
/* SDMMC_DAT2 pin configuration, PIN = E19, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_MMC_DAT2, 0);
/* SDMMC_DAT3 pin configuration, PIN = D19, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_MMC_DAT3, 0);
/* SDMMC_DDIR0 pin configuration, PIN = F19, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR0, 0);
/* SDMMC_DDIR1 pin configuration, PIN = E20, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR1, 0);
/* SDMMC_DDIR2 pin configuration, PIN = F18, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR2, 0);
/* SDMMC_DDIR3 pin configuration, PIN = E18, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR3, 0);
/* SDMMC_CDIR pin configuration, PIN = G18, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_MMC_CMD_DIR, 0);
}
/******************************************
* Routine: muxSetupTouchScreen (ostboot)
* Description: Set up touch screen muxing
*******************************************/
void muxSetupTouchScreen(void)
{
/* SPI1_CLK pin configuration, PIN = U18, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_SPI1_CLK, 0);
/* SPI1_MOSI pin configuration, PIN = V20, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_SPI1_SIMO, 0);
/* SPI1_MISO pin configuration, PIN = T18, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_SPI1_SOMI, 0);
/* SPI1_nCS0 pin configuration, PIN = U19, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_SPI1_NCS0, 0);
#define CONTROL_PADCONF_GPIO85 CONTROL_PADCONF_SPI1_NCS1
/* PEN_IRQ pin configuration, PIN = N15, Mode = 3, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_GPIO85, 3);
}
/***************************************************************
* Routine: muxSetupGPMC (ostboot)
* Description: Configures balls which cam up in protected mode
***************************************************************/
void muxSetupGPMC(void)
{
/* gpmc_io_dir, MCR */
writel(0x4800008C, 0x19000000);
/* NOR FLASH CS0 */
/* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode 0; Byte-3 */
write_config_reg(CONTROL_PADCONF_GPMC_D2_BYTE3, 0);
/* MPDB(Multi Port Debug Port) CS1 */
/* signal - gpmc_ncs1; pin - N8; offset - 0x008D; mode 0; Byte-1 */
write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE1, 0);
/* signal - Gpmc_ncs2; pin - E2; offset - 0x008E; mode 0; Byte-2 */
write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE2, 0);
/* signal - Gpmc_ncs3; pin - N2; offset - 0x008F; mode 0; Byte-3 */
write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE3, 0);
/* signal - Gpmc_ncs4; pin - ??; offset - 0x0090; mode 0; Byte-4 */
write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE4, 0);
/* signal - Gpmc_ncs5; pin - ??; offset - 0x0091; mode 0; Byte-5 */
write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE5, 0);
/* signal - Gpmc_ncs6; pin - ??; offset - 0x0092; mode 0; Byte-6 */
write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE6, 0);
/* signal - Gpmc_ncs7; pin - ??; offset - 0x0093; mode 0; Byte-7 */
write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE7, 0);
}
/****************************************************************
* Routine: muxSetupSDRC (ostboot)
* Description: Configures balls which come up in protected mode
****************************************************************/
void muxSetupSDRC(void)
{
/* It's set by IPL */
}

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board/apollon/config.mk Normal file
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#
# (C) Copyright 2005-2007
# Samsung Electronics
#
# Samsung December board with OMAP2420 (ARM1136) cpu
# see http://www.ti.com/ for more information on Texas Instruments
#
# December has 1 bank of 128MB mDDR-SDRAM on CS0
# December has 1 bank of 00MB mDDR-SDRAM on CS1
# Physical Address:
# 8000'0000 (bank0)
# A000/0000 (bank1) ES2 will be configurable
# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
# (mem base + reserved)
# For use with external or internal boots.
TEXT_BASE = 0x80e80000
# Used with full SRAM boot.
# This is either with a GP system or a signed boot image.
# easiest, and safest way to go if you can.
#TEXT_BASE = 0x40270000
# Handy to get symbols to debug ROM version.
#TEXT_BASE = 0x0
#TEXT_BASE = 0x08000000

337
board/apollon/lowlevel_init.S Normal file
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/*
* Board specific setup info
*
* (C) Copyright 2005-2007
* Samsung Electronics,
* Kyungmin Park <kyungmin.park@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/arch/omap2420.h>
#include <asm/arch/mem.h>
#include <asm/arch/clocks.h>
#include "mem.h"
#define APOLLON_CS0_BASE 0x00000000
#ifdef PRCM_CONFIG_I
#define SDRC_ACTIM_CTRLA_0_VAL 0x7BA35907
#define SDRC_ACTIM_CTRLB_0_VAL 0x00000013
#define SDRC_RFR_CTRL_0_VAL 0x00044C01
#elif defined(PRCM_CONFIG_II)
#define SDRC_ACTIM_CTRLA_0_VAL 0x4A59B485
#define SDRC_ACTIM_CTRLB_0_VAL 0x0000000C
#define SDRC_RFR_CTRL_0_VAL 0x00030001
#endif
#define SDRAM_BASE_ADDRESS 0x80008000
_TEXT_BASE:
.word TEXT_BASE /* sdram load addr from config.mk */
.globl lowlevel_init
lowlevel_init:
#ifdef CFG_NOR_BOOT
/* Check running in SDRAM */
mov r0, pc, lsr #28
cmp r0, #8
beq prcm_setup
flash_setup:
/* In Flash */
ldr r0, =WD2_BASE
ldr r1, =WD_UNLOCK1
str r1, [r0, #WSPR]
ldr r1, =WD_UNLOCK2
str r1, [r0, #WSPR]
/* Pin muxing for SDRC */
mov r1, #0x00
ldr r0, =0x480000A1 /* ball C12, mode 0 */
strb r1, [r0]
ldr r0, =0x48000032 /* ball D11, mode 0 */
strb r1, [r0]
ldr r0, =0x480000A3 /* ball B13, mode 0 */
strb r1, [r0]
/* SDRC setting */
ldr r0, =OMAP2420_SDRC_BASE
ldr r1, =0x00000010
str r1, [r0, #0x10]
ldr r1, =0x00000100
str r1, [r0, #0x44]
/* SDRC CS0 configuration */
ldr r1, =0x00d04011
str r1, [r0, #0x80]
ldr r1, =SDRC_ACTIM_CTRLA_0_VAL
str r1, [r0, #0x9C]
ldr r1, =SDRC_ACTIM_CTRLB_0_VAL
str r1, [r0, #0xA0]
ldr r1, =SDRC_RFR_CTRL_0_VAL
str r1, [r0, #0xA4]
ldr r1, =0x00000041
str r1, [r0, #0x70]
/* Manual command sequence */
ldr r1, =0x00000007
str r1, [r0, #0xA8]
ldr r1, =0x00000000
str r1, [r0, #0xA8]
ldr r1, =0x00000001
str r1, [r0, #0xA8]
ldr r1, =0x00000002
str r1, [r0, #0xA8]
str r1, [r0, #0xA8]
/*
* CS0 SDRC Mode register
* Burst length = 4 - DDR memory
* Serial mode
* CAS latency = 3
*/
ldr r1, =0x00000032
str r1, [r0, #0x84]
/* Note: You MUST set EMR values */
/* EMR1 & EMR2 */
ldr r1, =0x00000000
str r1, [r0, #0x88]
str r1, [r0, #0x8C]
#ifdef OLD_SDRC_DLLA_CTRL
/* SDRC_DLLA_CTRL */
ldr r1, =0x00007306
str r1, [r0, #0x60]
ldr r1, =0x00007303
str r1, [r0, #0x60]
#else
/* SDRC_DLLA_CTRL */
ldr r1, =0x00000506
str r1, [r0, #0x60]
ldr r1, =0x00000503
str r1, [r0, #0x60]
#endif
#ifdef __BROKEN_FEATURE__
/* SDRC_DLLB_CTRL */
ldr r1, =0x00000506
str r1, [r0, #0x68]
ldr r1, =0x00000503
str r1, [r0, #0x68]
#endif
/* little delay after init */
mov r2, #0x1800
1:
subs r2, r2, #0x1
bne 1b
/* Setup base address */
ldr r0, =0x00000000 /* NOR address */
ldr r1, =SDRAM_BASE_ADDRESS /* SDRAM address */
ldr r2, =0x20000 /* Size: 128KB */
copy_loop:
ldmia r0!, {r3-r10}
stmia r1!, {r3-r10}
cmp r0, r2
ble copy_loop
ldr r1, =SDRAM_BASE_ADDRESS
mov lr, pc
mov pc, r1
#endif
prcm_setup:
ldr r0, =OMAP2420_CM_BASE
ldr r1, [r0, #0x544] /* CLKSEL2_PLL */
bic r1, r1, #0x03
orr r1, r1, #0x02
str r1, [r0, #0x544]
ldr r1, [r0, #0x500]
bic r1, r1, #0x03
orr r1, r1, #0x01
str r1, [r0, #0x500]
ldr r1, [r0, #0x140]
bic r1, r1, #0x1f
orr r1, r1, #0x02
str r1, [r0, #0x140]
#ifdef PRCM_CONFIG_I
ldr r1, =0x000003C3
#else
ldr r1, =0x00000343
#endif
str r1, [r0, #0x840]
ldr r1, =0x00000002
str r1, [r0, #0x340]
ldr r1, =CM_CLKSEL1_CORE
#ifdef PRCM_CONFIG_I
ldr r2, =0x08300C44
#else
ldr r2, =0x04600C26
#endif
str r2, [r1]
ldr r0, =OMAP2420_CM_BASE
ldr r1, [r0, #0x084]
and r1, r1, #0x01
cmp r1, #0x01
bne clkvalid
b .
clkvalid:
mov r1, #0x01
str r1, [r0, #0x080]
waitvalid:
ldr r1, [r0, #0x084]
and r1, r1, #0x01
cmp r1, #0x00
bne waitvalid
ldr r0, =CM_CLKSEL1_PLL
#ifdef PRCM_CONFIG_I
ldr r1, =0x01837100
#else
ldr r1, =0x01832100
#endif
str r1, [r0]
ldr r0, =PRCM_CLKCFG_CTRL
mov r1, #0x01
str r1, [r0]
mov r6, #0x50
loop1:
subs r6, r6, #0x01
cmp r6, #0x01
bne loop1
ldr r0, =CM_CLKEN_PLL
mov r1, #0x0f
str r1, [r0]
mov r6, #0x100
loop2:
subs r6, r6, #0x01
cmp r6, #0x01
bne loop2
ldr r0, =0x48008200
ldr r1, =0xbfffffff
str r1, [r0]
ldr r0, =0x48008210
ldr r1, =0xfffffff9
str r1, [r0]
ldr r0, =0x4806a004
ldr r1, =0x00
strb r1, [r0]
ldr r0, =0x4806a020
ldr r1, =0x07
strb r1, [r0]
ldr r0, =0x4806a00c
ldr r1, =0x83
strb r1, [r0]
ldr r0, =0x4806a000
ldr r1, =0x1a
strb r1, [r0]
ldr r0, =0x4806a004
ldr r1, =0x00
strb r1, [r0]
ldr r0, =0x4806a00c
ldr r1, =0x03
strb r1, [r0]
ldr r0, =0x4806a010
ldr r1, =0x03
strb r1, [r0]
ldr r0, =0x4806a008
ldr r1, =0x04
strb r1, [r0]
ldr r0, =0x4806a020
ldr r1, =0x00
strb r1, [r0]
#if 0
ldr r0, =0x4806a000
mov r1, #'u'
strb r1, [r0]
#endif
#if 0
/* LED0 OFF */
ldr r3, =0x480000E5
mov r4, #0x0b
strb r4, [r3]
#endif
ldr sp, SRAM_STACK
str ip, [sp] /* stash old link register */
mov ip, lr /* save link reg across call */
bl s_init /* go setup pll,mux,memory */
ldr ip, [sp] /* restore save ip */
mov lr, ip /* restore link reg */
/* map interrupt controller */
ldr r0, VAL_INTH_SETUP
mcr p15, 0, r0, c15, c2, 4
/* back to arch calling code */
mov pc, lr
/* the literal pools origin */
.ltorg
VAL_INTH_SETUP:
.word PERIFERAL_PORT_BASE
SRAM_STACK:
.word LOW_LEVEL_SRAM_STACK

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/*
* (C) Copyright 2005-2007
* Samsung Electronics,
* Kyungmin Park <kyungmin.park@samsung.com>
*
* Derived from omap2420
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/omap2420.h>
#include <asm/io.h>
#include <asm/arch/bits.h>
#include <asm/arch/mux.h>
#include <asm/arch/mem.h>
#include <asm/arch/clocks.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/sys_info.h>
#include "mem.h"
/************************************************************
* sdelay() - simple spin loop. Will be constant time as
* its generally used in 12MHz bypass conditions only. This
* is necessary until timers are accessible.
*
* not inline to increase chances its in cache when called
*************************************************************/
void sdelay(unsigned long loops)
{
__asm__("1:\n" "subs %0, %1, #1\n"
"bne 1b":"=r" (loops):"0"(loops));
}
/********************************************************************
* prcm_init() - inits clocks for PRCM as defined in clocks.h
* (config II default).
* -- called from SRAM, or Flash (using temp SRAM stack).
********************************************************************/
void prcm_init(void) { }
/**************************************************************************
* make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
* command line mem=xyz use all memory with out discontigious support
* compiled in. Could do it at the ATAG, but there really is two banks...
* Called as part of 2nd phase DDR init.
**************************************************************************/
void make_cs1_contiguous(void)
{
u32 size, a_add_low, a_add_high;
size = get_sdr_cs_size(SDRC_CS0_OSET);
size /= SZ_32M; /* find size to offset CS1 */
a_add_high = (size & 3) << 8; /* set up low field */
a_add_low = (size & 0x3C) >> 2; /* set up high field */
__raw_writel((a_add_high | a_add_low), SDRC_CS_CFG);
}
/********************************************************
* mem_ok() - test used to see if timings are correct
* for a part. Helps in gussing which part
* we are currently using.
*******************************************************/
u32 mem_ok(void)
{
u32 val1, val2;
u32 pattern = 0x12345678;
/* clear pos A */
__raw_writel(0x0, OMAP2420_SDRC_CS0 + 0x400);
/* pattern to pos B */
__raw_writel(pattern, OMAP2420_SDRC_CS0);
/* remove pattern off the bus */
__raw_writel(0x0, OMAP2420_SDRC_CS0 + 4);
/* get pos A value */
val1 = __raw_readl(OMAP2420_SDRC_CS0 + 0x400);
val2 = __raw_readl(OMAP2420_SDRC_CS0); /* get val2 */
/* see if pos A value changed */
if ((val1 != 0) || (val2 != pattern))
return (0);
else
return (1);
}
/********************************************************
* sdrc_init() - init the sdrc chip selects CS0 and CS1
* - early init routines, called from flash or
* SRAM.
*******************************************************/
void sdrc_init(void)
{
#define EARLY_INIT 1
/* only init up first bank here */
do_sdrc_init(SDRC_CS0_OSET, EARLY_INIT);
}
/*************************************************************************
* do_sdrc_init(): initialize the SDRAM for use.
* -called from low level code with stack only.
* -code sets up SDRAM timing and muxing for 2422 or 2420.
* -optimal settings can be placed here, or redone after i2c
* inspection of board info
*
* This is a bit ugly, but should handle all memory moduels
* used with the APOLLON. The first time though this code from s_init()
* we configure the first chip select. Later on we come back and
* will configure the 2nd chip select if it exists.
*
**************************************************************************/
void do_sdrc_init(u32 offset, u32 early)
{
}
/*****************************************************
* gpmc_init(): init gpmc bus
* Init GPMC for x16, MuxMode (SDRAM in x32).
* This code can only be executed from SRAM or SDRAM.
*****************************************************/
void gpmc_init(void)
{
u32 mux = 0, mtype, mwidth, rev, tval;
rev = get_cpu_rev();
if (rev == CPU_2420_2422_ES1)
tval = 1;
else
tval = 0; /* disable bit switched meaning */
/* global settings */
__raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */
__raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */
__raw_writel(tval, GPMC_TIMEOUT_CONTROL); /* timeout disable */
#ifdef CFG_NAND_BOOT
/* set nWP, disable limited addr */
__raw_writel(0x001, GPMC_CONFIG);
#else
/* set nWP, disable limited addr */
__raw_writel(0x111, GPMC_CONFIG);
#endif
/* discover bus connection from sysboot */
if (is_gpmc_muxed() == GPMC_MUXED)
mux = BIT9;
mtype = get_gpmc0_type();
mwidth = get_gpmc0_width();
/* setup cs0 */
__raw_writel(0x0, GPMC_CONFIG7_0); /* disable current map */
sdelay(1000);
#ifdef CFG_NOR_BOOT
__raw_writel(APOLLON_24XX_GPMC_CONFIG1_3, GPMC_CONFIG1_0);
__raw_writel(APOLLON_24XX_GPMC_CONFIG2_3, GPMC_CONFIG2_0);
__raw_writel(APOLLON_24XX_GPMC_CONFIG3_3, GPMC_CONFIG3_0);
__raw_writel(APOLLON_24XX_GPMC_CONFIG4_3, GPMC_CONFIG4_0);
__raw_writel(APOLLON_24XX_GPMC_CONFIG5_3, GPMC_CONFIG5_0);
__raw_writel(APOLLON_24XX_GPMC_CONFIG6_3, GPMC_CONFIG6_0);
__raw_writel(APOLLON_24XX_GPMC_CONFIG7_3, GPMC_CONFIG7_0);
#else
__raw_writel(APOLLON_24XX_GPMC_CONFIG1_0 | mux | mtype | mwidth,
GPMC_CONFIG1_0);
__raw_writel(APOLLON_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_0);
__raw_writel(APOLLON_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_0);
__raw_writel(APOLLON_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_0);
__raw_writel(APOLLON_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_0);
__raw_writel(APOLLON_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_0);
__raw_writel(APOLLON_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_0);
#endif
sdelay(2000);
/* setup cs1 */
__raw_writel(0, GPMC_CONFIG7_1); /* disable any mapping */
sdelay(1000);
__raw_writel(APOLLON_24XX_GPMC_CONFIG1_1, GPMC_CONFIG1_1);
__raw_writel(APOLLON_24XX_GPMC_CONFIG2_1, GPMC_CONFIG2_1);
__raw_writel(APOLLON_24XX_GPMC_CONFIG3_1, GPMC_CONFIG3_1);
__raw_writel(APOLLON_24XX_GPMC_CONFIG4_1, GPMC_CONFIG4_1);
__raw_writel(APOLLON_24XX_GPMC_CONFIG5_1, GPMC_CONFIG5_1);
__raw_writel(APOLLON_24XX_GPMC_CONFIG6_1, GPMC_CONFIG6_1);
__raw_writel(APOLLON_24XX_GPMC_CONFIG7_1, GPMC_CONFIG7_1);
sdelay(2000);
/* setup cs2 */
__raw_writel(APOLLON_24XX_GPMC_CONFIG1_0 | mux | mtype | mwidth,
GPMC_CONFIG1_2);
/* It's same as cs 0 */
__raw_writel(APOLLON_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_2);
__raw_writel(APOLLON_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_2);
__raw_writel(APOLLON_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_2);
__raw_writel(APOLLON_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_2);
__raw_writel(APOLLON_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_2);
#ifdef CFG_NOR_BOOT
__raw_writel(APOLLON_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_2);
#else
__raw_writel(APOLLON_24XX_GPMC_CONFIG7_2, GPMC_CONFIG7_2);
#endif
#ifndef CFG_NOR_BOOT
/* setup cs3 */
__raw_writel(0, GPMC_CONFIG7_3); /* disable any mapping */
sdelay(1000);
__raw_writel(APOLLON_24XX_GPMC_CONFIG1_3, GPMC_CONFIG1_3);
__raw_writel(APOLLON_24XX_GPMC_CONFIG2_3, GPMC_CONFIG2_3);
__raw_writel(APOLLON_24XX_GPMC_CONFIG3_3, GPMC_CONFIG3_3);
__raw_writel(APOLLON_24XX_GPMC_CONFIG4_3, GPMC_CONFIG4_3);
__raw_writel(APOLLON_24XX_GPMC_CONFIG5_3, GPMC_CONFIG5_3);
__raw_writel(APOLLON_24XX_GPMC_CONFIG6_3, GPMC_CONFIG6_3);
__raw_writel(APOLLON_24XX_GPMC_CONFIG7_3, GPMC_CONFIG7_3);
#endif
#ifndef ASYNC_NOR
__raw_writew(0xaa, (APOLLON_CS3_BASE + 0xaaa));
__raw_writew(0x55, (APOLLON_CS3_BASE + 0x554));
__raw_writew(0xc0, (APOLLON_CS3_BASE | SYNC_NOR_VALUE));
#endif
sdelay(2000);
}

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/*
* (C) Copyright 2005-2007
* Samsung Electronics,
* Kyungmin Park <kyungmin.park@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _APOLLON_OMAP24XX_MEM_H_
#define _APOLLON_OMAP24XX_MEM_H_
/* Slower full frequency range default timings for x32 operation*/
#define APOLLON_2420_SDRC_SHARING 0x00000100
#define APOLLON_2420_SDRC_MDCFG_0_DDR 0x00d04011
#define APOLLON_2420_SDRC_MR_0_DDR 0x00000032
/* optimized timings good for current shipping parts */
#define APOLLON_242X_SDRC_ACTIM_CTRLA_0_100MHz 0x4A59B485
#define APOLLON_242X_SDRC_ACTIM_CTRLB_0_100MHz 0x0000000C
#define APOLLON_242X_SDRC_ACTIM_CTRLA_0_166MHz 0x7BA35907
#define APOLLON_242X_SDRC_ACTIM_CTRLB_0_166MHz 0x00000013
#define APOLLON_242X_SDRC_RFR_CTRL_100MHz 0x00030001
#define APOLLON_242X_SDRC_RFR_CTRL_166MHz 0x00044C01
#define APOLLON_242x_SDRC_DLLAB_CTRL_100MHz 0x00007306
#define APOLLON_242x_SDRC_DLLAB_CTRL_166MHz 0x00000506
#ifdef PRCM_CONFIG_I
#define APOLLON_2420_SDRC_ACTIM_CTRLA_0 APOLLON_242X_SDRC_ACTIM_CTRLA_0_166MHz
#define APOLLON_2420_SDRC_ACTIM_CTRLB_0 APOLLON_242X_SDRC_ACTIM_CTRLB_0_166MHz
#define APOLLON_2420_SDRC_RFR_CTRL APOLLON_242X_SDRC_RFR_CTRL_166MHz
#define APOLLON_2420_SDRC_DLLAB_CTRL APOLLON_242x_SDRC_DLLAB_CTRL_166MHz
#elif PRCM_CONFIG_II
#define APOLLON_2420_SDRC_ACTIM_CTRLA_0 APOLLON_242X_SDRC_ACTIM_CTRLA_0_100MHz
#define APOLLON_2420_SDRC_ACTIM_CTRLB_0 APOLLON_242X_SDRC_ACTIM_CTRLB_0_100MHz
#define APOLLON_2420_SDRC_RFR_CTRL APOLLON_242X_SDRC_RFR_CTRL_100MHz
#define APOLLON_2420_SDRC_DLLAB_CTRL APOLLON_242x_SDRC_DLLAB_CTRL_100MHz
#endif
/* GPMC settings */
#ifdef PRCM_CONFIG_I /* L3 at 165MHz */
/* CS0: OneNAND */
# define APOLLON_24XX_GPMC_CONFIG1_0 0x00000001
# define APOLLON_24XX_GPMC_CONFIG2_0 0x000c1000
# define APOLLON_24XX_GPMC_CONFIG3_0 0x00030400
# define APOLLON_24XX_GPMC_CONFIG4_0 0x0b841006
# define APOLLON_24XX_GPMC_CONFIG5_0 0x020f0c11
# define APOLLON_24XX_GPMC_CONFIG6_0 0x00000000
# define APOLLON_24XX_GPMC_CONFIG7_0 (0x00000e40|(APOLLON_CS0_BASE >> 24))
/* CS1: Ethernet */
# define APOLLON_24XX_GPMC_CONFIG1_1 0x00011200
# define APOLLON_24XX_GPMC_CONFIG2_1 0x001F1F01
# define APOLLON_24XX_GPMC_CONFIG3_1 0x00080803
# define APOLLON_24XX_GPMC_CONFIG4_1 0x1C0b1C0a
# define APOLLON_24XX_GPMC_CONFIG5_1 0x041F1F1F
# define APOLLON_24XX_GPMC_CONFIG6_1 0x000004C4
# define APOLLON_24XX_GPMC_CONFIG7_1 (0x00000F40|(APOLLON_CS1_BASE >> 24))
/* CS2: OneNAND */
/* It's same as CS0 */
# define APOLLON_24XX_GPMC_CONFIG7_2 (0x00000e40|(APOLLON_CS2_BASE >> 24))
/* CS3: NOR */
#ifdef ASYNC_NOR
# define APOLLON_24XX_GPMC_CONFIG1_3 0x00021201
# define APOLLON_24XX_GPMC_CONFIG2_3 0x00121601
# define APOLLON_24XX_GPMC_CONFIG3_3 0x00040401
# define APOLLON_24XX_GPMC_CONFIG4_3 0x12061605
# define APOLLON_24XX_GPMC_CONFIG5_3 0x01151317
#else
# define SYNC_NOR_VALUE 0x24aaa
# define APOLLON_24XX_GPMC_CONFIG1_3 0xe5011211
# define APOLLON_24XX_GPMC_CONFIG2_3 0x00090b01
# define APOLLON_24XX_GPMC_CONFIG3_3 0x00020201
# define APOLLON_24XX_GPMC_CONFIG4_3 0x09030b03
# define APOLLON_24XX_GPMC_CONFIG5_3 0x010a0a0c
#endif /* ASYNC_NOR */
# define APOLLON_24XX_GPMC_CONFIG6_3 0x00000000
# define APOLLON_24XX_GPMC_CONFIG7_3 (0x00000e40|(APOLLON_CS3_BASE >> 24))
#endif /* endif PRCM_CONFIG_I */
#ifdef PRCM_CONFIG_II /* L3 at 100MHz */
/* CS0: OneNAND */
# define APOLLON_24XX_GPMC_CONFIG1_0 0x00000001
# define APOLLON_24XX_GPMC_CONFIG2_0 0x00081080
# define APOLLON_24XX_GPMC_CONFIG3_0 0x00030300
# define APOLLON_24XX_GPMC_CONFIG4_0 0x08041004
# define APOLLON_24XX_GPMC_CONFIG5_0 0x020b0910
# define APOLLON_24XX_GPMC_CONFIG6_0 0x00000000
# define APOLLON_24XX_GPMC_CONFIG7_0 (0x00000C40|(APOLLON_CS0_BASE >> 24))
/* CS1: ethernet */
# define APOLLON_24XX_GPMC_CONFIG1_1 0x00401203
# define APOLLON_24XX_GPMC_CONFIG2_1 0x001F1F01
# define APOLLON_24XX_GPMC_CONFIG3_1 0x00080803
# define APOLLON_24XX_GPMC_CONFIG4_1 0x1C091C09
# define APOLLON_24XX_GPMC_CONFIG5_1 0x041F1F1F
# define APOLLON_24XX_GPMC_CONFIG6_1 0x000004C4
# define APOLLON_24XX_GPMC_CONFIG7_1 (0x00000F40|(APOLLON_CS1_BASE >> 24))
/* CS2: OneNAND */
/* It's same as CS0 */
# define APOLLON_24XX_GPMC_CONFIG7_2 (0x00000e40|(APOLLON_CS2_BASE >> 24))
/* CS3: NOR */
#define ASYNC_NOR
#ifdef ASYNC_NOR
# define APOLLON_24XX_GPMC_CONFIG1_3 0x00021201
# define APOLLON_24XX_GPMC_CONFIG2_3 0x00121601
# define APOLLON_24XX_GPMC_CONFIG3_3 0x00040401
# define APOLLON_24XX_GPMC_CONFIG4_3 0x12061605
# define APOLLON_24XX_GPMC_CONFIG5_3 0x01151317
#else
# define SYNC_NOR_VALUE 0x24aaa
# define APOLLON_24XX_GPMC_CONFIG1_3 0xe1001202
# define APOLLON_24XX_GPMC_CONFIG2_3 0x00151501
# define APOLLON_24XX_GPMC_CONFIG3_3 0x00050501
# define APOLLON_24XX_GPMC_CONFIG4_3 0x0e070e07
# define APOLLON_24XX_GPMC_CONFIG5_3 0x01131F1F
#endif /* ASYNC_NOR */
# define APOLLON_24XX_GPMC_CONFIG6_3 0x00000000
# define APOLLON_24XX_GPMC_CONFIG7_3 (0x00000C40|(APOLLON_CS3_BASE >> 24))
#endif /* endif PRCM_CONFIG_II */
#ifdef PRCM_CONFIG_III /* L3 at 133MHz */
# ifdef CFG_NAND_BOOT
# define APOLLON_24XX_GPMC_CONFIG1_0 0x0
# define APOLLON_24XX_GPMC_CONFIG2_0 0x00141400
# define APOLLON_24XX_GPMC_CONFIG3_0 0x00141400
# define APOLLON_24XX_GPMC_CONFIG4_0 0x0F010F01
# define APOLLON_24XX_GPMC_CONFIG5_0 0x010C1414
# define APOLLON_24XX_GPMC_CONFIG6_0 0x00000A80
# else /* NOR boot */
# define APOLLON_24XX_GPMC_CONFIG1_0 0x3
# define APOLLON_24XX_GPMC_CONFIG2_0 0x00151501
# define APOLLON_24XX_GPMC_CONFIG3_0 0x00060602
# define APOLLON_24XX_GPMC_CONFIG4_0 0x10081008
# define APOLLON_24XX_GPMC_CONFIG5_0 0x01131F1F
# define APOLLON_24XX_GPMC_CONFIG6_0 0x000004c4
# endif /* endif CFG_NAND_BOOT */
# define APOLLON_24XX_GPMC_CONFIG7_0 (0x00000C40|(APOLLON_CS0_BASE >> 24))
# define APOLLON_24XX_GPMC_CONFIG1_1 0x00011000
# define APOLLON_24XX_GPMC_CONFIG2_1 0x001f1f01
# define APOLLON_24XX_GPMC_CONFIG3_1 0x00080803
# define APOLLON_24XX_GPMC_CONFIG4_1 0x1C091C09
# define APOLLON_24XX_GPMC_CONFIG5_1 0x041f1F1F
# define APOLLON_24XX_GPMC_CONFIG6_1 0x000004C4
# define APOLLON_24XX_GPMC_CONFIG7_1 (0x00000F40|(APOLLON_CS1_BASE >> 24))
#endif /* endif CFG_PRCM_III */
#endif /* endif _APOLLON_OMAP24XX_MEM_H_ */

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/*
* (C) Copyright 2005-2007
* Samsung Electronics,
* Kyungmin Park <kyungmin.park@samsung.com>
*
* Derived from omap2420
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/omap2420.h>
#include <asm/io.h>
#include <asm/arch/bits.h>
#include <asm/arch/mem.h> /* get mem tables */
#include <asm/arch/sys_proto.h>
#include <asm/arch/sys_info.h>
#include <i2c.h>
/**************************************************************************
* get_prod_id() - get id info from chips
***************************************************************************/
static u32 get_prod_id(void)
{
u32 p;
p = __raw_readl(PRODUCTION_ID); /* get production ID */
return ((p & CPU_242X_PID_MASK) >> 16);
}
/**************************************************************************
* get_cpu_type() - low level get cpu type
* - no C globals yet.
* - just looking to say if this is a 2422 or 2420 or ...
* - to start with we will look at switch settings..
* - 2422 id's same as 2420 for ES1 will rely on H4 board characteristics
* (mux for 2420, non-mux for 2422).
***************************************************************************/
u32 get_cpu_type(void)
{
u32 v;
switch (get_prod_id()) {
case 1:; /* 2420 */
case 2:
return (CPU_2420);
break; /* 2420 pop */
case 4:
return (CPU_2422);
break;
case 8:
return (CPU_2423);
break;
default:
break; /* early 2420/2422's unmarked */
}
v = __raw_readl(TAP_IDCODE_REG);
v &= CPU_24XX_ID_MASK;
/* currently 2420 and 2422 have same id */
if (v == CPU_2420_CHIPID) {
if (is_gpmc_muxed() == GPMC_MUXED) /* if mux'ed */
return (CPU_2420);
else
return (CPU_2422);
} else
return (CPU_2420); /* don't know, say 2420 */
}
/******************************************
* get_cpu_rev(void) - extract version info
******************************************/
u32 get_cpu_rev(void)
{
u32 v;
v = __raw_readl(TAP_IDCODE_REG);
v = v >> 28;
return (v + 1); /* currently 2422 and 2420 match up */
}
/****************************************************
* is_mem_sdr() - return 1 if mem type in use is SDR
****************************************************/
u32 is_mem_sdr(void)
{
volatile u32 *burst = (volatile u32 *)(SDRC_MR_0 + SDRC_CS0_OSET);
if (*burst == H4_2420_SDRC_MR_0_SDR)
return (1);
return (0);
}
/***********************************************************
* get_mem_type() - identify type of mDDR part used.
* 2422 uses stacked DDR, 2 parts CS0/CS1.
* 2420 may have 1 or 2, no good way to know...only init 1...
* when eeprom data is up we can select 1 more.
*************************************************************/
u32 get_mem_type(void)
{
u32 cpu, sdr = is_mem_sdr();
cpu = get_cpu_type();
if (cpu == CPU_2422 || cpu == CPU_2423)
return (DDR_STACKED);
if (get_prod_id() == 0x2)
return (XDR_POP);
if (get_board_type() == BOARD_H4_MENELAUS)
if (sdr)
return (SDR_DISCRETE);
else
return (DDR_COMBO);
else if (sdr) /* SDP + SDR kit */
return (SDR_DISCRETE);
else
return (DDR_DISCRETE); /* origional SDP */
}
/***********************************************************************
* get_cs0_size() - get size of chip select 0/1
************************************************************************/
u32 get_sdr_cs_size(u32 offset)
{
u32 size;
size = __raw_readl(SDRC_MCFG_0 + offset) >> 8; /* get ram size field */
size &= 0x2FF; /* remove unwanted bits */
size *= SZ_2M; /* find size in MB */
return (size);
}
/***********************************************************************
* get_board_type() - get board type based on current production stats.
* --- NOTE: 2 I2C EEPROMs will someday be populated with proper info.
* when they are available we can get info from there. This should
* be correct of all known boards up until today.
************************************************************************/
u32 get_board_type(void)
{
return (BOARD_H4_SDP);
}
/******************************************************************
* get_sysboot_value() - get init word settings (dip switch on h4)
******************************************************************/
inline u32 get_sysboot_value(void)
{
return (0x00000FFF & __raw_readl(CONTROL_STATUS));
}
/***************************************************************************
* get_gpmc0_base() - Return current address hardware will be
* fetching from. The below effectively gives what is correct, its a bit
* mis-leading compared to the TRM. For the most general case the mask
* needs to be also taken into account this does work in practice.
* - for u-boot we currently map:
* -- 0 to nothing,
* -- 4 to flash
* -- 8 to enent
* -- c to wifi
****************************************************************************/
u32 get_gpmc0_base(void)
{
u32 b;
b = __raw_readl(GPMC_CONFIG7_0);
b &= 0x1F; /* keep base [5:0] */
b = b << 24; /* ret 0x0b000000 */
return (b);
}
/*****************************************************************
* is_gpmc_muxed() - tells if address/data lines are multiplexed
*****************************************************************/
u32 is_gpmc_muxed(void)
{
u32 mux;
mux = get_sysboot_value();
if ((mux & (BIT0 | BIT1 | BIT2 | BIT3)) == (BIT0 | BIT2 | BIT3))
return (GPMC_MUXED); /* NAND Boot mode */
if (mux & BIT1) /* if mux'ed */
return (GPMC_MUXED);
else
return (GPMC_NONMUXED);
}
/************************************************************************
* get_gpmc0_type() - read sysboot lines to see type of memory attached
************************************************************************/
u32 get_gpmc0_type(void)
{
u32 type;
type = get_sysboot_value();
if ((type & (BIT3 | BIT2)) == (BIT3 | BIT2))
return (TYPE_NAND);
else
return (TYPE_NOR);
}
/*******************************************************************
* get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
*******************************************************************/
u32 get_gpmc0_width(void)
{
u32 width;
width = get_sysboot_value();
if ((width & 0xF) == (BIT3 | BIT2))
return (WIDTH_8BIT);
else
return (WIDTH_16BIT);
}
/*********************************************************************
* wait_on_value() - common routine to allow waiting for changes in
* volatile regs.
*********************************************************************/
u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
{
u32 i = 0, val;
do {
++i;
val = __raw_readl(read_addr) & read_bit_mask;
if (val == match_value)
return (1);
if (i == bound)
return (0);
} while (1);
}
/*********************************************************************
* display_board_info() - print banner with board info.
*********************************************************************/
void display_board_info(u32 btype)
{
char cpu_2420[] = "2420"; /* cpu type */
char cpu_2422[] = "2422";
char cpu_2423[] = "2423";
char db_men[] = "Menelaus"; /* board type */
char db_ip[] = "IP";
char mem_sdr[] = "mSDR"; /* memory type */
char mem_ddr[] = "mDDR";
char t_tst[] = "TST"; /* security level */
char t_emu[] = "EMU";
char t_hs[] = "HS";
char t_gp[] = "GP";
char unk[] = "?";
char *cpu_s, *db_s, *mem_s, *sec_s;
u32 cpu, rev, sec;
rev = get_cpu_rev();
cpu = get_cpu_type();
sec = get_device_type();
if (is_mem_sdr())
mem_s = mem_sdr;
else
mem_s = mem_ddr;
if (cpu == CPU_2423)
cpu_s = cpu_2423;
else if (cpu == CPU_2422)
cpu_s = cpu_2422;
else
cpu_s = cpu_2420;
if (btype == BOARD_H4_MENELAUS)
db_s = db_men;
else
db_s = db_ip;
switch (sec) {
case TST_DEVICE:
sec_s = t_tst;
break;
case EMU_DEVICE:
sec_s = t_emu;
break;
case HS_DEVICE:
sec_s = t_hs;
break;
case GP_DEVICE:
sec_s = t_gp;
break;
default:
sec_s = unk;
}
printf("OMAP%s-%s revision %d\n", cpu_s, sec_s, rev - 1);
printf("Samsung Apollon SDP Base Board + %s \n", mem_s);
}
/*************************************************************************
* get_board_rev() - setup to pass kernel board revision information
* 0 = 242x IP platform (first 2xx boards)
* 1 = 242x Menelaus platfrom.
*************************************************************************/
u32 get_board_rev(void)
{
u32 rev = 0;
u32 btype = get_board_type();
if (btype == BOARD_H4_MENELAUS)
rev = 1;
return (rev);
}
/********************************************************
* get_base(); get upper addr of current execution
*******************************************************/
u32 get_base(void)
{
u32 val;
__asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
val &= 0xF0000000;
val >>= 28;
return (val);
}
/********************************************************
* get_base2(); get 2upper addr of current execution
*******************************************************/
u32 get_base2(void)
{
u32 val;
__asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
val &= 0xFF000000;
val >>= 24;
return (val);
}
/********************************************************
* running_in_flash() - tell if currently running in
* flash.
*******************************************************/
u32 running_in_flash(void)
{
if (get_base() < 4)
return (1); /* in flash */
return (0); /* running in SRAM or SDRAM */
}
/********************************************************
* running_in_sram() - tell if currently running in
* sram.
*******************************************************/
u32 running_in_sram(void)
{
if (get_base() == 4)
return (1); /* in SRAM */
return (0); /* running in FLASH or SDRAM */
}
/********************************************************
* running_in_sdram() - tell if currently running in
* flash.
*******************************************************/
u32 running_in_sdram(void)
{
if (get_base() > 4)
return (1); /* in sdram */
return (0); /* running in SRAM or FLASH */
}
/*************************************************************
* running_from_internal_boot() - am I a signed NOR image.
*************************************************************/
u32 running_from_internal_boot(void)
{
u32 v, base;
v = get_sysboot_value() & BIT3;
base = get_base2();
/* if running at mask rom flash address and
* sysboot3 says this was an internal boot
*/
if ((base == 0x08) && v)
return (1);
else
return (0);
}
/*************************************************************
* get_device_type(): tell if GP/HS/EMU/TST
*************************************************************/
u32 get_device_type(void)
{
int mode;
mode = __raw_readl(CONTROL_STATUS) & (BIT10 | BIT9 | BIT8);
return (mode >>= 8);
}

63
board/apollon/u-boot.lds Normal file
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/*
*
* Copyright (C) 2005-2007 Samsung Electronics
* Kyungin Park <kyugnmin.park@samsung.com>
*
* January 2004 - Changed to support H4 device
* Copyright (c) 2004 Texas Instruments
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
cpu/arm1136/start.o (.text)
*(.text)
}
. = ALIGN(4);
.rodata : { *(.rodata) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.got : { *(.got) }
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
__bss_start = .;
.bss : { *(.bss) }
_end = .;
}

38
board/esd/common/lcd.c
View File

@ -37,41 +37,41 @@ int lcd_depth;
unsigned char *glob_lcd_reg;
unsigned char *glob_lcd_mem;
#ifdef CFG_LCD_ENDIAN
#if defined(CFG_LCD_ENDIAN)
void lcd_setup(int lcd, int config)
{
if (lcd == 0) {
/*
* Set endianess and reset lcd controller 0 (small)
*/
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD0_RST); /* set reset to low */
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_LCD0_RST); /* set reset to low */
udelay(10); /* wait 10us */
if (config == 1)
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */
else
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */
udelay(10); /* wait 10us */
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD0_RST); /* set reset to high */
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD0_RST); /* set reset to high */
} else {
/*
* Set endianess and reset lcd controller 1 (big)
*/
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD1_RST); /* set reset to low */
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_LCD1_RST); /* set reset to low */
udelay(10); /* wait 10us */
if (config == 1)
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */
else
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */
udelay(10); /* wait 10us */
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD1_RST); /* set reset to high */
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD1_RST); /* set reset to high */
}
/*
* CFG_LCD_ENDIAN may also be FPGA_RESET, so set inactive
*/
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* set reset high again */
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); /* set reset high again */
}
#endif /* #ifdef CFG_LCD_ENDIAN */
#endif /* CFG_LCD_ENDIAN */
void lcd_bmp(uchar *logo_bmp)
@ -93,7 +93,6 @@ void lcd_bmp(uchar *logo_bmp)
* Check for bmp mark 'BM'
*/
if (*(ushort *)logo_bmp != 0x424d) {
/*
* Decompress bmp image
*/
@ -160,7 +159,7 @@ void lcd_bmp(uchar *logo_bmp)
*/
if ((colors <= 256) && (lcd_depth <= 8)) {
ptr = (unsigned char *)(dst + 14 + 40);
for (i=0; i<colors; i++) {
for (i = 0; i < colors; i++) {
b = *ptr++;
g = *ptr++;
r = *ptr++;
@ -175,11 +174,11 @@ void lcd_bmp(uchar *logo_bmp)
ptr = glob_lcd_mem;
ptr2 = (ushort *)glob_lcd_mem;
header_size = 14 + 40 + 4*colors; /* skip bmp header */
for (y=0; y<height; y++) {
for (y = 0; y < height; y++) {
bmp = &dst[(height-1-y)*line_size + header_size];
if (lcd_depth == 16) {
if (bpp == 24) {
for (x=0; x<width; x++) {
for (x = 0; x < width; x++) {
/*
* Generate epson 16bpp fb-format from 24bpp image
*/
@ -190,7 +189,7 @@ void lcd_bmp(uchar *logo_bmp)
*ptr2++ = val;
}
} else if (bpp == 8) {
for (x=0; x<line_size; x++) {
for (x = 0; x < line_size; x++) {
/* query rgb value from palette */
ptr = (unsigned char *)(dst + 14 + 40) ;
ptr += (*bmp++) << 2;
@ -202,9 +201,8 @@ void lcd_bmp(uchar *logo_bmp)
}
}
} else {
for (x=0; x<line_size; x++) {
for (x = 0; x < line_size; x++)
*ptr++ = *bmp++;
}
}
}
@ -254,7 +252,7 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
palette_value = 0x17;
lcd_depth = 8;
puts("LCD: S1D13704");
} else if (in_8(&lcd_reg[0x10000]) == 0x24) {
} else if (in_8(&lcd_reg[0x10000]) == 0x24) {
/*
* Small epson detected (705)
*/
@ -296,7 +294,7 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
lcd_bmp(logo_bmp);
}
#ifdef CONFIG_VIDEO_SM501
#if defined(CONFIG_VIDEO_SM501)
int do_esdbmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
ulong addr;

4
board/esd/pmc440/cmd_pmc440.c
View File

@ -280,10 +280,10 @@ int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]
if (argc > 1) {
if (!strcmp(argv[1], "400")) {
/* PLB=133MHz, PLB/PCI=4 */
/* PLB=133MHz, PLB/PCI=3 */
printf("Bootstrapping for 400MHz\n");
sdsdp[0]=0x8678624e;
sdsdp[1]=0x0947a030;
sdsdp[1]=0x095fa030;
sdsdp[2]=0x40082350;
sdsdp[3]=0x0d050000;
} else if (!strcmp(argv[1], "533")) {

342
board/esd/pmc440/sdram.c
View File

@ -33,343 +33,9 @@
#include <asm/io.h>
#include <ppc440.h>
#include "sdram.h"
extern int denali_wait_for_dlllock(void);
extern void denali_core_search_data_eye(void);
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
defined(CONFIG_DDR_DATA_EYE)
/*-----------------------------------------------------------------------------+
* wait_for_dlllock.
+----------------------------------------------------------------------------*/
static int wait_for_dlllock(void)
{
unsigned long val;
int wait = 0;
/* -----------------------------------------------------------+
* Wait for the DCC master delay line to finish calibration
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_17);
val = DDR0_17_DLLLOCKREG_UNLOCKED;
while (wait != 0xffff) {
val = mfdcr(ddrcfgd);
if ((val & DDR0_17_DLLLOCKREG_MASK) == DDR0_17_DLLLOCKREG_LOCKED)
/* dlllockreg bit on */
return 0;
else
wait++;
}
debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val);
debug("Waiting for dlllockreg bit to raise\n");
return -1;
}
#endif
#if defined(CONFIG_DDR_DATA_EYE)
/*-----------------------------------------------------------------------------+
* wait_for_dram_init_complete.
+----------------------------------------------------------------------------*/
int wait_for_dram_init_complete(void)
{
unsigned long val;
int wait = 0;
/* --------------------------------------------------------------+
* Wait for 'DRAM initialization complete' bit in status register
* -------------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_00);
while (wait != 0xffff) {
val = mfdcr(ddrcfgd);
if ((val & DDR0_00_INT_STATUS_BIT6) == DDR0_00_INT_STATUS_BIT6)
/* 'DRAM initialization complete' bit */
return 0;
else
wait++;
}
debug("DRAM initialization complete bit in status register did not rise\n");
return -1;
}
#define NUM_TRIES 64
#define NUM_READS 10
/*-----------------------------------------------------------------------------+
* denali_core_search_data_eye.
+----------------------------------------------------------------------------*/
void denali_core_search_data_eye(unsigned long memory_size)
{
int k, j;
u32 val;
u32 wr_dqs_shift, dqs_out_shift, dll_dqs_delay_X;
u32 max_passing_cases = 0, wr_dqs_shift_with_max_passing_cases = 0;
u32 passing_cases = 0, dll_dqs_delay_X_sw_val = 0;
u32 dll_dqs_delay_X_start_window = 0, dll_dqs_delay_X_end_window = 0;
volatile u32 *ram_pointer;
u32 test[NUM_TRIES] = {
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
ram_pointer = (volatile u32 *)(CFG_SDRAM_BASE);
for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) {
/*for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) {*/
/* -----------------------------------------------------------+
* De-assert 'start' parameter.
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_02);
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
mtdcr(ddrcfgd, val);
/* -----------------------------------------------------------+
* Set 'wr_dqs_shift'
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_09);
val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
mtdcr(ddrcfgd, val);
/* -----------------------------------------------------------+
* Set 'dqs_out_shift' = wr_dqs_shift + 32
* ----------------------------------------------------------*/
dqs_out_shift = wr_dqs_shift + 32;
mtdcr(ddrcfga, DDR0_22);
val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
mtdcr(ddrcfgd, val);
passing_cases = 0;
for (dll_dqs_delay_X = 1; dll_dqs_delay_X < 64; dll_dqs_delay_X++) {
/*for (dll_dqs_delay_X=1; dll_dqs_delay_X<128; dll_dqs_delay_X++) {*/
/* -----------------------------------------------------------+
* Set 'dll_dqs_delay_X'.
* ----------------------------------------------------------*/
/* dll_dqs_delay_0 */
mtdcr(ddrcfga, DDR0_17);
val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
/* dll_dqs_delay_1 to dll_dqs_delay_4 */
mtdcr(ddrcfga, DDR0_18);
val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
/* dll_dqs_delay_5 to dll_dqs_delay_8 */
mtdcr(ddrcfga, DDR0_19);
val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
ppcMsync();
ppcMbar();
/* -----------------------------------------------------------+
* Assert 'start' parameter.
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_02);
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
mtdcr(ddrcfgd, val);
ppcMsync();
ppcMbar();
/* -----------------------------------------------------------+
* Wait for the DCC master delay line to finish calibration
* ----------------------------------------------------------*/
if (wait_for_dlllock() != 0) {
printf("dlllock did not occur !!!\n");
printf("denali_core_search_data_eye!!!\n");
printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
wr_dqs_shift, dll_dqs_delay_X);
hang();
}
ppcMsync();
ppcMbar();
if (wait_for_dram_init_complete() != 0) {
printf("dram init complete did not occur !!!\n");
printf("denali_core_search_data_eye!!!\n");
printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
wr_dqs_shift, dll_dqs_delay_X);
hang();
}
udelay(100); /* wait 100us to ensure init is really completed !!! */
/* write values */
for (j=0; j<NUM_TRIES; j++) {
ram_pointer[j] = test[j];
/* clear any cache at ram location */
__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
}
/* read values back */
for (j=0; j<NUM_TRIES; j++) {
for (k=0; k<NUM_READS; k++) {
/* clear any cache at ram location */
__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
if (ram_pointer[j] != test[j])
break;
}
/* read error */
if (k != NUM_READS)
break;
}
/* See if the dll_dqs_delay_X value passed.*/
if (j < NUM_TRIES) {
/* Failed */
passing_cases = 0;
/* break; */
} else {
/* Passed */
if (passing_cases == 0)
dll_dqs_delay_X_sw_val = dll_dqs_delay_X;
passing_cases++;
if (passing_cases >= max_passing_cases) {
max_passing_cases = passing_cases;
wr_dqs_shift_with_max_passing_cases = wr_dqs_shift;
dll_dqs_delay_X_start_window = dll_dqs_delay_X_sw_val;
dll_dqs_delay_X_end_window = dll_dqs_delay_X;
}
}
/* -----------------------------------------------------------+
* De-assert 'start' parameter.
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_02);
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
mtdcr(ddrcfgd, val);
} /* for (dll_dqs_delay_X=0; dll_dqs_delay_X<128; dll_dqs_delay_X++) */
} /* for (wr_dqs_shift=0; wr_dqs_shift<96; wr_dqs_shift++) */
/* -----------------------------------------------------------+
* Largest passing window is now detected.
* ----------------------------------------------------------*/
/* Compute dll_dqs_delay_X value */
dll_dqs_delay_X = (dll_dqs_delay_X_end_window + dll_dqs_delay_X_start_window) / 2;
wr_dqs_shift = wr_dqs_shift_with_max_passing_cases;
debug("DQS calibration - Window detected:\n");
debug("max_passing_cases = %d\n", max_passing_cases);
debug("wr_dqs_shift = %d\n", wr_dqs_shift);
debug("dll_dqs_delay_X = %d\n", dll_dqs_delay_X);
debug("dll_dqs_delay_X window = %d - %d\n",
dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window);
/* -----------------------------------------------------------+
* De-assert 'start' parameter.
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_02);
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
mtdcr(ddrcfgd, val);
/* -----------------------------------------------------------+
* Set 'wr_dqs_shift'
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_09);
val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
mtdcr(ddrcfgd, val);
debug("DDR0_09=0x%08lx\n", val);
/* -----------------------------------------------------------+
* Set 'dqs_out_shift' = wr_dqs_shift + 32
* ----------------------------------------------------------*/
dqs_out_shift = wr_dqs_shift + 32;
mtdcr(ddrcfga, DDR0_22);
val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
mtdcr(ddrcfgd, val);
debug("DDR0_22=0x%08lx\n", val);
/* -----------------------------------------------------------+
* Set 'dll_dqs_delay_X'.
* ----------------------------------------------------------*/
/* dll_dqs_delay_0 */
mtdcr(ddrcfga, DDR0_17);
val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
debug("DDR0_17=0x%08lx\n", val);
/* dll_dqs_delay_1 to dll_dqs_delay_4 */
mtdcr(ddrcfga, DDR0_18);
val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
debug("DDR0_18=0x%08lx\n", val);
/* dll_dqs_delay_5 to dll_dqs_delay_8 */
mtdcr(ddrcfga, DDR0_19);
val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
debug("DDR0_19=0x%08lx\n", val);
/* -----------------------------------------------------------+
* Assert 'start' parameter.
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_02);
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
mtdcr(ddrcfgd, val);
ppcMsync();
ppcMbar();
/* -----------------------------------------------------------+
* Wait for the DCC master delay line to finish calibration
* ----------------------------------------------------------*/
if (wait_for_dlllock() != 0) {
printf("dlllock did not occur !!!\n");
hang();
}
ppcMsync();
ppcMbar();
if (wait_for_dram_init_complete() != 0) {
printf("dram init complete did not occur !!!\n");
hang();
}
udelay(100); /* wait 100us to ensure init is really completed !!! */
}
#endif /* CONFIG_DDR_DATA_EYE */
#if defined(CONFIG_NAND_SPL)
/* Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big
@ -428,14 +94,14 @@ long int initdram (int board_type)
mtsdram(DDR0_44, 0x00000003);
mtsdram(DDR0_02, 0x00000001);
wait_for_dlllock();
denali_wait_for_dlllock();
#endif /* #ifndef CONFIG_NAND_U_BOOT */
#ifdef CONFIG_DDR_DATA_EYE
/* -----------------------------------------------------------+
* Perform data eye search if requested.
* ----------------------------------------------------------*/
denali_core_search_data_eye(CFG_MBYTES_SDRAM << 20);
denali_core_search_data_eye();
#endif
return (CFG_MBYTES_SDRAM << 20);

505
board/esd/pmc440/sdram.h
View File

@ -1,505 +0,0 @@
/*
* (C) Copyright 2006
* Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
* Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
* Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _SPD_SDRAM_DENALI_H_
#define _SPD_SDRAM_DENALI_H_
#define ppcMsync sync
#define ppcMbar eieio
/* General definitions */
#define MAX_SPD_BYTE 128 /* highest SPD byte # to read */
#define DENALI_REG_NUMBER 45 /* 45 Regs in PPC440EPx Denali Core */
#define SUPPORTED_DIMMS_NB 7 /* Number of supported DIMM modules types */
#define SDRAM_NONE 0 /* No DIMM detected in Slot */
#define MAXRANKS 2 /* 2 ranks maximum */
/* Supported PLB Frequencies */
#define PLB_FREQ_133MHZ 133333333
#define PLB_FREQ_152MHZ 152000000
#define PLB_FREQ_160MHZ 160000000
#define PLB_FREQ_166MHZ 166666666
/* Denali Core Registers */
#define SDRAM_DCR_BASE 0x10
#define DDR_DCR_BASE 0x10
#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */
#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */
/*-----------------------------------------------------------------------------+
| Values for ddrcfga register - indirect addressing of these regs
+-----------------------------------------------------------------------------*/
#define DDR0_00 0x00
#define DDR0_00_INT_ACK_MASK 0x7F000000 /* Write only */
#define DDR0_00_INT_ACK_ALL 0x7F000000
#define DDR0_00_INT_ACK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
#define DDR0_00_INT_ACK_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
/* Status */
#define DDR0_00_INT_STATUS_MASK 0x00FF0000 /* Read only */
/* Bit0. A single access outside the defined PHYSICAL memory space detected. */
#define DDR0_00_INT_STATUS_BIT0 0x00010000
/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */
#define DDR0_00_INT_STATUS_BIT1 0x00020000
/* Bit2. Single correctable ECC event detected */
#define DDR0_00_INT_STATUS_BIT2 0x00040000
/* Bit3. Multiple correctable ECC events detected. */
#define DDR0_00_INT_STATUS_BIT3 0x00080000
/* Bit4. Single uncorrectable ECC event detected. */
#define DDR0_00_INT_STATUS_BIT4 0x00100000
/* Bit5. Multiple uncorrectable ECC events detected. */
#define DDR0_00_INT_STATUS_BIT5 0x00200000
/* Bit6. DRAM initialization complete. */
#define DDR0_00_INT_STATUS_BIT6 0x00400000
/* Bit7. Logical OR of all lower bits. */
#define DDR0_00_INT_STATUS_BIT7 0x00800000
#define DDR0_00_INT_STATUS_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
#define DDR0_00_INT_STATUS_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
#define DDR0_00_DLL_INCREMENT_MASK 0x00007F00
#define DDR0_00_DLL_INCREMENT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_00_DLL_INCREMENT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_00_DLL_START_POINT_MASK 0x0000007F
#define DDR0_00_DLL_START_POINT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_00_DLL_START_POINT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_01 0x01
#define DDR0_01_PLB0_DB_CS_LOWER_MASK 0x1F000000
#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
#define DDR0_01_PLB0_DB_CS_UPPER_MASK 0x001F0000
#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n) ((((unsigned long)(n))>>16)&0x1F)
#define DDR0_01_OUT_OF_RANGE_TYPE_MASK 0x00000700 /* Read only */
#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
#define DDR0_01_INT_MASK_MASK 0x000000FF
#define DDR0_01_INT_MASK_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
#define DDR0_01_INT_MASK_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
#define DDR0_01_INT_MASK_ALL_ON 0x000000FF
#define DDR0_01_INT_MASK_ALL_OFF 0x00000000
#define DDR0_02 0x02
#define DDR0_02_MAX_CS_REG_MASK 0x02000000 /* Read only */
#define DDR0_02_MAX_CS_REG_ENCODE(n) ((((unsigned long)(n))&0x2)<<24)
#define DDR0_02_MAX_CS_REG_DECODE(n) ((((unsigned long)(n))>>24)&0x2)
#define DDR0_02_MAX_COL_REG_MASK 0x000F0000 /* Read only */
#define DDR0_02_MAX_COL_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<16)
#define DDR0_02_MAX_COL_REG_DECODE(n) ((((unsigned long)(n))>>16)&0xF)
#define DDR0_02_MAX_ROW_REG_MASK 0x00000F00 /* Read only */
#define DDR0_02_MAX_ROW_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
#define DDR0_02_MAX_ROW_REG_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
#define DDR0_02_START_MASK 0x00000001
#define DDR0_02_START_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
#define DDR0_02_START_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
#define DDR0_02_START_OFF 0x00000000
#define DDR0_02_START_ON 0x00000001
#define DDR0_03 0x03
#define DDR0_03_BSTLEN_MASK 0x07000000
#define DDR0_03_BSTLEN_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
#define DDR0_03_BSTLEN_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
#define DDR0_03_CASLAT_MASK 0x00070000
#define DDR0_03_CASLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
#define DDR0_03_CASLAT_LIN_MASK 0x00000F00
#define DDR0_03_CASLAT_LIN_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
#define DDR0_03_CASLAT_LIN_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
#define DDR0_03_INITAREF_MASK 0x0000000F
#define DDR0_03_INITAREF_ENCODE(n) ((((unsigned long)(n))&0xF)<<0)
#define DDR0_03_INITAREF_DECODE(n) ((((unsigned long)(n))>>0)&0xF)
#define DDR0_04 0x04
#define DDR0_04_TRC_MASK 0x1F000000
#define DDR0_04_TRC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
#define DDR0_04_TRC_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
#define DDR0_04_TRRD_MASK 0x00070000
#define DDR0_04_TRRD_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
#define DDR0_04_TRRD_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
#define DDR0_04_TRTP_MASK 0x00000700
#define DDR0_04_TRTP_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
#define DDR0_04_TRTP_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
#define DDR0_05 0x05
#define DDR0_05_TMRD_MASK 0x1F000000
#define DDR0_05_TMRD_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
#define DDR0_05_TMRD_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
#define DDR0_05_TEMRS_MASK 0x00070000
#define DDR0_05_TEMRS_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
#define DDR0_05_TEMRS_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
#define DDR0_05_TRP_MASK 0x00000F00
#define DDR0_05_TRP_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
#define DDR0_05_TRP_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
#define DDR0_05_TRAS_MIN_MASK 0x000000FF
#define DDR0_05_TRAS_MIN_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
#define DDR0_05_TRAS_MIN_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
#define DDR0_06 0x06
#define DDR0_06_WRITEINTERP_MASK 0x01000000
#define DDR0_06_WRITEINTERP_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
#define DDR0_06_WRITEINTERP_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
#define DDR0_06_TWTR_MASK 0x00070000
#define DDR0_06_TWTR_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
#define DDR0_06_TWTR_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
#define DDR0_06_TDLL_MASK 0x0000FF00
#define DDR0_06_TDLL_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
#define DDR0_06_TDLL_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
#define DDR0_06_TRFC_MASK 0x0000007F
#define DDR0_06_TRFC_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_06_TRFC_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_07 0x07
#define DDR0_07_NO_CMD_INIT_MASK 0x01000000
#define DDR0_07_NO_CMD_INIT_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
#define DDR0_07_NO_CMD_INIT_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
#define DDR0_07_TFAW_MASK 0x001F0000
#define DDR0_07_TFAW_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
#define DDR0_07_TFAW_DECODE(n) ((((unsigned long)(n))>>16)&0x1F)
#define DDR0_07_AUTO_REFRESH_MODE_MASK 0x00000100
#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
#define DDR0_07_AREFRESH_MASK 0x00000001
#define DDR0_07_AREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
#define DDR0_07_AREFRESH_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
#define DDR0_08 0x08
#define DDR0_08_WRLAT_MASK 0x07000000
#define DDR0_08_WRLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
#define DDR0_08_WRLAT_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
#define DDR0_08_TCPD_MASK 0x00FF0000
#define DDR0_08_TCPD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
#define DDR0_08_TCPD_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
#define DDR0_08_DQS_N_EN_MASK 0x00000100
#define DDR0_08_DQS_N_EN_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
#define DDR0_08_DQS_N_EN_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
#define DDR0_08_DDRII_SDRAM_MODE_MASK 0x00000001
#define DDR0_08_DDRII_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
#define DDR0_08_DDRII_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
#define DDR0_09 0x09
#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK 0x1F000000
#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
#define DDR0_09_RTT_0_MASK 0x00030000
#define DDR0_09_RTT_0_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
#define DDR0_09_RTT_0_DECODE(n) ((((unsigned long)(n))>>16)&0x3)
#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK 0x00007F00
#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_09_WR_DQS_SHIFT_MASK 0x0000007F
#define DDR0_09_WR_DQS_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_09_WR_DQS_SHIFT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_10 0x0A
#define DDR0_10_WRITE_MODEREG_MASK 0x00010000 /* Write only */
#define DDR0_10_WRITE_MODEREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
#define DDR0_10_WRITE_MODEREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
#define DDR0_10_CS_MAP_MASK 0x00000300
#define DDR0_10_CS_MAP_NO_MEM 0x00000000
#define DDR0_10_CS_MAP_RANK0_INSTALLED 0x00000100
#define DDR0_10_CS_MAP_RANK1_INSTALLED 0x00000200
#define DDR0_10_CS_MAP_ENCODE(n) ((((unsigned long)(n))&0x3)<<8)
#define DDR0_10_CS_MAP_DECODE(n) ((((unsigned long)(n))>>8)&0x3)
#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK 0x0000001F
#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<0)
#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x1F)
#define DDR0_11 0x0B
#define DDR0_11_SREFRESH_MASK 0x01000000
#define DDR0_11_SREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
#define DDR0_11_SREFRESH_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
#define DDR0_11_TXSNR_MASK 0x00FF0000
#define DDR0_11_TXSNR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
#define DDR0_11_TXSNR_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
#define DDR0_11_TXSR_MASK 0x0000FF00
#define DDR0_11_TXSR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
#define DDR0_11_TXSR_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
#define DDR0_12 0x0C
#define DDR0_12_TCKE_MASK 0x0000007
#define DDR0_12_TCKE_ENCODE(n) ((((unsigned long)(n))&0x7)<<0)
#define DDR0_12_TCKE_DECODE(n) ((((unsigned long)(n))>>0)&0x7)
#define DDR0_13 0x0D
#define DDR0_14 0x0E
#define DDR0_14_DLL_BYPASS_MODE_MASK 0x01000000
#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
#define DDR0_14_DLL_BYPASS_MODE_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
#define DDR0_14_REDUC_MASK 0x00010000
#define DDR0_14_REDUC_64BITS 0x00000000
#define DDR0_14_REDUC_32BITS 0x00010000
#define DDR0_14_REDUC_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
#define DDR0_14_REDUC_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
#define DDR0_14_REG_DIMM_ENABLE_MASK 0x00000100
#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
#define DDR0_14_REG_DIMM_ENABLE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
#define DDR0_15 0x0F
#define DDR0_16 0x10
#define DDR0_17 0x11
#define DDR0_17_DLL_DQS_DELAY_0_MASK 0x7F000000
#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */
#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000
#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000
#define DDR0_17_DLLLOCKREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
#define DDR0_17_DLLLOCKREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
#define DDR0_17_DLL_LOCK_MASK 0x00007F00 /* Read only */
#define DDR0_17_DLL_LOCK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_17_DLL_LOCK_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_18 0x12
#define DDR0_18_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
#define DDR0_18_DLL_DQS_DELAY_4_MASK 0x7F000000
#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
#define DDR0_18_DLL_DQS_DELAY_3_MASK 0x007F0000
#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
#define DDR0_18_DLL_DQS_DELAY_2_MASK 0x00007F00
#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_18_DLL_DQS_DELAY_1_MASK 0x0000007F
#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_19 0x13
#define DDR0_19_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
#define DDR0_19_DLL_DQS_DELAY_8_MASK 0x7F000000
#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
#define DDR0_19_DLL_DQS_DELAY_7_MASK 0x007F0000
#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
#define DDR0_19_DLL_DQS_DELAY_6_MASK 0x00007F00
#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_19_DLL_DQS_DELAY_5_MASK 0x0000007F
#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_20 0x14
#define DDR0_20_DLL_DQS_BYPASS_3_MASK 0x7F000000
#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
#define DDR0_20_DLL_DQS_BYPASS_2_MASK 0x007F0000
#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
#define DDR0_20_DLL_DQS_BYPASS_1_MASK 0x00007F00
#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_20_DLL_DQS_BYPASS_0_MASK 0x0000007F
#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_21 0x15
#define DDR0_21_DLL_DQS_BYPASS_7_MASK 0x7F000000
#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
#define DDR0_21_DLL_DQS_BYPASS_6_MASK 0x007F0000
#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
#define DDR0_21_DLL_DQS_BYPASS_5_MASK 0x00007F00
#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_21_DLL_DQS_BYPASS_4_MASK 0x0000007F
#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_22 0x16
/* ECC */
#define DDR0_22_CTRL_RAW_MASK 0x03000000
#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not being used */
#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC checking is on, but no attempts to correct*/
#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* No ECC RAM storage available */
#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC checking and correcting on */
#define DDR0_22_CTRL_RAW_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
#define DDR0_22_CTRL_RAW_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000
#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
#define DDR0_22_DQS_OUT_SHIFT_MASK 0x00007F00
#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_22_DQS_OUT_SHIFT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_22_DLL_DQS_BYPASS_8_MASK 0x0000007F
#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_23 0x17
#define DDR0_23_ODT_RD_MAP_CS0_MASK 0x03000000
#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
#define DDR0_23_ECC_C_SYND_MASK 0x00FF0000 /* Read only */
#define DDR0_23_ECC_C_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
#define DDR0_23_ECC_C_SYND_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
#define DDR0_23_ECC_U_SYND_MASK 0x0000FF00 /* Read only */
#define DDR0_23_ECC_U_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
#define DDR0_23_ECC_U_SYND_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
#define DDR0_23_FWC_MASK 0x00000001 /* Write only */
#define DDR0_23_FWC_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
#define DDR0_23_FWC_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
#define DDR0_24 0x18
#define DDR0_24_RTT_PAD_TERMINATION_MASK 0x03000000
#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
#define DDR0_24_ODT_WR_MAP_CS1_MASK 0x00030000
#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>16)&0x3)
#define DDR0_24_ODT_RD_MAP_CS1_MASK 0x00000300
#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<8)
#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>8)&0x3)
#define DDR0_24_ODT_WR_MAP_CS0_MASK 0x00000003
#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<0)
#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>0)&0x3)
#define DDR0_25 0x19
#define DDR0_25_VERSION_MASK 0xFFFF0000 /* Read only */
#define DDR0_25_VERSION_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
#define DDR0_25_VERSION_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK 0x000003FF /* Read only */
#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
#define DDR0_26 0x1A
#define DDR0_26_TRAS_MAX_MASK 0xFFFF0000
#define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
#define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
#define DDR0_26_TREF_MASK 0x00003FFF
#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
#define DDR0_27 0x1B
#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000
#define DDR0_27_EMRS_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16)
#define DDR0_27_EMRS_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF)
#define DDR0_27_TINIT_MASK 0x0000FFFF
#define DDR0_27_TINIT_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0)
#define DDR0_27_TINIT_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF)
#define DDR0_28 0x1C
#define DDR0_28_EMRS3_DATA_MASK 0x3FFF0000
#define DDR0_28_EMRS3_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16)
#define DDR0_28_EMRS3_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF)
#define DDR0_28_EMRS2_DATA_MASK 0x00003FFF
#define DDR0_28_EMRS2_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0)
#define DDR0_28_EMRS2_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF)
#define DDR0_29 0x1D
#define DDR0_30 0x1E
#define DDR0_31 0x1F
#define DDR0_31_XOR_CHECK_BITS_MASK 0x0000FFFF
#define DDR0_31_XOR_CHECK_BITS_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0)
#define DDR0_31_XOR_CHECK_BITS_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF)
#define DDR0_32 0x20
#define DDR0_32_OUT_OF_RANGE_ADDR_MASK 0xFFFFFFFF /* Read only */
#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
#define DDR0_33 0x21
#define DDR0_33_OUT_OF_RANGE_ADDR_MASK 0x00000001 /* Read only */
#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
#define DDR0_34 0x22
#define DDR0_34_ECC_U_ADDR_MASK 0xFFFFFFFF /* Read only */
#define DDR0_34_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
#define DDR0_34_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
#define DDR0_35 0x23
#define DDR0_35_ECC_U_ADDR_MASK 0x00000001 /* Read only */
#define DDR0_35_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
#define DDR0_35_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
#define DDR0_36 0x24
#define DDR0_36_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
#define DDR0_36_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
#define DDR0_36_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
#define DDR0_37 0x25
#define DDR0_37_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
#define DDR0_37_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
#define DDR0_37_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
#define DDR0_38 0x26
#define DDR0_38_ECC_C_ADDR_MASK 0xFFFFFFFF /* Read only */
#define DDR0_38_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
#define DDR0_38_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
#define DDR0_39 0x27
#define DDR0_39_ECC_C_ADDR_MASK 0x00000001 /* Read only */
#define DDR0_39_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
#define DDR0_39_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
#define DDR0_40 0x28
#define DDR0_40_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
#define DDR0_40_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
#define DDR0_40_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
#define DDR0_41 0x29
#define DDR0_41_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
#define DDR0_41_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
#define DDR0_41_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
#define DDR0_42 0x2A
#define DDR0_42_ADDR_PINS_MASK 0x07000000
#define DDR0_42_ADDR_PINS_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
#define DDR0_42_ADDR_PINS_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
#define DDR0_42_CASLAT_LIN_GATE_MASK 0x0000000F
#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n) ((((unsigned long)(n))&0xF)<<0)
#define DDR0_42_CASLAT_LIN_GATE_DECODE(n) ((((unsigned long)(n))>>0)&0xF)
#define DDR0_43 0x2B
#define DDR0_43_TWR_MASK 0x07000000
#define DDR0_43_TWR_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
#define DDR0_43_TWR_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
#define DDR0_43_APREBIT_MASK 0x000F0000
#define DDR0_43_APREBIT_ENCODE(n) ((((unsigned long)(n))&0xF)<<16)
#define DDR0_43_APREBIT_DECODE(n) ((((unsigned long)(n))>>16)&0xF)
#define DDR0_43_COLUMN_SIZE_MASK 0x00000700
#define DDR0_43_COLUMN_SIZE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
#define DDR0_43_COLUMN_SIZE_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
#define DDR0_43_EIGHT_BANK_MODE_MASK 0x00000001
#define DDR0_43_EIGHT_BANK_MODE_8_BANKS 0x00000001
#define DDR0_43_EIGHT_BANK_MODE_4_BANKS 0x00000000
#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
#define DDR0_43_EIGHT_BANK_MODE_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
#define DDR0_44 0x2C
#define DDR0_44_TRCD_MASK 0x000000FF
#define DDR0_44_TRCD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
#define DDR0_44_TRCD_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
#endif /* _SPD_SDRAM_DENALI_H_ */

4
board/freescale/common/Makefile
View File

@ -31,7 +31,9 @@ LIB = $(obj)lib$(VENDOR).a
COBJS := sys_eeprom.o \
pixis.o \
pq-mds-pib.o
pq-mds-pib.o \
fsl_logo_bmp.o \
fsl_diu_fb.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

618
board/freescale/common/fsl_diu_fb.c Normal file
View File

@ -0,0 +1,618 @@
/*
* Copyright 2007 Freescale Semiconductor, Inc.
* York Sun <yorksun@freescale.com>
*
* FSL DIU Framebuffer driver
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <i2c.h>
#include <malloc.h>
#ifdef CONFIG_FSL_DIU_FB
#include "fsl_diu_fb.h"
#ifdef DEBUG
#define DPRINTF(fmt, args...) printf("%s: " fmt,__FUNCTION__,## args)
#else
#define DPRINTF(fmt, args...)
#endif
struct fb_videomode {
const char *name; /* optional */
unsigned int refresh; /* optional */
unsigned int xres;
unsigned int yres;
unsigned int pixclock;
unsigned int left_margin;
unsigned int right_margin;
unsigned int upper_margin;
unsigned int lower_margin;
unsigned int hsync_len;
unsigned int vsync_len;
unsigned int sync;
unsigned int vmode;
unsigned int flag;
};
#define FB_SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */
#define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */
#define FB_VMODE_NONINTERLACED 0 /* non interlaced */
/*
* These parameters give default parameters
* for video output 1024x768,
* FIXME - change timing to proper amounts
* hsync 31.5kHz, vsync 60Hz
*/
static struct fb_videomode fsl_diu_mode_1024 = {
.refresh = 60,
.xres = 1024,
.yres = 768,
.pixclock = 15385,
.left_margin = 160,
.right_margin = 24,
.upper_margin = 29,
.lower_margin = 3,
.hsync_len = 136,
.vsync_len = 6,
.sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED
};
static struct fb_videomode fsl_diu_mode_1280 = {
.name = "1280x1024-60",
.refresh = 60,
.xres = 1280,
.yres = 1024,
.pixclock = 9375,
.left_margin = 38,
.right_margin = 128,
.upper_margin = 2,
.lower_margin = 7,
.hsync_len = 216,
.vsync_len = 37,
.sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED
};
/*
* These are the fields of area descriptor(in DDR memory) for every plane
*/
struct diu_ad {
/* Word 0(32-bit) in DDR memory */
unsigned int pix_fmt; /* hard coding pixel format */
/* Word 1(32-bit) in DDR memory */
unsigned int addr;
/* Word 2(32-bit) in DDR memory */
unsigned int src_size_g_alpha;
/* Word 3(32-bit) in DDR memory */
unsigned int aoi_size;
/* Word 4(32-bit) in DDR memory */
unsigned int offset_xyi;
/* Word 5(32-bit) in DDR memory */
unsigned int offset_xyd;
/* Word 6(32-bit) in DDR memory */
unsigned int ckmax_r:8;
unsigned int ckmax_g:8;
unsigned int ckmax_b:8;
unsigned int res9:8;
/* Word 7(32-bit) in DDR memory */
unsigned int ckmin_r:8;
unsigned int ckmin_g:8;
unsigned int ckmin_b:8;
unsigned int res10:8;
/* Word 8(32-bit) in DDR memory */
unsigned int next_ad;
/* Word 9(32-bit) in DDR memory, just for 64-bit aligned */
unsigned int res1;
unsigned int res2;
unsigned int res3;
}__attribute__ ((packed));
/*
* DIU register map
*/
struct diu {
unsigned int desc[3];
unsigned int gamma;
unsigned int pallete;
unsigned int cursor;
unsigned int curs_pos;
unsigned int diu_mode;
unsigned int bgnd;
unsigned int bgnd_wb;
unsigned int disp_size;
unsigned int wb_size;
unsigned int wb_mem_addr;
unsigned int hsyn_para;
unsigned int vsyn_para;
unsigned int syn_pol;
unsigned int thresholds;
unsigned int int_status;
unsigned int int_mask;
unsigned int colorbar[8];
unsigned int filling;
unsigned int plut;
} __attribute__ ((packed));
struct diu_hw {
struct diu *diu_reg;
volatile unsigned int mode; /* DIU operation mode */
};
struct diu_addr {
unsigned char * paddr; /* Virtual address */
unsigned int offset;
};
#define FSL_DIU_BASE_OFFSET 0x2C000 /* Offset of Display Interface Unit */
/*
* Modes of operation of DIU
*/
#define MFB_MODE0 0 /* DIU off */
#define MFB_MODE1 1 /* All three planes output to display */
#define MFB_MODE2 2 /* Plane 1 to display,
* planes 2+3 written back to memory */
#define MFB_MODE3 3 /* All three planes written back to memory */
#define MFB_MODE4 4 /* Color bar generation */
#define MAX_CURS 32
static struct fb_info fsl_fb_info;
static struct diu_addr gamma, cursor;
static struct diu_ad fsl_diu_fb_ad __attribute__ ((aligned(32)));
static struct diu_ad dummy_ad __attribute__ ((aligned(32)));
static unsigned char *dummy_fb;
static struct diu_hw dr = {
.mode = MFB_MODE1,
};
int fb_enabled = 0;
int fb_initialized = 0;
const int default_xres = 1280;
const int default_pixel_format = 0x88882317;
static int map_video_memory(struct fb_info *info, unsigned long bytes_align);
static void enable_lcdc(void);
static void disable_lcdc(void);
static int fsl_diu_enable_panel(struct fb_info *info);
static int fsl_diu_disable_panel(struct fb_info *info);
static int allocate_buf(struct diu_addr *buf, u32 size, u32 bytes_align);
static u32 get_busfreq(void);
int fsl_diu_init(int xres,
unsigned int pixel_format,
int gamma_fix,
unsigned char *splash_bmp)
{
struct fb_videomode *fsl_diu_mode_db;
struct diu_ad *ad = &fsl_diu_fb_ad;
struct diu *hw;
struct fb_info *info = &fsl_fb_info;
struct fb_var_screeninfo *var = &info->var;
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
volatile unsigned int *guts_clkdvdr = &gur->clkdvdr;
unsigned char *gamma_table_base;
unsigned int i, j;
unsigned long speed_ccb, temp, pixval;
DPRINTF("Enter fsl_diu_init\n");
dr.diu_reg = (struct diu *) (CFG_IMMR + FSL_DIU_BASE_OFFSET);
hw = (struct diu *) dr.diu_reg;
disable_lcdc();
if (xres == 1280) {
fsl_diu_mode_db = &fsl_diu_mode_1280;
} else {
fsl_diu_mode_db = &fsl_diu_mode_1024;
}
if (0 == fb_initialized) {
allocate_buf(&gamma, 768, 32);
DPRINTF("gamma is allocated @ 0x%x\n",
(unsigned int)gamma.paddr);
allocate_buf(&cursor, MAX_CURS * MAX_CURS * 2, 32);
DPRINTF("curosr is allocated @ 0x%x\n",
(unsigned int)cursor.paddr);
/* create a dummy fb and dummy ad */
dummy_fb = malloc(64);
if (NULL == dummy_fb) {
printf("Cannot allocate dummy fb\n");
return -1;
}
dummy_ad.addr = cpu_to_le32((unsigned int)dummy_fb);
dummy_ad.pix_fmt = 0x88882317;
dummy_ad.src_size_g_alpha = 0x04400000; /* alpha = 0 */
dummy_ad.aoi_size = 0x02000400;
dummy_ad.offset_xyi = 0;
dummy_ad.offset_xyd = 0;
dummy_ad.next_ad = 0;
/* Memory allocation for framebuffer */
if (map_video_memory(info, 32)) {
printf("Unable to allocate fb memory 1\n");
return -1;
}
} else {
memset(info->screen_base, 0, info->smem_len);
}
dr.diu_reg->desc[0] = (unsigned int) &dummy_ad;
dr.diu_reg->desc[1] = (unsigned int) &dummy_ad;
dr.diu_reg->desc[2] = (unsigned int) &dummy_ad;
DPRINTF("dummy dr.diu_reg->desc[0] = 0x%x\n", dr.diu_reg->desc[0]);
DPRINTF("dummy desc[0] = 0x%x\n", hw->desc[0]);
/* read mode info */
var->xres = fsl_diu_mode_db->xres;
var->yres = fsl_diu_mode_db->yres;
var->bits_per_pixel = 32;
var->pixclock = fsl_diu_mode_db->pixclock;
var->left_margin = fsl_diu_mode_db->left_margin;
var->right_margin = fsl_diu_mode_db->right_margin;
var->upper_margin = fsl_diu_mode_db->upper_margin;
var->lower_margin = fsl_diu_mode_db->lower_margin;
var->hsync_len = fsl_diu_mode_db->hsync_len;
var->vsync_len = fsl_diu_mode_db->vsync_len;
var->sync = fsl_diu_mode_db->sync;
var->vmode = fsl_diu_mode_db->vmode;
info->line_length = var->xres * var->bits_per_pixel / 8;
info->logo_size = 0;
info->logo_height = 0;
ad->pix_fmt = pixel_format;
ad->addr = cpu_to_le32((unsigned int)info->screen_base);
ad->src_size_g_alpha
= cpu_to_le32((var->yres << 12) | var->xres);
/* fix me. AOI should not be greater than display size */
ad->aoi_size = cpu_to_le32(( var->yres << 16) | var->xres);
ad->offset_xyi = 0;
ad->offset_xyd = 0;
/* Disable chroma keying function */
ad->ckmax_r = 0;
ad->ckmax_g = 0;
ad->ckmax_b = 0;
ad->ckmin_r = 255;
ad->ckmin_g = 255;
ad->ckmin_b = 255;
gamma_table_base = gamma.paddr;
DPRINTF("gamma_table_base is allocated @ 0x%x\n",
(unsigned int)gamma_table_base);
/* Prep for DIU init - gamma table */
for (i = 0; i <= 2; i++)
for (j = 0; j <= 255; j++)
*gamma_table_base++ = j;
if (gamma_fix == 1) { /* fix the gamma */
DPRINTF("Fix gamma table\n");
gamma_table_base = gamma.paddr;
for (i = 0; i < 256*3; i++) {
gamma_table_base[i] = (gamma_table_base[i] << 2)
| ((gamma_table_base[i] >> 6) & 0x03);
}
}
DPRINTF("update-lcdc: HW - %p\n Disabling DIU\n", hw);
/* Program DIU registers */
hw->gamma = (unsigned int) gamma.paddr;
hw->cursor= (unsigned int) cursor.paddr;
hw->bgnd = 0x007F7F7F; /* BGND */
hw->bgnd_wb = 0; /* BGND_WB */
hw->disp_size = var->yres << 16 | var->xres; /* DISP SIZE */
hw->wb_size = 0; /* WB SIZE */
hw->wb_mem_addr = 0; /* WB MEM ADDR */
hw->hsyn_para = var->left_margin << 22 | /* BP_H */
var->hsync_len << 11 | /* PW_H */
var->right_margin; /* FP_H */
hw->vsyn_para = var->upper_margin << 22 | /* BP_V */
var->vsync_len << 11 | /* PW_V */
var->lower_margin; /* FP_V */
/* Pixel Clock configuration */
DPRINTF("DIU: Bus Frequency = %d\n", get_busfreq());
speed_ccb = get_busfreq();
DPRINTF("DIU pixclock in ps - %d\n", var->pixclock);
temp = 1;
temp *= 1000000000;
temp /= var->pixclock;
temp *= 1000;
pixval = speed_ccb / temp;
DPRINTF("DIU pixval = %lu\n", pixval);
hw->syn_pol = 0; /* SYNC SIGNALS POLARITY */
hw->thresholds = 0x00037800; /* The Thresholds */
hw->int_status = 0; /* INTERRUPT STATUS */
hw->int_mask = 0; /* INT MASK */
hw->plut = 0x01F5F666;
/* Modify PXCLK in GUTS CLKDVDR */
DPRINTF("DIU: Current value of CLKDVDR = 0x%08x\n", *guts_clkdvdr);
temp = *guts_clkdvdr & 0x2000FFFF;
*guts_clkdvdr = temp; /* turn off clock */
*guts_clkdvdr = temp | 0x80000000 | ((pixval & 0x1F) << 16);
DPRINTF("DIU: Modified value of CLKDVDR = 0x%08x\n", *guts_clkdvdr);
fb_initialized = 1;
if (splash_bmp) {
info->logo_height = fsl_diu_display_bmp(splash_bmp, 0, 0, 0);
info->logo_size = info->logo_height * info->line_length;
DPRINTF("logo height %d, logo_size 0x%x\n",
info->logo_height,info->logo_size);
}
/* Enable the DIU */
fsl_diu_enable_panel(info);
enable_lcdc();
return 0;
}
char *fsl_fb_open(struct fb_info **info)
{
*info = &fsl_fb_info;
return (char *) ((unsigned int)(*info)->screen_base
+ (*info)->logo_size);
}
void fsl_diu_close(void)
{
struct fb_info *info = &fsl_fb_info;
fsl_diu_disable_panel(info);
}
static int fsl_diu_enable_panel(struct fb_info *info)
{
struct diu *hw = dr.diu_reg;
struct diu_ad *ad = &fsl_diu_fb_ad;
DPRINTF("Entered: enable_panel\n");
if (hw->desc[0] != (unsigned int)ad)
hw->desc[0] = (unsigned int)ad;
DPRINTF("desc[0] = 0x%x\n", hw->desc[0]);
return 0;
}
static int fsl_diu_disable_panel(struct fb_info *info)
{
struct diu *hw = dr.diu_reg;
DPRINTF("Entered: disable_panel\n");
if (hw->desc[0] != (unsigned int)&dummy_ad)
hw->desc[0] = (unsigned int)&dummy_ad;
return 0;
}
static int map_video_memory(struct fb_info *info, unsigned long bytes_align)
{
unsigned long offset;
unsigned long mask;
DPRINTF("Entered: map_video_memory\n");
/* allocate maximum 1280*1024 with 32bpp */
info->smem_len = 1280 * 4 *1024 + bytes_align;
DPRINTF("MAP_VIDEO_MEMORY: smem_len = %d\n", info->smem_len);
info->screen_base = malloc(info->smem_len);
if (info->screen_base == NULL) {
printf("Unable to allocate fb memory\n");
return -1;
}
info->smem_start = (unsigned int) info->screen_base;
mask = bytes_align - 1;
offset = (unsigned long)info->screen_base & mask;
if (offset) {
info->screen_base += offset;
info->smem_len = info->smem_len - (bytes_align - offset);
} else
info->smem_len = info->smem_len - bytes_align;
info->screen_size = info->smem_len;
DPRINTF("Allocated fb @ 0x%08lx, size=%d.\n",
info->smem_start, info->smem_len);
return 0;
}
static void enable_lcdc(void)
{
struct diu *hw = dr.diu_reg;
DPRINTF("Entered: enable_lcdc, fb_enabled = %d\n", fb_enabled);
if (!fb_enabled) {
hw->diu_mode = dr.mode;
fb_enabled++;
}
DPRINTF("diu_mode = %d\n", hw->diu_mode);
}
static void disable_lcdc(void)
{
struct diu *hw = dr.diu_reg;
DPRINTF("Entered: disable_lcdc, fb_enabled = %d\n", fb_enabled);
if (fb_enabled) {
hw->diu_mode = 0;
fb_enabled = 0;
}
}
static u32 get_busfreq(void)
{
u32 fs_busfreq = 0;
fs_busfreq = get_bus_freq(0);
return fs_busfreq;
}
/*
* Align to 64-bit(8-byte), 32-byte, etc.
*/
static int allocate_buf(struct diu_addr *buf, u32 size, u32 bytes_align)
{
u32 offset, ssize;
u32 mask;
DPRINTF("Entered: allocate_buf\n");
ssize = size + bytes_align;
buf->paddr = malloc(ssize);
if (!buf->paddr)
return -1;
memset(buf->paddr, 0, ssize);
mask = bytes_align - 1;
offset = (u32)buf->paddr & mask;
if (offset) {
buf->offset = bytes_align - offset;
buf->paddr = (unsigned char *) ((u32)buf->paddr + offset);
} else
buf->offset = 0;
return 0;
}
int fsl_diu_display_bmp(unsigned char *bmp,
int xoffset,
int yoffset,
int transpar)
{
struct fb_info *info = &fsl_fb_info;
unsigned char r, g, b;
unsigned int *fb_t, val;
unsigned char *bitmap;
unsigned int palette[256];
int width, height, bpp, ncolors, raster, offset, x, y, i, k, cpp;
if (!bmp) {
printf("Must supply a bitmap address\n");
return 0;
}
raster = bmp[10] + (bmp[11] << 8) + (bmp[12] << 16) + (bmp[13] << 24);
width = (bmp[21] << 24) | (bmp[20] << 16) | (bmp[19] << 8) | bmp[18];
height = (bmp[25] << 24) | (bmp[24] << 16) | (bmp[23] << 8) | bmp[22];
bpp = (bmp[29] << 8) | (bmp[28]);
ncolors = bmp[46] + (bmp[47] << 8) + (bmp[48] << 16) + (bmp[49] << 24);
bitmap = bmp + raster;
cpp = info->var.bits_per_pixel / 8;
DPRINTF("bmp = 0x%08x\n", (unsigned int)bmp);
DPRINTF("bitmap = 0x%08x\n", (unsigned int)bitmap);
DPRINTF("width = %d\n", width);
DPRINTF("height = %d\n", height);
DPRINTF("bpp = %d\n", bpp);
DPRINTF("ncolors = %d\n", ncolors);
DPRINTF("xres = %d\n", info->var.xres);
DPRINTF("yres = %d\n", info->var.yres);
DPRINTF("Screen_base = 0x%x\n", (unsigned int)info->screen_base);
if (((width+xoffset) > info->var.xres) ||
((height+yoffset) > info->var.yres)) {
printf("bitmap is out of range, image too large or too much offset\n");
return 0;
}
if (bpp < 24) {
for (i = 0, offset = 54; i < ncolors; i++, offset += 4)
palette[i] = (bmp[offset+2] << 16)
+ (bmp[offset+1] << 8) + bmp[offset];
}
switch (bpp) {
case 1:
for (y = height - 1; y >= 0; y--) {
fb_t = (unsigned int *) ((unsigned int)info->screen_base + (((y+yoffset) * info->var.xres) + xoffset)*cpp);
for (x = 0; x < width; x += 8) {
b = *bitmap++;
for (k = 0; k < 8; k++) {
if (b & 0x80)
*fb_t = palette[1];
else
*fb_t = palette[0];
b = b << 1;
}
}
for (i = (width / 2) % 4; i > 0; i--)
bitmap++;
}
break;
case 4:
for (y = height - 1; y >= 0; y--) {
fb_t = (unsigned int *) ((unsigned int)info->screen_base + (((y+yoffset) * info->var.xres) + xoffset)*cpp);
for (x = 0; x < width; x += 2) {
b = *bitmap++;
r = (b >> 4) & 0x0F;
g = b & 0x0F;
*fb_t++ = palette[r];
*fb_t++ = palette[g];
}
for (i = (width / 2) % 4; i > 0; i--)
bitmap++;
}
break;
case 8:
for (y = height - 1; y >= 0; y--) {
fb_t = (unsigned int *) ((unsigned int)info->screen_base + (((y+yoffset) * info->var.xres) + xoffset)*cpp);
for (x = 0; x < width; x++) {
*fb_t++ = palette[ *bitmap++ ];
}
for (i = (width / 2) % 4; i > 0; i--)
bitmap++;
}
break;
case 24:
for (y = height - 1; y >= 0; y--) {
fb_t = (unsigned int *) ((unsigned int)info->screen_base + (((y+yoffset) * info->var.xres) + xoffset)*cpp);
for (x = 0; x < width; x++) {
b = *bitmap++;
g = *bitmap++;
r = *bitmap++;
val = (r << 16) + (g << 8) + b;
*fb_t++ = val;
}
for (; (x % 4) != 0; x++) /* 4-byte alignment */
bitmap++;
}
break;
}
return height;
}
void fsl_diu_clear_screen(void)
{
struct fb_info *info = &fsl_fb_info;
memset(info->screen_base, 0, info->smem_len);
}
#endif /* CONFIG_FSL_DIU_FB */

69
board/freescale/common/fsl_diu_fb.h Normal file
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@ -0,0 +1,69 @@
/*
* Copyright 2007 Freescale Semiconductor, Inc.
* York Sun <yorksun@freescale.com>
*
* FSL DIU Framebuffer driver
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
struct fb_var_screeninfo {
unsigned int xres; /* visible resolution */
unsigned int yres;
unsigned int bits_per_pixel; /* guess what */
/* Timing: All values in pixclocks, except pixclock (of course) */
unsigned int pixclock; /* pixel clock in ps (pico seconds) */
unsigned int left_margin; /* time from sync to picture */
unsigned int right_margin; /* time from picture to sync */
unsigned int upper_margin; /* time from sync to picture */
unsigned int lower_margin;
unsigned int hsync_len; /* length of horizontal sync */
unsigned int vsync_len; /* length of vertical sync */
unsigned int sync; /* see FB_SYNC_* */
unsigned int vmode; /* see FB_VMODE_* */
unsigned int rotate; /* angle we rotate counter clockwise */
};
struct fb_info {
struct fb_var_screeninfo var; /* Current var */
unsigned long smem_start; /* Start of frame buffer mem */
/* (physical address) */
unsigned int smem_len; /* Length of frame buffer mem */
unsigned int type; /* see FB_TYPE_* */
unsigned int line_length; /* length of a line in bytes */
char *screen_base;
unsigned long screen_size;
int logo_height;
unsigned int logo_size;
};
extern char *fsl_fb_open(struct fb_info **info);
extern int fsl_diu_init(int xres,
unsigned int pixel_format,
int gamma_fix,
unsigned char *splash_bmp);
extern void fsl_diu_clear_screen(void);
extern int fsl_diu_display_bmp(unsigned char *bmp,
int xoffset,
int yoffset,
int transpar);

878
board/freescale/common/fsl_logo_bmp.c Normal file
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@ -0,0 +1,878 @@
/*
* Copyright 2007 Freescale Semiconductor, Inc.
* York Sun <yorksun@freescale.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*---------------------------------------------------------------------------
* FSL_Logo_BMP --
*
* A 340x128x4bpp BMP logo.
*---------------------------------------------------------------------------
*/
unsigned int FSL_Logo_BMP[] = {
0x424d765c,
0x00000000,0x00007600,0x00002800,0x00006c01,0x00008000,0x00000100,0x04000000,
0x0000005c,0x0000130b,0x0000130b,0x00001000,0x00000000,0x00000402,0x04000d91,
0xbc000b51,0x67001536,0x9a000f2a,0x4b005050,0x50009090,0x90000c70,0x92002e2f,
0x2e00cfcf,0xcf007c82,0x7c00fbfd,0xfb006f70,0x6f00b0b0,0xb00004bd,0xfa000542,
0xf9000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0xa9996500,0x0000a999,
0xa80000aa,0x400006a0,0x00086500,0x86500008,0x699da800,0x0000c999,0x68000056,
0x5000006a,0x00000a99,0x9a0c6800,0x08699685,0xa5000086,0x99dc4000,0x05999800,
0x08699dc0,0x0000a600,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x0000008b,0xbb99bbd4,0x004bbb99,0xbba0009b,0x50000bb4,0x0008b900,
0x5b90005b,0xbb99bbc0,0x0009bb99,0xbb60005b,0xd00000bb,0x0004bbbb,0xbbb9ba00,
0x4bbbbbbd,0xbd000cbb,0xb9bbb500,0x0cbbba00,0x5bbb9bbb,0x5000db50,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x0000006b,0x980006bd,
0x006b9800,0x89ba006b,0x600009b5,0x0000bb00,0x4bb000bb,0xd00059bc,0x006b9800,
0x89bd008b,0xb00000db,0x5006bb50,0x089bbd00,0x5bbc086b,0xb9000bb6,0x00059b50,
0x0cbd0000,0xbb6000c9,0xb500dba0,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x0000009b,0xa00008bb,0x80bb5000,0x00bb805b,0xd00006ba,
0x00009b50,0x09b405bb,0x000008bb,0x409bc000,0x049bc009,0xb000006b,0xa009b600,
0x0009b900,0x5b900005,0xbb005bb0,0x00005bb0,0x08b90005,0xbb00000c,0xb900cbd0,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x0000005c,
0x800008bb,0x80bb8000,0x0088008b,0x90000cbd,0x0000dbc0,0x0db505b9,0x0000006d,
0x50bb8000,0x005b9009,0xb50000cb,0xd00bb500,0x0008bb00,0x8b900000,0x9b50cb90,
0x000006d5,0x00bb000c,0xbd000000,0x9bc08b90,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00ca9bbb,0x00bb5585,0x8558500b,
0xb00008b9,0x0000cbd0,0x06ba05bb,0x00000000,0x00bb5000,0x000bb806,0xba00008b,
0x9009b500,0x00009b50,0x0bb00000,0xdbc05b90,0x00000000,0x009b500c,0xb9000000,
0xcb900bb0,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0xdbbbbb68,0x009bbbbb,0xbbbbb009,0xb50000bb,0x00008b90,0x05b900bb,
0x40000000,0x009bc000,0x0009bc0c,0xbd00000b,0xb009ba00,0x00006bc0,0x09b50000,
0xcb608bb0,0x00000000,0x00dbc008,0xbb000000,0x8bb009b8,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000005,0xbb9c8000,0x00cb9555,
0xc55bb406,0xba00009b,0x50000bb0,0x08bb009b,0xc0000000,0x00abd000,0x000dbc08,
0xbb00000d,0xb50cb900,0x0000abd0,0x0dbc0000,0x8b9009b5,0x00000000,0x00cbd000,
0xbb500000,0x8bb006b6,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x0000000c,0xbd000059,0xa08bb800,0x008bb00c,0xb90000db,0xa00009b8,
0x009b40cb,0x90000089,0x900bb800,0x0009bc00,0xbb50000d,0xbc00bb50,0x0000db90,
0x0cb60000,0x0bb00cb9,0x00000899,0x008b9000,0xab900000,0x8bb00cbb,0x80000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000008,0xb90000ab,
0x900ab940,0x00ab9008,0xbb60009b,0xbc000bb8,0x009b5009,0xbd00006b,0xb00cbb80,
0x005bb800,0xdb950009,0xba00cbb5,0x0005bbb0,0x08b90000,0x09b8009b,0xd00006b9,
0x000bb000,0x09bd0000,0xdb9005bb,0x9c880000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0xdb96cdbb,0xc000db96,0xcdbbc000,0xbbb999bb,
0x6b9dbbb4,0x006bc000,0x9b96cdbb,0xc0006bb6,0xc69bd000,0x6bbb9dbb,0xb50006bb,
0x96db9bb8,0x00bb0000,0x0dbc0049,0xb9acdbbc,0x069bb995,0x089b9aad,0xbb5000bb,
0xdbbb0000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x059bbb9c,0x00000c9b,0xbbbc0000,0xd98dbbb6,0x059bbb50,0x00596000,0x0c9bbb9c,
0x0000089b,0xbbb60000,0xc96c9bbb,0x6000005d,0xbbb9cdbc,0x00998000,0x0c960000,
0xa9bbb9c0,0x0a9bbb9a,0x000a9bbb,0x950000d9,0x8c9b5000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00008400,0x00000000,0x84000000,
0x00004800,0x00048000,0x00000000,0x00048800,0x00000000,0x88000000,0x00000880,
0x00000000,0x08800cb6,0x00000000,0x00000000,0x00488000,0x000ab600,0x00000488,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x000005b9,0x00000000,
0x00000000,0x00000000,0x0005b900,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x000000bb,0x00000000,0x00000000,0x00000000,0x0000bb00,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x000a9c00,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x0000009b,
0x80000000,0x00000000,0x00000000,0x0000cc00,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x000cbd00,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x000000db,0x50000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x0004c500,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x0000005c,0x50000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x008a66d6,0x6a580000,0x00000000,0x00000000,0x000008c6,
0xd6d6a580,0x00000000,0x00000000,0x000008ca,0x6d6d6a58,0x00000000,0x00000000,
0x00000004,0x5a6d6da5,0x80000000,0x00000000,0x00008c6d,0x66c50000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x005cad6d,0x6a580000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00033400,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000009,
0x99d9999d,0x50000000,0x00a999d9,0x99960000,0x00000000,0x00000008,0xdbbbbbbb,
0xbbbb9650,0x00000000,0x00000000,0x008dbbbb,0xbbbbbbb9,0x65000000,0x00000000,
0x005dbbbb,0xbbbbbbbb,0x96800000,0x00000000,0x00000c9b,0xbbbbbbbb,0xb9640000,
0x00000000,0x00c9bbbb,0xbbbbbd80,0x00c999d9,0x99980000,0x06999d99,0x99600000,
0x00000008,0x6bbbbbbb,0xbbbb9d50,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x04ffff30,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000009,0xbbbbbbbb,0xd0000000,0x00cbbbbb,
0xbbbb0000,0x00000000,0x000004db,0xbbbbbbbb,0xbbbbbbb9,0x50000000,0x00000000,
0x06bbbbbb,0xbbbbbbbb,0xbb950000,0x00000000,0x59bbbbbb,0xbbbbbbbb,0xbbb95000,
0x00000000,0x00059bbb,0xbbbbbbbb,0xbbbb6800,0x00000000,0x89bbbbbb,0xbbbbbbb9,
0x806bbbbb,0xbbb40000,0x0abbbbbb,0xbbb00000,0x0000006b,0xbbbbbbbb,0xbbbbbbb9,
0x50000000,0x00000000,0x00000000,0x00000000,0x00000004,0xffffffff,0x40000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x0000000d,0xbbbbbbbb,0x90000000,0x005bbbbb,0xbbbb8000,0x00000000,0x000089bb,
0xbbbbbbbb,0xbbbbbbbb,0xbd800000,0x00000008,0x9bbbbbbb,0xbbbbbbbb,0xbbbb9800,
0x0000000d,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbd00,0x00000000,0x00cbbbbb,0xbbbbbbbb,
0xbbbbbbc0,0x00000000,0xdbbbbbbb,0xbbbbbbbb,0xba6bbbbb,0xbbb80000,0x05bbbbbb,
0xbbb40000,0x000009bb,0xbbbbbbbb,0xbbbbbbbb,0xb9800000,0x00000000,0x00000000,
0x00000000,0x000004ff,0xffffffff,0xf3400000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x0000000a,0xbbbbbbbb,0xb0000000,
0x008bbbbb,0xbbbbc000,0x00000000,0x0000bbbb,0xbbbbbbbb,0xbbbbbbbb,0xbb950000,
0x00000009,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbc0,0x0000089b,0xbbbbbbbb,0xbbbbbbbb,
0xbbbbbb98,0x00000000,0x0abbbbbb,0xbbbbbbbb,0xbbbbbbbd,0x4000000c,0xbbbbbbbb,
0xbbbbbbbb,0xbb9bbbbb,0xbbb80000,0x08bbbbbb,0xbbb50000,0x00049bbb,0xbbbbbbbb,
0xbbbbbbbb,0xbbbc0000,0x00000000,0x00000000,0x00000000,0x0004ffff,0xffffffff,
0xfff30000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000005,0xbbbbbbbb,0xb8000000,0x0009bbbb,0xbbbb6000,0x00000000,
0x0009bbbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbc000,0x000000db,0xbbbbbbbb,0xbbbbbbbb,
0xbbbbbbb6,0x000089bb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0x80000000,0x8bbbbbbb,
0xbbbbbbbb,0xbbbbbbbb,0x95000009,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xbbb50000,
0x00bbbbbb,0xbbb60000,0x0006bbbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbba000,0x00000000,
0x00000000,0x00000000,0x043fffff,0xffffffff,0xfffff400,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0xbbbbbbbb,
0xbc000000,0x000dbbbb,0xbbbb9000,0x00000000,0x005bbbbb,0xbbbbbbbb,0xbbbbbbbb,
0xbbbbbc00,0x000008bb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0x60009bbb,0xbbbbbbbb,
0xbbbbbbbb,0xbbbbbbbb,0x90000000,0x9bbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xbb80000b,
0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbc0000,0x009bbbbb,0xbbbd0000,0x008bbbbb,
0xbbbbbbbb,0xbbbbbbbb,0xbbbbbd00,0x00000000,0x00000000,0x00000000,0x003fffff,
0xffffffff,0xfffffff0,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0xbbbbbbbb,0xb6000000,0x000abbbb,0xbbbbb000,
0x00000000,0x009bbbbb,0xbbbbbb65,0x5569bbbb,0xbbbbbbc0,0x00000dbb,0xbbbbbbbb,
0xb6c5569b,0xbbbbbbbb,0xba08bbbb,0xbbbbbbbb,0x96c55c6b,0xbbbbbbbb,0xb6000005,
0xbbbbbbbb,0xbbbbbddd,0x9bbbbbbb,0xbbb8004b,0xbbbbbbbb,0xb9655cdb,0xbbbbbbbb,
0xbbbd0000,0x006bbbbb,0xbbbb0000,0x00dbbbbb,0xbbbbbbdc,0x8c69bbbb,0xbbbbbbc0,
0x00000000,0x00000000,0x00000000,0x0004ffff,0xffffffff,0xffffffff,0x30000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0xdbbbbbbb,0xb9000000,0x0005bbbb,0xbbbbb800,0x00000000,0x00bbbbbb,0xbbbbd000,
0x0000cbbb,0xbbbbbbb8,0x00000bbb,0xbbbbbbb9,0x0000000c,0xbbbbbbbb,0xbb5006bb,
0xbbbbbbd8,0x00000000,0x6bbbbbbb,0xbb400006,0xbbbbbbbb,0xbbb50000,0x08dbbbbb,
0xbbb9000b,0xbbbbbbbb,0x94000008,0xdbbbbbbb,0xbbb90000,0x00cbbbbb,0xbbbb4000,
0x00bbbbbb,0xbbbbd400,0x0000cbbb,0xbbbbbbb5,0x00000000,0x00000000,0x00000000,
0x000004ff,0xffffffff,0xffffffff,0xff400000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x6bbbbbbb,0xbb000000,0x0008bbbb,
0xbbbbb500,0x00000000,0x0cbbbbbb,0xbbb90000,0x000008bb,0xbbbbbb95,0x00008bbb,
0xbbbbbb98,0x00000000,0x49bbbbbb,0xbbc0008d,0xbbbbb500,0x00000000,0x0dbbbbbb,
0xbbc0000b,0xbbbbbbbb,0xbb800000,0x0005bbbb,0xbb98000b,0xbbbbbbbb,0xc0000000,
0x06bbbbbb,0xbbbb0000,0x008bbbbb,0xbbbb5000,0x08bbbbbb,0xbbb98000,0x0000089b,
0xbbbbbbbc,0x00000000,0x00000000,0x00000000,0x00000043,0xffffffff,0xffffffff,
0xfff34000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x5bbbbbbb,0xbb800000,0x0000bbbb,0xbbbbb600,0x00000000,0x0abbbbbb,
0xbbb50000,0x00000009,0xbbbbbc00,0x0000cbbb,0xbbbbbbc0,0x00000000,0x089bbbbb,
0xa0000000,0xc9bb8000,0x00000000,0x05bbbbbb,0xbb90000b,0xbbbbbbbb,0xbc000000,
0x00005bbb,0x95000009,0xbbbbbbbb,0x50000000,0x009bbbbb,0xbbbb5000,0x000bbbbb,
0xbbbba000,0x0cbbbbbb,0xbbbc0000,0x00000049,0xbbbbba00,0x00000000,0x00000000,
0x00000000,0x00000000,0x4fffffff,0xffffffff,0xfffff300,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x8bbbbbbb,0xbb500000,
0x0000dbbb,0xbbbbb900,0x00000000,0x06bbbbbb,0xbbb00000,0x00000004,0xbbbc0000,
0x0000abbb,0xbbbbbb40,0x00000000,0x0089bba0,0x00000000,0x00680000,0x00000000,
0x0abbbbbb,0xbbb0008b,0xbbbbbbbb,0xb8000000,0x00000695,0x0000000c,0xbbbbbbbb,
0xd0000000,0x008bbbbb,0xbbbbc000,0x0009bbbb,0xbbbbd000,0x0cbbbbbb,0xbbb40000,
0x00000008,0x9bb60000,0x00000000,0x00000000,0x00000000,0x00000000,0x003fffff,
0xffffffff,0xffff3400,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x0bbbbbbb,0xbb600000,0x00006bbb,0xbbbbb900,0x00000000,
0x0dbbbbbb,0xbb900000,0x00000000,0x8c000000,0x00006bbb,0xbbbbbb00,0x00000000,
0x0008a400,0x00000000,0x00000000,0x00000008,0x6bbbbbbb,0xbbb5005b,0xbbbbbbbb,
0x90000000,0x00000000,0x00000008,0xbbbbbbbb,0xb8000000,0x000dbbbb,0xbbbb6000,
0x000dbbbb,0xbbbb9000,0x0abbbbbb,0xbbb00000,0x00000000,0x06000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00003fff,0xffffffff,0xfff40000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x0dbbbbbb,
0xbbd00000,0x00005bbb,0xbbbbbb80,0x00000000,0x06bbbbbb,0xbb900000,0x00000000,
0x00000000,0x0000abbb,0xbbbbbb00,0x00000000,0x00000000,0x00000000,0x00000000,
0x0005ad9b,0xbbbbbbbb,0xbbb5008b,0xbbbbbbbb,0x90000000,0x00000000,0x00000000,
0xdbbbbbbb,0xb9500000,0x000cbbbb,0xbbbb9000,0x000cbbbb,0xbbbbb400,0x0cbbbbbb,
0xbbb00000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x000004ff,0xffffffff,0xf4000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x06bbbbbb,0xbbb00000,0x00008bbb,0xbbbbbb50,
0x00000000,0x06bbbbbb,0xbbb00000,0x00000000,0x00000000,0x0000cbbb,0xbbbbbb00,
0x00000000,0x00000000,0x00000000,0x00000045,0xd9bbbbbb,0xbbbbbbbb,0xbbb5008b,
0xbbbbbbbb,0x90000000,0x00000000,0x00000000,0x0bbbbbbb,0xbbb95400,0x0004bbbb,
0xbbbbb000,0x0008bbbb,0xbbbbb800,0x0cbbbbbb,0xbbb00000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000004,0xfffffff4,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x0cbbbbbb,0xbbb80000,0x00000bbb,0xbbbbbb60,0x00000000,0x0cbbbbbb,0xbbbddddd,
0xdddddddd,0xdddddddd,0xd8005bbb,0xbbbbbbdd,0xdddddddd,0xdddddddd,0xdddd8000,
0x00008dbb,0xbbbbbbbb,0xbbbbbbbb,0xbbb4000b,0xbbbbbbbb,0x90000000,0x00000000,
0x00000000,0x05bbbbbb,0xbbbbbb96,0x5000bbbb,0xbbbbb800,0x0000bbbb,0xbbbbba00,
0x05bbbbbb,0xbbb9dddd,0xdddddddd,0xdddddddd,0xd8000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x43fff400,0x00000000,0x0007e140,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x08bbbbbb,0xbbb50000,0x000009bb,
0xbbbbbbd0,0x00000000,0x08bbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xb8004bbb,
0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbc000,0x0006bbbb,0xbbbbbbbb,0xbbbbbbbb,
0xbbd0000b,0xbbbbbbbb,0xb0000000,0x00000000,0x00000000,0x00cbbbbb,0xbbbbbbbb,
0xbb9c9bbb,0xbbbbbc00,0x00009bbb,0xbbbbbd00,0x00bbbbbb,0xbbbbbbbb,0xbbbbbbbb,
0xbbbbbbbb,0xbc000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00440000,
0x00000000,0x07eeeee2,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00bbbbbb,0xbbba0000,0x000006bb,0xbbbbbbb0,0x00000000,0x00bbbbbb,
0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xbc000bbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,
0xbbbb6000,0x00dbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xb980000d,0xbbbbbbbb,0xb0000000,
0x00000000,0x00000000,0x00089bbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbb600,0x0000dbbb,
0xbbbbb900,0x00bbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xb6000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000002,0xeeeeeeee,0x12000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x009bbbbb,0xbbbd0000,
0x00000cbb,0xbbbbbbb0,0x00000000,0x009bbbbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,
0xb6000dbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbb6000,0x0cbbbbbb,0xbbbbbbbb,
0xbbbbbbbb,0x94000006,0xbbbbbbbb,0xbc000000,0x00000000,0x00000000,0x00000cbb,
0xbbbbbbbb,0xbbbbbbbb,0xbbbbb900,0x0000cbbb,0xbbbbbb00,0x006bbbbb,0xbbbbbbbb,
0xbbbbbbbb,0xbbbbbbbb,0xb6000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x000002ee,0xeeeeeeee,0xee140000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x006bbbbb,0xbbb90000,0x000008bb,0xbbbbbbb5,0x00000000,
0x00abbbbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xb60005bb,0xbbbbbbbb,0xbbbbbbbb,
0xbbbbbbbb,0xbbbb9000,0x09bbbbbb,0xbbbbbbbb,0xbbbbbb9c,0x00000008,0xbbbbbbbb,
0xbd000000,0x00000000,0x00000000,0x00000005,0x9bbbbbbb,0xbbbbbbbb,0xbbbbbb00,
0x00005bbb,0xbbbbbb80,0x00cbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xb9000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x0002eeee,0xeeeeeeee,
0xeeee7000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00cbbbbb,
0xbbbb8000,0x000000bb,0xbbbbbbb6,0x00000000,0x008bbbbb,0xbbbbbbbb,0xbbbbbbbb,
0xbbbbbbbb,0xb60008bb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbd000,0x0bbbbbbb,
0xbbbbbbbb,0xbbb96800,0x00000000,0xbbbbbbbb,0xbb000000,0x00000000,0x00000000,
0x00000000,0x00cd9bbb,0xbbbbbbbb,0xbbbbbb80,0x00000bbb,0xbbbbbbc0,0x000bbbbb,
0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xbd000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x001eeeee,0xeeeeeeee,0xeeeeee40,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x008bbbbb,0xbbbb5000,0x0000009b,0xbbbbbbbb,
0x00000000,0x0009bbbb,0xbbbb5888,0x88888888,0xcbbbbbbb,0xbd0000db,0xbbbbbbbc,
0x88888888,0x8885bbbb,0xbbbb9000,0x0bbbbbbb,0xbbbbbb96,0xc8000000,0x00000000,
0x6bbbbbbb,0xbbc00000,0x00000000,0x00000000,0x00000000,0x0000045c,0x69bbbbbb,
0xbbbbbbc0,0x000009bb,0xbbbbbb60,0x000dbbbb,0xbbbbc888,0x88888888,0x5bbbbbbb,
0xb9000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x0047eeee,
0xeeeeeeee,0xeeeeeee1,0x40000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x000bbbbb,0xbbbba000,0x000000db,0xbbbbbbbb,0xd0000000,0x000cbbbb,0xbbbb6000,
0x00000000,0x8bbbbbbb,0xb600005b,0xbbbbbbbd,0x00000000,0x0008bbbb,0xbbbbd000,
0x0bbbbbbb,0xbbb9c000,0x00000000,0x00000000,0x8bbbbbbb,0xbb900000,0x0000000d,
0x50000000,0x00000000,0x00000000,0x00008dbb,0xbbbbbb60,0x00000dbb,0xbbbbbb90,
0x0005bbbb,0xbbbbd000,0x00000000,0x8bbbbbbb,0xbd000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x000041ee,0xeeeeeeee,0xeeeeeeee,0xe2000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x0009bbbb,0xbbbbd000,0x000000cb,
0xbbbbbbbb,0xb9500000,0x00009bbb,0xbbbbb800,0x00000000,0x5bbbbbbb,0xb6000009,
0xbbbbbbbb,0x50000000,0x0008bbbb,0xbbbbd000,0x0dbbbbbb,0xbb980000,0x00000000,
0x00000000,0x06bbbbbb,0xbbbd0000,0x0000004b,0xb9800000,0x00000000,0x00000000,
0x00000cbb,0xbbbbbbd0,0x00000abb,0xbbbbbbb0,0x00009bbb,0xbbbbb500,0x00000000,
0x8bbbbbbb,0xbd000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00043000,
0x0000002e,0xeeeeeeee,0xeeeeeeee,0xee120000,0x00000000,0x00000000,0x00000000,
0x00000000,0x000dbbbb,0xbbbb9000,0x0000008b,0xbbbbbbbb,0xbbb9da58,0x0000cbbb,
0xbbbbb980,0x00000000,0xdbbbbbbb,0xbc000005,0xbbbbbbbb,0xb0000000,0x0006bbbb,
0xbbbba000,0x0cbbbbbb,0xbbd00000,0x000000cb,0x50000000,0x08bbbbbb,0xbbbb5000,
0x0000006b,0xbbb60000,0x0006bbbb,0xbbbb6000,0x000008bb,0xbbbbbbb0,0x000005bb,
0xbbbbbbb8,0x00005bbb,0xbbbbb980,0x00000000,0x6bbbbbbb,0xba000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x043fff30,0x00000000,0x1eeeeeee,0xeeeeeeee,
0xeeee1400,0x00000000,0x00000000,0x00000000,0x00000000,0x000cbbbb,0xbbbbb000,
0x0000000b,0xbbbbbbbb,0xbbbbbbbb,0xb50009bb,0xbbbbbb98,0x00000005,0xbbbbbbbb,
0xb8000000,0xdbbbbbbb,0xbb800000,0x005bbbbb,0xbbbb5000,0x04bbbbbb,0xbbb00000,
0x000006bb,0xbd800000,0x00cbbbbb,0xbbbbb600,0x00000cbb,0xbbbbb500,0x0005bbbb,
0xbbbbb400,0x000000bb,0xbbbbbbb4,0x000004bb,0xbbbbbbbc,0x00000dbb,0xbbbbbb95,
0x00000008,0xbbbbbbbb,0xb5000000,0x00000000,0x00000000,0x00000000,0x00000004,
0x3fffffff,0x40000000,0x04eeeeee,0xeeeeeeee,0xeeeeee40,0x00000000,0x00000000,
0x00000000,0x00000008,0x888cbbbb,0xbbbbbc88,0x88800009,0xbbbbbbbb,0xbbbbbbbb,
0xba0008bb,0xbbbbbbbb,0x680008ab,0xbbbbbbbb,0x90000000,0x89bbbbbb,0xbbb68000,
0x0cbbbbbb,0xbbbb0000,0x006bbbbb,0xbbb95000,0x0056bbbb,0xbbb60000,0x0009bbbb,
0xbbbbbbb6,0x588c9bbb,0xbbbbbb90,0x0000bbbb,0xbbbbbd00,0x000005bb,0xbbbbbbb8,
0x0000009b,0xbbbbbbb6,0x000000bb,0xbbbbbbbb,0x680000cb,0xbbbbbbbb,0xb0000000,
0x00000000,0x00000000,0x00000000,0x0000043f,0xffffffff,0xf3000000,0x0002eeee,
0xeeeeeeee,0xeeee7000,0x00000000,0x00000000,0x00000000,0x0000000b,0xbbbbbbbb,
0xbbbbbbbb,0xbbb5000d,0xbbbbbbbb,0xbbbbbbbb,0xbd0000cb,0xbbbbbbbb,0xbb999bbb,
0xbbbbbbbb,0x60000000,0x05bbbbbb,0xbbbbbb99,0xbbbbbbbb,0xbbbd0000,0x008bbbbb,
0xbbbbbb99,0xbbbbbbbb,0xbbbb9c00,0x00009bbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbb90,
0x0000cbbb,0xbbbbbb98,0x000089bb,0xbbbbbbb8,0x0000009b,0xbbbbbbb9,0x0000005b,
0xbbbbbbbb,0xbbb99bbb,0xbbbbbbbb,0xd0000000,0x00000000,0x00000000,0x00000000,
0x00003fff,0xffffffff,0xfff30000,0x000001ee,0xeeeeeeee,0xee140000,0x00000000,
0x00000000,0x00000000,0x00000009,0xbbbbbbbb,0xbbbbbbbb,0xbbbc000a,0xbbbbbbbb,
0xbbbbbbbb,0xb9000006,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0x40000000,0x00abbbbb,
0xbbbbbbbb,0xbbbbbbbb,0xbbb80000,0x0005bbbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbd0,
0x00008bbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbb50,0x000009bb,0xbbbbbbbb,0x9d99bbbb,
0xbbbbbbb0,0x0000006b,0xbbbbbbbb,0x00000005,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,
0x80000000,0x00000000,0x00000000,0x00000000,0x003fffff,0xffffffff,0xfffff400,
0x00000041,0xeeeeeeee,0x14000000,0x00000000,0x00000000,0x00000000,0x00000006,
0xbbbbbbbb,0xbbbbbbbb,0xbbb60008,0xbbbbbbbb,0xbbbbbbbb,0xbb000000,0x6bbbbbbb,
0xbbbbbbbb,0xbbbbbbbc,0x00000000,0x000abbbb,0xbbbbbbbb,0xbbbbbbbb,0xbb600000,
0x00005bbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbb50,0x0000049b,0xbbbbbbbb,0xbbbbbbbb,
0xbbbbbd00,0x000008bb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbb90,0x0000005b,0xbbbbbbbb,
0x80000000,0x5bbbbbbb,0xbbbbbbbb,0xbbbbbbb6,0x00005050,0x50500000,0x00000000,
0x00000000,0x04ffffff,0xffffffff,0xffffff30,0x00000000,0x2eeeee14,0x00000000,
0x00004400,0x00000000,0x00000000,0x0000000c,0xbbbbbbbb,0xbbbbbbbb,0xbbb90000,
0xbbbbbbbb,0xbdbbbbbb,0xbb500000,0x05bbbbbb,0xbbbbbbbb,0xbbbbbb90,0x00000000,
0x00005bbb,0xbbbbbbbb,0xbbbbbbbb,0xb9000000,0x000005bb,0xbbbbbbbb,0xbbbbbbbb,
0xbbbb9000,0x0000000d,0xbbbbbbbb,0xbbbbbbbb,0xbbbb9000,0x0000005b,0xbbbbbbbb,
0xbbbbbbbb,0xbbbbbb50,0x0000008b,0xbbbbbbbb,0x50000000,0x05bbbbbb,0xbbbbbbbb,
0xbbbbbb90,0x0008c068,0x98d00000,0x00000000,0x00000000,0x0004ffff,0xffffffff,
0xffffffff,0x30000000,0x047e1400,0x00000000,0x0043ff34,0x00000000,0x00000000,
0x00000008,0xbbbbbbbb,0xbbbbbbbb,0xbbbb0000,0x9bbbbbbb,0xb60a9bbb,0xbbc00000,
0x008dbbbb,0xbbbbbbbb,0xbbbbbd00,0x00000000,0x000000db,0xbbbbbbbb,0xbbbbbbbb,
0xd8000000,0x0000008d,0xbbbbbbbb,0xbbbbbbbb,0xbb950000,0x00000000,0x59bbbbbb,
0xbbbbbbbb,0xbbbd0000,0x00000004,0xdbbbbbbb,0xbbbbbbbb,0xbbbbbc00,0x00000009,
0xbbbbbbbb,0x60000000,0x000dbbbb,0xbbbbbbbb,0xbbbbbd00,0x0008a06a,0xccd00000,
0x00000000,0x00000000,0x000003ff,0xffffffff,0xffffffff,0xff400000,0x00040000,
0x00000000,0x03ffffff,0x30000000,0x00000000,0x00000000,0xdddddbbb,0xbbbbbb9d,
0xdddd8000,0xdbbbbbbb,0xb90005db,0xbb600000,0x00005dbb,0xbbbbbbbb,0xbbb95000,
0x00000000,0x00000008,0xdbbbbbbb,0xbbbbbb9c,0x00000000,0x00000000,0x59bbbbbb,
0xbbbbbbbb,0x95000000,0x00000000,0x00c9bbbb,0xbbbbbbbb,0xb9500000,0x00000000,
0x059bbbbb,0xbbbbbbbb,0xbbb95000,0x00000009,0xbbbbbbbb,0xd0000000,0x00008dbb,
0xbbbbbbbb,0xbbb9a000,0x0008a0dd,0x06d00000,0x00000000,0x00000000,0x00000043,
0xffffffff,0xffffffff,0xfff34000,0x00000000,0x00000043,0xffffffff,0xff400000,
0x00000000,0x00000000,0x000009bb,0xbbbbbbd0,0x00000000,0x8c5555c5,0x55000000,
0x85500000,0x0000008c,0xd9bbbbbb,0x9d500000,0x00000000,0x00000000,0x00cd9bbb,
0xbbb9d500,0x00000000,0x00000000,0x004cd9bb,0xbbbb9dc0,0x00000000,0x00000000,
0x00005cdb,0xbbbbbb9a,0x50000000,0x00000000,0x0008cdbb,0xbbbbbbb9,0xda800000,
0x00000006,0xbbbbbbbb,0xb0000000,0x0000000c,0xd9bbbbbb,0x9dc00000,0x0086dc6c,
0x0cd00000,0x00000000,0x00000000,0x00000000,0x4fffffff,0xffffffff,0xfffff300,
0x00000000,0x000003ff,0xffffffff,0xffff0000,0x00000000,0x00000000,0x00000dbb,
0xbbbbbb90,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00008840,
0x00000000,0x00000000,0x00000000,0x00000008,0x84000000,0x00000000,0x00000000,
0x00000000,0x88400000,0x00000000,0x00000000,0x00000000,0x08880000,0x00000000,
0x00000000,0x00000000,0x08888000,0x00000000,0x0000000c,0xbbbbbbbb,0xb8000000,
0x00000000,0x00008880,0x00000000,0x00888480,0x00800000,0x00000000,0x00000000,
0x00000000,0x003fffff,0xffffffff,0xfffff400,0x00000000,0x0003ffff,0xffffffff,
0xfffff300,0x00000000,0x00000000,0x00000abb,0xbbbbbbb8,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000008,0xbbbbbbbb,0xb5000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00043fff,0xffffffff,
0xfff30000,0x00000000,0x003fffff,0xffffffff,0xfffffff4,0x00000000,0x00000000,
0x000005bb,0xbbbbbbbb,0x58040000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0xbbbbbbbb,
0xba000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x000004ff,0xffffffff,0xf3000000,0x00000000,0x00003fff,
0xffffffff,0xffffffff,0x30000000,0x00000000,0x000000bb,0xbbbbbbbb,0xbbbbb500,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0xdbbbbbbb,0xbd000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000003,
0xfffffff3,0x00000000,0x00000000,0x000004ff,0xffffffff,0xffffffff,0xff300000,
0x00000000,0x000000db,0xbbbbbbbb,0xbbbbba00,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x6bbbbbbb,0xb9000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x43fff340,0x00000000,0x00021100,
0x00000003,0xffffffff,0xffffffff,0xffff4000,0x00000000,0x0000008b,0xbbbbbbbb,
0xbbbbbd00,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0xcbbbbbbb,0xbb800000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00430000,0x00000000,0x021eeee2,0x00000000,0x03ffffff,0xffffffff,
0xfffff300,0x00000000,0x0000000d,0xbbbbbbbb,0xbbbbb900,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x8bbbbbbb,0xbb500000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000004,
0x1eeeeeee,0x14000000,0x004fffff,0xffffffff,0xffffff30,0x00000000,0x00000000,
0x9bbbbbbb,0xbbbbbb00,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x0bbbbbbb,0xbba00000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x0000041e,0xeeeeeeee,0xee100000,0x00003fff,
0xffffffff,0xffff3000,0x00000000,0x00000000,0x0dbbbbbb,0xbbbbbb50,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x09bbbbbb,0xbbd00000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00047eee,0xeeeeeeee,0xeeee2000,0x0000003f,0xffffffff,0xff300000,0x00000000,
0x00000000,0x0059bbbb,0xbbbbbbc0,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x06bbbbbb,
0xbb900000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x007eeeee,0xeeeeeeee,0xeeeee140,
0x00000004,0xffffffff,0x30000000,0x00000000,0x00000000,0x00004c66,0xd66a5800,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00808480,0x84800000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x0041eeee,0xeeeeeeee,0xeeeeeee7,0x00000000,0x03ffff34,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00002eee,0xeeeeeeee,
0xeeeeeeee,0xe2000000,0x004f3400,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x0000007e,0xeeeeeeee,0xeeeeeeee,0xee140000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000004,
0x1eeeeeee,0xeeeeeeee,0xeeee7000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x02eeeeee,0xeeeeeeee,0xeeeeee40,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x0007eeee,0xeeeeeeee,0xeeeee400,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x000041ee,0xeeeeeeee,
0xeee20000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x0000002e,0xeeeeeeee,0xe2000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x7eeeeee2,0x00000000,0x00000400,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x041ee700,0x00000000,0x0003ff30,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00040000,0x00000000,0x04ffffff,0x40000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000004,
0xffffffff,0xff400000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x000004ff,0xffffffff,0xfff30000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x0004ffff,0xffffffff,0xfffff400,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x004fffff,0xffffffff,0xfffffff4,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00043fff,0xffffffff,0xffffffff,0x30000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x000004ff,0xffffffff,
0xffffffff,0xff400000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00047700,0x00000003,0xffffffff,0xffffffff,0xffff4000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x001eeee4,0x00000000,
0x4fffffff,0xffffffff,0xfffff300,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x7eeeeeee,0x14000000,0x004fffff,0xffffffff,0xffffff30,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x0000007e,0xeeeeeeee,
0xee200000,0x00003fff,0xffffffff,0xffff3400,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00002eee,0xeeeeeeee,0xeeee4000,0x000004ff,0xffffffff,
0xfff40000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x002eeeee,
0xeeeeeeee,0xeeeee140,0x00000004,0xffffffff,0xf4000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x0041eeee,0xeeeeeeee,0xeeeeeee7,0x00000000,
0x43fffff4,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00002eee,0xeeeeeeee,0xeeeeeeee,0x12000000,0x004ff400,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00004000,0x0000007e,0xeeeeeeee,0xeeeeeeee,
0xee100000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x004fff40,0x00000004,0x1eeeeeee,0xeeeeeeee,0xeeee7000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x4ffffff3,0x00000000,0x02eeeeee,
0xeeeeeeee,0xeeeeee40,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000043,0xffffffff,0xf3000000,0x0001eeee,0xeeeeeeee,0xeeeee200,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x000043ff,0xffffffff,0xfff40000,
0x00004eee,0xeeeeeeee,0xeee70000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x0043ffff,0xffffffff,0xffff3400,0x0000002e,0xeeeeeeee,0xe7400000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00ffffff,0xffffffff,
0xffffff30,0x00000000,0x1eeeeee7,0x40000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x0003ffff,0xffffffff,0xffffffff,0x40000000,0x04eee140,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x000003ff,
0xffffffff,0xffffffff,0xf3000000,0x00024000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x0000004f,0xffffffff,0xffffffff,0xfff30000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x3fffffff,0xffffffff,0xfffff400,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00ffffff,0xffffffff,
0xfffff300,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x0004ffff,0xffffffff,0xffff3000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x000003ff,
0xffffffff,0xff400000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x0000004f,0xffffffff,0x30000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x4fffff30,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x003f3000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x0000babe
};

14
board/freescale/mpc8313erdb/mpc8313erdb.c
View File

@ -23,9 +23,7 @@
*/
#include <common.h>
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#elif defined(CONFIG_OF_LIBFDT)
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
#include <pci.h>
@ -103,16 +101,6 @@ void pci_init_board(void)
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
#if defined(CONFIG_OF_FLAT_TREE)
u32 *p;
int len;
p = ft_get_prop(blob, "/memory/reg", &len);
if (p != NULL) {
*p++ = cpu_to_be32(bd->bi_memstart);
*p = cpu_to_be32(bd->bi_memsize);
}
#endif
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);

10
board/freescale/mpc8323erdb/mpc8323erdb.c
View File

@ -184,16 +184,6 @@ void pci_init_board(void)
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
#if defined(CONFIG_OF_FLAT_TREE)
u32 *p;
int len;
p = ft_get_prop(blob, "/memory/reg", &len);
if (p != NULL) {
*p++ = cpu_to_be32(bd->bi_memstart);
*p = cpu_to_be32(bd->bi_memsize);
}
#endif
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);

14
board/freescale/mpc832xemds/mpc832xemds.c
View File

@ -27,9 +27,7 @@
#else
#include <asm/mmu.h>
#endif
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#elif defined(CONFIG_OF_LIBFDT)
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
#if defined(CONFIG_PQ_MDS_PIB)
@ -169,16 +167,6 @@ int checkboard(void)
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
#if defined(CONFIG_OF_FLAT_TREE)
u32 *p;
int len;
p = ft_get_prop(blob, "/memory/reg", &len);
if (p != NULL) {
*p++ = cpu_to_be32(bd->bi_memstart);
*p = cpu_to_be32(bd->bi_memsize);
}
#endif
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);

44
board/freescale/mpc832xemds/pci.c
View File

@ -18,10 +18,9 @@
#include <common.h>
#include <pci.h>
#include <i2c.h>
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#elif defined(CONFIG_OF_LIBFDT)
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#include <fdt_support.h>
#endif
#include <asm/fsl_i2c.h>
@ -262,37 +261,26 @@ void pci_init_board(void)
#endif /* CONFIG_PCISLAVE */
#if defined(CONFIG_OF_LIBFDT)
void
ft_pci_setup(void *blob, bd_t *bd)
void ft_pci_setup(void *blob, bd_t *bd)
{
int nodeoffset;
int err;
int tmp[2];
const char *path;
nodeoffset = fdt_path_offset(blob, "/" OF_SOC "/pci@8500");
nodeoffset = fdt_path_offset(blob, "/aliases");
if (nodeoffset >= 0) {
tmp[0] = cpu_to_be32(hose[0].first_busno);
tmp[1] = cpu_to_be32(hose[0].last_busno);
err = fdt_setprop(blob, nodeoffset, "bus-range",
tmp, sizeof(tmp));
path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
if (path) {
tmp[0] = cpu_to_be32(hose[0].first_busno);
tmp[1] = cpu_to_be32(hose[0].last_busno);
do_fixup_by_path(blob, path, "bus-range",
&tmp, sizeof(tmp), 1);
tmp[0] = cpu_to_be32(gd->pci_clk);
err = fdt_setprop(blob, nodeoffset, "clock-frequency",
tmp, sizeof(tmp[0]));
tmp[0] = cpu_to_be32(gd->pci_clk);
do_fixup_by_path(blob, path, "clock-frequency",
&tmp, sizeof(tmp[0]), 1);
}
}
}
#elif defined(CONFIG_OF_FLAT_TREE)
void
ft_pci_setup(void *blob, bd_t *bd)
{
u32 *p;
int len;
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
if (p != NULL) {
p[0] = hose[0].first_busno;
p[1] = hose[0].last_busno;
}
}
#endif /* CONFIG_OF_FLAT_TREE */
#endif /* CONFIG_OF_LIBFDT */
#endif /* CONFIG_PCI */

14
board/freescale/mpc8349emds/mpc8349emds.c
View File

@ -32,9 +32,7 @@
#if defined(CONFIG_SPD_EEPROM)
#include <spd_sdram.h>
#endif
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#elif defined(CONFIG_OF_LIBFDT)
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
@ -256,16 +254,6 @@ void sdram_init(void)
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
#if defined(CONFIG_OF_FLAT_TREE)
u32 *p;
int len;
p = ft_get_prop(blob, "/memory/reg", &len);
if (p != NULL) {
*p++ = cpu_to_be32(bd->bi_memstart);
*p = cpu_to_be32(bd->bi_memsize);
}
#endif
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);

72
board/freescale/mpc8349emds/pci.c
View File

@ -25,10 +25,9 @@
#include <pci.h>
#include <asm/mpc8349_pci.h>
#include <i2c.h>
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#elif defined(CONFIG_OF_LIBFDT)
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#include <fdt_support.h>
#endif
@ -389,58 +388,39 @@ pci_init_board(void)
}
#if defined(CONFIG_OF_LIBFDT)
void
ft_pci_setup(void *blob, bd_t *bd)
void ft_pci_setup(void *blob, bd_t *bd)
{
int nodeoffset;
int err;
int tmp[2];
const char *path;
nodeoffset = fdt_path_offset(blob, "/" OF_SOC "/pci@8500");
nodeoffset = fdt_path_offset(blob, "/aliases");
if (nodeoffset >= 0) {
tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
err = fdt_setprop(blob, nodeoffset, "bus-range",
tmp, sizeof(tmp));
path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
if (path) {
tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
do_fixup_by_path(blob, path, "bus-range",
&tmp, sizeof(tmp), 1);
tmp[0] = cpu_to_be32(gd->pci_clk);
err = fdt_setprop(blob, nodeoffset, "clock-frequency",
tmp, sizeof(tmp[0]));
}
tmp[0] = cpu_to_be32(gd->pci_clk);
do_fixup_by_path(blob, path, "clock-frequency",
&tmp, sizeof(tmp[0]), 1);
}
#ifdef CONFIG_MPC83XX_PCI2
nodeoffset = fdt_path_offset(blob, "/" OF_SOC "/pci@8600");
if (nodeoffset >= 0) {
tmp[0] = cpu_to_be32(pci_hose[1].first_busno);
tmp[1] = cpu_to_be32(pci_hose[1].last_busno);
err = fdt_setprop(blob, nodeoffset, "bus-range",
tmp, sizeof(tmp));
path = fdt_getprop(blob, nodeoffset, "pci1", NULL);
if (path) {
tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
do_fixup_by_path(blob, path, "bus-range",
&tmp, sizeof(tmp), 1);
tmp[0] = cpu_to_be32(gd->pci_clk);
err = fdt_setprop(blob, nodeoffset, "clock-frequency",
tmp, sizeof(tmp[0]));
}
tmp[0] = cpu_to_be32(gd->pci_clk);
do_fixup_by_path(blob, path, "clock-frequency",
&tmp, sizeof(tmp[0]), 1);
}
#endif
}
#elif defined(CONFIG_OF_FLAT_TREE)
void
ft_pci_setup(void *blob, bd_t *bd)
{
u32 *p;
int len;
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
if (p != NULL) {
p[0] = pci_hose[0].first_busno;
p[1] = pci_hose[0].last_busno;
}
#ifdef CONFIG_MPC83XX_PCI2
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len);
if (p != NULL) {
p[0] = pci_hose[1].first_busno;
p[1] = pci_hose[1].last_busno;
}
#endif
}
#endif /* CONFIG_OF_FLAT_TREE */
#endif /* CONFIG_OF_LIBFDT */
#endif /* CONFIG_PCI */

14
board/freescale/mpc8349itx/mpc8349itx.c
View File

@ -37,9 +37,7 @@
#else
#include <asm/mmu.h>
#endif
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#elif defined(CONFIG_OF_LIBFDT)
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
@ -389,16 +387,6 @@ int misc_init_r(void)
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
#if defined(CONFIG_OF_FLAT_TREE)
u32 *p;
int len;
p = ft_get_prop(blob, "/memory/reg", &len);
if (p != NULL) {
*p++ = cpu_to_be32(bd->bi_memstart);
*p = cpu_to_be32(bd->bi_memsize);
}
#endif
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);

72
board/freescale/mpc8349itx/pci.c
View File

@ -29,10 +29,9 @@
#include <pci.h>
#include <asm/mpc8349_pci.h>
#include <i2c.h>
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#elif defined(CONFIG_OF_LIBFDT)
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#include <fdt_support.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
@ -335,58 +334,39 @@ void pci_init_board(void)
}
#if defined(CONFIG_OF_LIBFDT)
void
ft_pci_setup(void *blob, bd_t *bd)
void ft_pci_setup(void *blob, bd_t *bd)
{
int nodeoffset;
int err;
int tmp[2];
const char *path;
nodeoffset = fdt_path_offset(blob, "/" OF_SOC "/pci@8500");
nodeoffset = fdt_path_offset(blob, "/aliases");
if (nodeoffset >= 0) {
tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
err = fdt_setprop(blob, nodeoffset, "bus-range",
tmp, sizeof(tmp));
path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
if (path) {
tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
do_fixup_by_path(blob, path, "bus-range",
&tmp, sizeof(tmp), 1);
tmp[0] = cpu_to_be32(gd->pci_clk);
err = fdt_setprop(blob, nodeoffset, "clock-frequency",
tmp, sizeof(tmp[0]));
}
tmp[0] = cpu_to_be32(gd->pci_clk);
do_fixup_by_path(blob, path, "clock-frequency",
&tmp, sizeof(tmp[0]), 1);
}
#ifdef CONFIG_MPC83XX_PCI2
nodeoffset = fdt_path_offset(blob, "/" OF_SOC "/pci@8500");
if (nodeoffset >= 0) {
tmp[0] = cpu_to_be32(pci_hose[1].first_busno);
tmp[1] = cpu_to_be32(pci_hose[1].last_busno);
err = fdt_setprop(blob, nodeoffset, "bus-range",
tmp, sizeof(tmp));
path = fdt_getprop(blob, nodeoffset, "pci1", NULL);
if (path) {
tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
do_fixup_by_path(blob, path, "bus-range",
&tmp, sizeof(tmp), 1);
tmp[0] = cpu_to_be32(gd->pci_clk);
err = fdt_setprop(blob, nodeoffset, "clock-frequency",
tmp, sizeof(tmp[0]));
}
tmp[0] = cpu_to_be32(gd->pci_clk);
do_fixup_by_path(blob, path, "clock-frequency",
&tmp, sizeof(tmp[0]), 1);
}
#endif
}
#elif defined(CONFIG_OF_FLAT_TREE)
void
ft_pci_setup(void *blob, bd_t *bd)
{
u32 *p;
int len;
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
if (p != NULL) {
p[0] = pci_hose[0].first_busno;
p[1] = pci_hose[0].last_busno;
}
#ifdef CONFIG_MPC83XX_PCI2
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len);
if (p != NULL) {
p[0] = pci_hose[1].first_busno;
p[1] = pci_hose[1].last_busno;
}
#endif
}
#endif /* CONFIG_OF_FLAT_TREE */
#endif /* CONFIG_OF_LIBFDT */
#endif /* CONFIG_PCI */

59
board/freescale/mpc8360emds/mpc8360emds.c
View File

@ -25,9 +25,7 @@
#else
#include <asm/mmu.h>
#endif
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#elif defined(CONFIG_OF_LIBFDT)
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
#if defined(CONFIG_PQ_MDS_PIB)
@ -87,6 +85,11 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
{0, 1, 3, 0, 2}, /* MDIO */
{0, 2, 1, 0, 1}, /* MDC */
{5, 0, 1, 0, 2}, /* UART2_SOUT */
{5, 1, 2, 0, 3}, /* UART2_CTS */
{5, 2, 1, 0, 1}, /* UART2_RTS */
{5, 3, 2, 0, 2}, /* UART2_SIN */
{0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
};
@ -106,6 +109,9 @@ int board_early_init_f(void)
immr->sysconf.spridr == SPR_8360E_REV21)
bcsr[0xe] = 0x30;
/* Enable second UART */
bcsr[0x9] &= ~0x01;
return 0;
}
@ -295,19 +301,48 @@ void sdram_init(void)
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
#if defined(CONFIG_OF_FLAT_TREE)
u32 *p;
int len;
const immap_t *immr = (immap_t *)CFG_IMMR;
p = ft_get_prop(blob, "/memory/reg", &len);
if (p != NULL) {
*p++ = cpu_to_be32(bd->bi_memstart);
*p = cpu_to_be32(bd->bi_memsize);
}
#endif
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
/*
* mpc8360ea pb mds errata 2: RGMII timing
* if on mpc8360ea rev. 2.1,
* change both ucc phy-connection-types from rgmii-id to rgmii-rxid
*/
if (immr->sysconf.spridr == SPR_8360_REV21 ||
immr->sysconf.spridr == SPR_8360E_REV21) {
int nodeoffset;
const char *prop;
const char *path;
nodeoffset = fdt_path_offset(fdt, "/aliases");
if (nodeoffset >= 0) {
#if defined(CONFIG_HAS_ETH0)
/* fixup UCC 1 if using rgmii-id mode */
path = fdt_getprop(blob, nodeoffset, "ethernet0", NULL);
if (path) {
prop = fdt_getprop(blob, nodeoffset,
"phy-connection-type", 0);
if (prop && (strcmp(prop, "rgmii-id") == 0))
fdt_setprop(blob, nodeoffset, "phy-connection-type",
"rgmii-rxid", sizeof("rgmii-rxid"));
}
#endif
#if defined(CONFIG_HAS_ETH1)
/* fixup UCC 2 if using rgmii-id mode */
path = fdt_getprop(blob, nodeoffset, "ethernet1", NULL);
if (path) {
prop = fdt_getprop(blob, nodeoffset,
"phy-connection-type", 0);
if (prop && (strcmp(prop, "rgmii-id") == 0))
fdt_setprop(blob, nodeoffset, "phy-connection-type",
"rgmii-rxid", sizeof("rgmii-rxid"));
}
#endif
}
}
}
#endif

44
board/freescale/mpc8360emds/pci.c
View File

@ -18,10 +18,9 @@
#include <common.h>
#include <pci.h>
#include <i2c.h>
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#elif defined(CONFIG_OF_LIBFDT)
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#include <fdt_support.h>
#endif
#include <asm/fsl_i2c.h>
@ -262,37 +261,26 @@ void pci_init_board(void)
#endif /* CONFIG_PCISLAVE */
#if defined(CONFIG_OF_LIBFDT)
void
ft_pci_setup(void *blob, bd_t *bd)
void ft_pci_setup(void *blob, bd_t *bd)
{
int nodeoffset;
int err;
int tmp[2];
const char *path;
nodeoffset = fdt_path_offset(blob, "/" OF_SOC "/pci@8500");
nodeoffset = fdt_path_offset(blob, "/aliases");
if (nodeoffset >= 0) {
tmp[0] = cpu_to_be32(hose[0].first_busno);
tmp[1] = cpu_to_be32(hose[0].last_busno);
err = fdt_setprop(blob, nodeoffset, "bus-range",
tmp, sizeof(tmp));
path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
if (path) {
tmp[0] = cpu_to_be32(hose[0].first_busno);
tmp[1] = cpu_to_be32(hose[0].last_busno);
do_fixup_by_path(blob, path, "bus-range",
&tmp, sizeof(tmp), 1);
tmp[0] = cpu_to_be32(gd->pci_clk);
err = fdt_setprop(blob, nodeoffset, "clock-frequency",
tmp, sizeof(tmp[0]));
tmp[0] = cpu_to_be32(gd->pci_clk);
do_fixup_by_path(blob, path, "clock-frequency",
&tmp, sizeof(tmp[0]), 1);
}
}
}
#elif defined(CONFIG_OF_FLAT_TREE)
void
ft_pci_setup(void *blob, bd_t *bd)
{
u32 *p;
int len;
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
if (p != NULL) {
p[0] = hose[0].first_busno;
p[1] = hose[0].last_busno;
}
}
#endif /* CONFIG_OF_FLAT_TREE */
#endif /* CONFIG_OF_LIBFDT */
#endif /* CONFIG_PCI */

50
board/freescale/mpc837xemds/Makefile Normal file
View File

@ -0,0 +1,50 @@
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := $(BOARD).o pci.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

28
board/freescale/mpc837xemds/config.mk Normal file
View File

@ -0,0 +1,28 @@
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# MPC837xEMDS
#
TEXT_BASE = 0xFE000000

132
board/freescale/mpc837xemds/mpc837xemds.c Normal file
View File

@ -0,0 +1,132 @@
/*
* Copyright (C) 2007 Freescale Semiconductor, Inc.
* Dave Liu <daveliu@freescale.com>
*
* CREDITS: Kim Phillips contribute to LIBFDT code
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
#include <common.h>
#include <i2c.h>
#include <spd.h>
#if defined(CONFIG_SPD_EEPROM)
#include <spd_sdram.h>
#endif
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
#if defined(CONFIG_PQ_MDS_PIB)
#include "../common/pq-mds-pib.h"
#endif
int board_early_init_f(void)
{
u8 *bcsr = (u8 *)CFG_BCSR;
/* Enable flash write */
bcsr[0x9] &= ~0x04;
/* Clear all of the interrupt of BCSR */
bcsr[0xe] = 0xff;
return 0;
}
int board_early_init_r(void)
{
#ifdef CONFIG_PQ_MDS_PIB
pib_init();
#endif
return 0;
}
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
int fixed_sdram(void);
long int initdram(int board_type)
{
volatile immap_t *im = (immap_t *) CFG_IMMR;
u32 msize = 0;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
return -1;
#if defined(CONFIG_SPD_EEPROM)
msize = spd_sdram();
#else
msize = fixed_sdram();
#endif
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
/* Initialize DDR ECC byte */
ddr_enable_ecc(msize * 1024 * 1024);
#endif
/* return total bus DDR size(bytes) */
return (msize * 1024 * 1024);
}
#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
* fixed sdram init -- doesn't use serial presence detect.
************************************************************************/
int fixed_sdram(void)
{
volatile immap_t *im = (immap_t *) CFG_IMMR;
u32 msize = CFG_DDR_SIZE * 1024 * 1024;
u32 msize_log2 = __ilog2(msize);
im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12;
im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
#if (CFG_DDR_SIZE != 512)
#warning Currenly any ddr size other than 512 is not supported
#endif
im->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
udelay(50000);
im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL;
udelay(1000);
im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
udelay(1000);
im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
im->ddr.sdram_mode = CFG_DDR_MODE;
im->ddr.sdram_mode2 = CFG_DDR_MODE2;
im->ddr.sdram_interval = CFG_DDR_INTERVAL;
__asm__ __volatile__("sync");
udelay(1000);
im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
udelay(2000);
return CFG_DDR_SIZE;
}
#endif /*!CFG_SPD_EEPROM */
int checkboard(void)
{
puts("Board: Freescale MPC837xEMDS\n");
return 0;
}
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
}
#endif /* CONFIG_OF_BOARD_SETUP */

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/*
* Copyright (C) 2007 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
#include <asm/mmu.h>
#include <asm/io.h>
#include <common.h>
#include <mpc83xx.h>
#include <pci.h>
#include <i2c.h>
#include <asm/fsl_i2c.h>
#if defined(CONFIG_PCI)
static struct pci_region pci_regions[] = {
{
bus_start: CFG_PCI_MEM_BASE,
phys_start: CFG_PCI_MEM_PHYS,
size: CFG_PCI_MEM_SIZE,
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
},
{
bus_start: CFG_PCI_MMIO_BASE,
phys_start: CFG_PCI_MMIO_PHYS,
size: CFG_PCI_MMIO_SIZE,
flags: PCI_REGION_MEM
},
{
bus_start: CFG_PCI_IO_BASE,
phys_start: CFG_PCI_IO_PHYS,
size: CFG_PCI_IO_SIZE,
flags: PCI_REGION_IO
}
};
void pci_init_board(void)
{
volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
struct pci_region *reg[] = { pci_regions };
/* Enable all 5 PCI_CLK_OUTPUTS */
clk->occr |= 0xf8000000;
udelay(2000);
/* Configure PCI Local Access Windows */
pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
udelay(2000);
mpc83xx_pci_init(1, reg, 0);
}
#endif /* CONFIG_PCI */

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# Copyright 2007 Freescale Semiconductor, Inc.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
ifneq ($(OBJTREE),$(SRCTREE))
$(shell mkdir -p $(obj)../common)
endif
LIB = $(obj)lib$(BOARD).a
COBJS := $(BOARD).o \
../common/sys_eeprom.o \
../common/pixis.o \
mpc8610hpcd_diu.o \
../common/fsl_diu_fb.o
SOBJS := init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(OBJS) $(SOBJS)
.PHONY: distclean
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

25
board/freescale/mpc8610hpcd/config.mk Normal file
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# Copyright 2007 Freescale Semiconductor.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
TEXT_BASE = 0xfff00000
PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1
PLATFORM_CPPFLAGS += -DCONFIG_MPC8610=1 -maltivec -mabi=altivec -msoft-float -O2

147
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/*
* Copyright 2007 Freescale Semiconductor.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*/
#include <config.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
#include <mpc86xx.h>
#define LAWAR_TRGT_PCI1 0x00000000
#define LAWAR_TRGT_PCIE1 0x00200000
#define LAWAR_TRGT_PCIE2 0x00100000
#define LAWAR_TRGT_LBC 0x00400000
#define LAWAR_TRGT_DDR 0x00f00000
#if !defined(CONFIG_SPD_EEPROM)
#define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M))
#else
#define LAWBAR1 0
#define LAWAR1 ((LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN)
#endif
#define LAWBAR2 ((CFG_PCIE1_MEM_BASE>>12) & 0xffffff)
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
#define LAWBAR3 ((CFG_PCIE2_MEM_BASE>>12) & 0xffffff)
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
#define LAWBAR4 ((PIXIS_BASE>>12) & 0xffffff)
#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_2M))
#define LAWBAR5 ((CFG_PCIE1_IO_PHYS>>12) & 0xffffff)
#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
#define LAWBAR6 ((CFG_PCIE2_IO_PHYS>>12) & 0xffffff)
#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_1M))
#define LAWBAR7 ((CFG_FLASH_BASE >>12) & 0xffffff)
#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
#define LAWBAR8 ((CFG_PCI1_MEM_PHYS>>12) & 0xffffff)
#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
#define LAWBAR9 ((CFG_PCI1_IO_PHYS>>12) & 0xffffff)
#define LAWAR9 (LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
.section .bootpg, "ax"
.globl law_entry
law_entry:
lis r7,CFG_CCSRBAR@h
ori r7,r7,CFG_CCSRBAR@l
addi r4,r7,0
addi r5,r7,0
/* Skip LAWAR0, start at LAWAR1 */
lis r6,LAWBAR1@h
ori r6,r6,LAWBAR1@l
stwu r6, 0xc28(r4)
lis r6,LAWAR1@h
ori r6,r6,LAWAR1@l
stwu r6, 0xc30(r5)
/* LAWBAR2, LAWAR2 */
lis r6,LAWBAR2@h
ori r6,r6,LAWBAR2@l
stwu r6, 0x20(r4)
lis r6,LAWAR2@h
ori r6,r6,LAWAR2@l
stwu r6, 0x20(r5)
/* LAWBAR3, LAWAR3 */
lis r6,LAWBAR3@h
ori r6,r6,LAWBAR3@l
stwu r6, 0x20(r4)
lis r6,LAWAR3@h
ori r6,r6,LAWAR3@l
stwu r6, 0x20(r5)
/* LAWBAR4, LAWAR4 */
lis r6,LAWBAR4@h
ori r6,r6,LAWBAR4@l
stwu r6, 0x20(r4)
lis r6,LAWAR4@h
ori r6,r6,LAWAR4@l
stwu r6, 0x20(r5)
/* LAWBAR5, LAWAR5 */
lis r6,LAWBAR5@h
ori r6,r6,LAWBAR5@l
stwu r6, 0x20(r4)
lis r6,LAWAR5@h
ori r6,r6,LAWAR5@l
stwu r6, 0x20(r5)
/* LAWBAR6, LAWAR6 */
lis r6,LAWBAR6@h
ori r6,r6,LAWBAR6@l
stwu r6, 0x20(r4)
lis r6,LAWAR6@h
ori r6,r6,LAWAR6@l
stwu r6, 0x20(r5)
/* LAWBAR7, LAWAR7 */
lis r6,LAWBAR7@h
ori r6,r6,LAWBAR7@l
stwu r6, 0x20(r4)
lis r6,LAWAR7@h
ori r6,r6,LAWAR7@l
stwu r6, 0x20(r5)
/* LAWBAR8, LAWAR8 */
lis r6,LAWBAR8@h
ori r6,r6,LAWBAR8@l
stwu r6, 0x20(r4)
lis r6,LAWAR8@h
ori r6,r6,LAWAR8@l
stwu r6, 0x20(r5)
/* LAWBAR9, LAWAR9 */
lis r6,LAWBAR9@h
ori r6,r6,LAWBAR9@l
stwu r6, 0x20(r4)
lis r6,LAWAR9@h
ori r6,r6,LAWAR9@l
stwu r6, 0x20(r5)
blr

546
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/*
* Copyright 2007 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#define DEBUG
#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_86xx.h>
#include <asm/immap_fsl_pci.h>
#include <spd.h>
#include <asm/io.h>
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
extern void ft_cpu_setup(void *blob, bd_t *bd);
#endif
#include "../common/pixis.h"
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
#if defined(CONFIG_SPD_EEPROM)
#include "spd_sdram.h"
#endif
void sdram_init(void);
long int fixed_sdram(void);
/* called before any console output */
int board_early_init_f(void)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */
return 0;
}
int misc_init_r(void)
{
u8 tmp_val, version;
/*Do not use 8259PIC*/
tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0);
out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x80);
/*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
version = in8(PIXIS_BASE + PIXIS_PVER);
if(version >= 0x07) {
tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0);
out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val & 0xbf);
}
/* Using this for DIU init before the driver in linux takes over
* Enable the TFP410 Encoder (I2C address 0x38)
*/
tmp_val = 0xBF;
i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
/* Verify if enabled */
tmp_val = 0;
i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
tmp_val = 0x10;
i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
/* Verify if enabled */
tmp_val = 0;
i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
#ifdef CONFIG_FSL_DIU_FB
mpc8610hpcd_diu_init();
#endif
return 0;
}
int checkboard(void)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
puts("Board: MPC8610HPCD\n");
mcm->abcr |= 0x00010000; /* 0 */
mcm->hpmr3 = 0x80000008; /* 4c */
mcm->hpmr0 = 0;
mcm->hpmr1 = 0;
mcm->hpmr2 = 0;
mcm->hpmr4 = 0;
mcm->hpmr5 = 0;
return 0;
}
long int
initdram(int board_type)
{
long dram_size = 0;
#if defined(CONFIG_SPD_EEPROM)
dram_size = spd_sdram();
#else
dram_size = fixed_sdram();
#endif
#if defined(CFG_RAMBOOT)
puts(" DDR: ");
return dram_size;
#endif
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/*
* Initialize and enable DDR ECC.
*/
ddr_enable_ecc(dram_size);
#endif
puts(" DDR: ");
return dram_size;
}
#if defined(CFG_DRAM_TEST)
int
testdram(void)
{
uint *pstart = (uint *) CFG_MEMTEST_START;
uint *pend = (uint *) CFG_MEMTEST_END;
uint *p;
puts("SDRAM test phase 1:\n");
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
puts("SDRAM test phase 2:\n");
for (p = pstart; p < pend; p++)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
puts("SDRAM test passed.\n");
return 0;
}
#endif
#if !defined(CONFIG_SPD_EEPROM)
/*
* Fixed sdram init -- doesn't use serial presence detect.
*/
long int fixed_sdram(void)
{
#if !defined(CFG_RAMBOOT)
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
uint d_init;
ddr->cs0_bnds = 0x0000001f;
ddr->cs0_config = 0x80010202;
ddr->ext_refrec = 0x00000000;
ddr->timing_cfg_0 = 0x00260802;
ddr->timing_cfg_1 = 0x3935d322;
ddr->timing_cfg_2 = 0x14904cc8;
ddr->sdram_mode_1 = 0x00480432;
ddr->sdram_mode_2 = 0x00000000;
ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
ddr->sdram_data_init = 0xDEADBEEF;
ddr->sdram_clk_cntl = 0x03800000;
ddr->sdram_cfg_2 = 0x04400010;
#if defined(CONFIG_DDR_ECC)
ddr->err_int_en = 0x0000000d;
ddr->err_disable = 0x00000000;
ddr->err_sbe = 0x00010000;
#endif
asm("sync;isync");
udelay(500);
ddr->sdram_cfg_1 = 0xc3000000; /* 0xe3008000;*/
#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
d_init = 1;
debug("DDR - 1st controller: memory initializing\n");
/*
* Poll until memory is initialized.
* 512 Meg at 400 might hit this 200 times or so.
*/
while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
udelay(1000);
debug("DDR: memory initialized\n\n");
asm("sync; isync");
udelay(500);
#endif
return 512 * 1024 * 1024;
#endif
return CFG_SDRAM_SIZE * 1024 * 1024;
}
#endif
#if defined(CONFIG_PCI)
/*
* Initialize PCI Devices, report devices found.
*/
#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_fsl86xxads_config_table[] = {
{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
PCI_IDSEL_NUMBER, PCI_ANY_ID,
pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
PCI_ENET0_MEMADDR,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} },
{}
};
#endif
static struct pci_controller pci1_hose = {
#ifndef CONFIG_PCI_PNP
config_table:pci_mpc86xxcts_config_table
#endif
};
#endif /* CONFIG_PCI */
#ifdef CONFIG_PCIE1
static struct pci_controller pcie1_hose;
#endif
#ifdef CONFIG_PCIE2
static struct pci_controller pcie2_hose;
#endif
int first_free_busno = 0;
void pci_init_board(void)
{
volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
volatile ccsr_gur_t *gur = &immap->im_gur;
uint devdisr = gur->devdisr;
uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
printf( " pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
devdisr, io_sel, host_agent);
#ifdef CONFIG_PCIE1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie1_hose;
int pcie_configured = (io_sel == 1) || (io_sel == 4);
int pcie_ep = (host_agent == 0) || (host_agent == 2) ||
(host_agent == 5);
if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) {
printf(" PCIe 1 connected to Uli as %s (base address %x)\n",
pcie_ep ? "End Point" : "Root Complex",
(uint)pci);
if (pci->pme_msg_det)
pci->pme_msg_det = 0xffffffff;
/* inbound */
pci_set_region(hose->regions + 0,
CFG_PCI_MEMORY_BUS,
CFG_PCI_MEMORY_PHYS,
CFG_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* outbound memory */
pci_set_region(hose->regions + 1,
CFG_PCIE1_MEM_BASE,
CFG_PCIE1_MEM_PHYS,
CFG_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(hose->regions + 2,
CFG_PCIE1_IO_BASE,
CFG_PCIE1_IO_PHYS,
CFG_PCIE1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 3;
hose->first_busno = first_free_busno;
pci_setup_indirect(hose, (int)&pci->cfg_addr,
(int)&pci->cfg_data);
fsl_pci_init(hose);
first_free_busno = hose->last_busno + 1;
printf(" PCI-Express 1 on bus %02x - %02x\n",
hose->first_busno, hose->last_busno);
} else
puts(" PCI-Express 1: Disabled\n");
}
#else
puts("PCI-Express 1: Disabled\n");
#endif /* CONFIG_PCIE1 */
#ifdef CONFIG_PCIE2
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR;
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie2_hose;
int pcie_configured = (io_sel == 0) || (io_sel == 4);
int pcie_ep = (host_agent == 0) || (host_agent == 1) ||
(host_agent == 4);
if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)) {
printf(" PCI-Express 2 connected to slot as %s" \
" (base address %x)\n",
pcie_ep ? "End Point" : "Root Complex",
(uint)pci);
if (pci->pme_msg_det)
pci->pme_msg_det = 0xffffffff;
/* inbound */
pci_set_region(hose->regions + 0,
CFG_PCI_MEMORY_BUS,
CFG_PCI_MEMORY_PHYS,
CFG_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* outbound memory */
pci_set_region(hose->regions + 1,
CFG_PCIE2_MEM_BASE,
CFG_PCIE2_MEM_PHYS,
CFG_PCIE2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(hose->regions + 2,
CFG_PCIE2_IO_BASE,
CFG_PCIE2_IO_PHYS,
CFG_PCIE2_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 3;
hose->first_busno = first_free_busno;
pci_setup_indirect(hose, (int)&pci->cfg_addr,
(int)&pci->cfg_data);
fsl_pci_init(hose);
first_free_busno = hose->last_busno + 1;
printf(" PCI-Express 2 on bus %02x - %02x\n",
hose->first_busno, hose->last_busno);
} else
puts(" PCI-Express 2: Disabled\n");
}
#else
puts("PCI-Express 2: Disabled\n");
#endif /* CONFIG_PCIE2 */
#ifdef CONFIG_PCI1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci1_hose;
int pci_agent = (host_agent >= 4) && (host_agent <= 6);
if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) {
printf(" PCI connected to PCI slots as %s" \
" (base address %x)\n",
pci_agent ? "Agent" : "Host",
(uint)pci);
/* inbound */
pci_set_region(hose->regions + 0,
CFG_PCI_MEMORY_BUS,
CFG_PCI_MEMORY_PHYS,
CFG_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* outbound memory */
pci_set_region(hose->regions + 1,
CFG_PCI1_MEM_BASE,
CFG_PCI1_MEM_PHYS,
CFG_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(hose->regions + 2,
CFG_PCI1_IO_BASE,
CFG_PCI1_IO_PHYS,
CFG_PCI1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 3;
hose->first_busno = first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr,
(int) &pci->cfg_data);
fsl_pci_init(hose);
first_free_busno = hose->last_busno + 1;
printf(" PCI on bus %02x - %02x\n",
hose->first_busno, hose->last_busno);
} else
puts(" PCI: Disabled\n");
}
#endif /* CONFIG_PCI1 */
}
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
void
ft_board_setup(void *blob, bd_t *bd)
{
u32 *p;
int len;
ft_cpu_setup(blob, bd);
p = ft_get_prop(blob, "/memory/reg", &len);
if (p != NULL) {
*p++ = cpu_to_be32(bd->bi_memstart);
*p = cpu_to_be32(bd->bi_memsize);
}
#ifdef CONFIG_PCI1
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
if (p != NULL) {
p[0] = 0;
p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
debug("pci@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
}
#endif
#ifdef CONFIG_PCIE1
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len);
if (p != NULL) {
p[0] = 0;
p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
debug("pcie@9000 first_busno=%d last_busno=%d\n",p[0],p[1]);
}
#endif
#ifdef CONFIG_PCIE2
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len);
if (p != NULL) {
p[0] = 0;
p[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
debug("pcie@9000 first_busno=%d last_busno=%d\n",p[0],p[1]);
}
#endif
}
#endif
/*
* get_board_sys_clk
* Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
*/
unsigned long
get_board_sys_clk(ulong dummy)
{
u8 i;
ulong val = 0;
ulong a;
a = PIXIS_BASE + PIXIS_SPD;
i = in8(a);
i &= 0x07;
switch (i) {
case 0:
val = 33333000;
break;
case 1:
val = 39999600;
break;
case 2:
val = 49999500;
break;
case 3:
val = 66666000;
break;
case 4:
val = 83332500;
break;
case 5:
val = 99999000;
break;
case 6:
val = 133332000;
break;
case 7:
val = 166665000;
break;
}
return val;
}

177
board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c Normal file
View File

@ -0,0 +1,177 @@
/*
* Copyright 2007 Freescale Semiconductor, Inc.
* York Sun <yorksun@freescale.com>
*
* FSL DIU Framebuffer driver
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <asm/io.h>
#ifdef CONFIG_FSL_DIU_FB
#include "../common/pixis.h"
#include "../common/fsl_diu_fb.h"
#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
#include <devices.h>
#include <video_fb.h>
#endif
extern unsigned int FSL_Logo_BMP[];
static int xres, yres;
void mpc8610hpcd_diu_init(void)
{
char *monitor_port;
int gamma_fix;
unsigned int pixel_format;
unsigned char tmp_val;
unsigned char pixis_arch;
tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0);
pixis_arch = in8(PIXIS_BASE + PIXIS_VER);
monitor_port = getenv("monitor");
if (!strncmp(monitor_port, "0", 1)) { /* 0 - DVI */
xres = 1280;
yres = 1024;
if (pixis_arch == 0x01)
pixel_format = 0x88882317;
else
pixel_format = 0x88883316;
gamma_fix = 0;
out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x08);
} else if (!strncmp(monitor_port, "1", 1)) { /* 1 - Single link LVDS */
xres = 1024;
yres = 768;
pixel_format = 0x88883316;
gamma_fix = 0;
out8(PIXIS_BASE + PIXIS_BRDCFG0, (tmp_val & 0xf7) | 0x10);
} else if (!strncmp(monitor_port, "2", 1)) { /* 2 - Double link LVDS */
xres = 1280;
yres = 1024;
pixel_format = 0x88883316;
gamma_fix = 1;
out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val & 0xe7);
} else { /* DVI */
xres = 1280;
yres = 1024;
pixel_format = 0x88882317;
gamma_fix = 0;
out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x08);
}
fsl_diu_init(xres, pixel_format, gamma_fix,
(unsigned char *)FSL_Logo_BMP);
}
int mpc8610diu_init_show_bmp(cmd_tbl_t *cmdtp,
int flag, int argc, char *argv[])
{
unsigned int addr;
if (argc < 2) {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
if (!strncmp(argv[1],"init",4)) {
#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
fsl_diu_clear_screen();
drv_video_init();
#else
mpc8610hpcd_diu_init();
#endif
} else {
addr = simple_strtoul(argv[1], NULL, 16);
fsl_diu_clear_screen();
fsl_diu_display_bmp((unsigned char *)addr, 0, 0, 0);
}
return 0;
}
U_BOOT_CMD(
diufb, CFG_MAXARGS, 1, mpc8610diu_init_show_bmp,
"diufb init | addr - Init or Display BMP file\n",
"init\n - initialize DIU\n"
"addr\n - display bmp at address 'addr'\n"
);
#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
/*
* The Graphic Device
*/
GraphicDevice ctfb;
void *video_hw_init(void)
{
GraphicDevice *pGD = (GraphicDevice *) &ctfb;
struct fb_info *info;
mpc8610hpcd_diu_init();
/* fill in Graphic device struct */
sprintf(pGD->modeIdent,
"%dx%dx%d %ldkHz %ldHz",
xres, yres, 32, 64, 60);
pGD->frameAdrs = (unsigned int)fsl_fb_open(&info);
pGD->winSizeX = xres;
pGD->winSizeY = yres - info->logo_height;
pGD->plnSizeX = pGD->winSizeX;
pGD->plnSizeY = pGD->winSizeY;
pGD->gdfBytesPP = 4;
pGD->gdfIndex = GDF_32BIT_X888RGB;
pGD->isaBase = 0;
pGD->pciBase = 0;
pGD->memSize = info->screen_size - info->logo_size;
/* Cursor Start Address */
pGD->dprBase = 0;
pGD->vprBase = 0;
pGD->cprBase = 0;
return (void *)pGD;
}
void video_set_lut (unsigned int index, /* color number */
unsigned char r, /* red */
unsigned char g, /* green */
unsigned char b /* blue */
)
{
return;
}
#endif /* defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) */
#endif /* CONFIG_FSL_DIU_FB */

135
board/freescale/mpc8610hpcd/u-boot.lds Normal file
View File

@ -0,0 +1,135 @@
/*
* Copyright 2007 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SECTIONS
{
/* Read-only sections, merged into text segment: */
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/mpc86xx/start.o (.text)
board/freescale/mpc8610hpcd/init.o (.bootpg)
cpu/mpc86xx/traps.o (.text)
cpu/mpc86xx/interrupts.o (.text)
cpu/mpc86xx/cpu_init.o (.text)
cpu/mpc86xx/cpu.o (.text)
cpu/mpc86xx/speed.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
lib_generic/zlib.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

60
board/freescale/mpc8641hpcn/mpc8641hpcn.c
View File

@ -27,11 +27,8 @@
#include <asm/immap_fsl_pci.h>
#include <spd.h>
#include <asm/io.h>
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
extern void ft_cpu_setup(void *blob, bd_t *bd);
#endif
#include <libfdt.h>
#include <fdt_support.h>
#include "../common/pixis.h"
@ -324,36 +321,47 @@ void pci_init_board(void)
}
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
#if defined(CONFIG_OF_BOARD_SETUP)
void
ft_board_setup(void *blob, bd_t *bd)
{
u32 *p;
int len;
int node, tmp[2];
const char *path;
ft_cpu_setup(blob, bd);
fdt_fixup_ethernet(blob, bd);
p = ft_get_prop(blob, "/memory/reg", &len);
if (p != NULL) {
*p++ = cpu_to_be32(bd->bi_memstart);
*p = cpu_to_be32(bd->bi_memsize);
}
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"timebase-frequency", bd->bi_busfreq / 4, 1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"bus-frequency", bd->bi_busfreq, 1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"clock-frequency", bd->bi_intfreq, 1);
do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
"bus-frequency", bd->bi_busfreq, 1);
do_fixup_by_compat_u32(blob, "ns16550",
"clock-frequency", bd->bi_busfreq, 1);
fdt_fixup_memory(blob, bd->bi_memstart, bd->bi_memsize);
node = fdt_path_offset(blob, "/aliases");
tmp[0] = 0;
if (node >= 0) {
#ifdef CONFIG_PCI1
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@8000/bus-range", &len);
if (p != NULL) {
p[0] = 0;
p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
}
path = fdt_getprop(blob, node, "pci0", NULL);
if (path) {
tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
}
#endif
#ifdef CONFIG_PCI2
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len);
if (p != NULL) {
p[0] = 0;
p[1] = pci2_hose.last_busno - pci2_hose.first_busno;
debug("PCI@9000 first_busno=%d last_busno=%d\n",p[0],p[1]);
}
path = fdt_getprop(blob, node, "pci1", NULL);
if (path) {
tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno;
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
}
#endif
}
}
#endif

2
board/gen860t/fpga.c
View File

@ -34,7 +34,7 @@
DECLARE_GLOBAL_DATA_PTR;
#if (CONFIG_FPGA)
#if defined(CONFIG_FPGA)
#if 0
#define GEN860T_FPGA_DEBUG

2
board/gen860t/gen860t.c
View File

@ -254,7 +254,7 @@ int misc_init_r (void)
mii_init ();
#endif
#if (CONFIG_FPGA)
#if defined(CONFIG_FPGA)
gen860t_init_fpga ();
#endif
return 0;

2
board/inka4x0/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := $(BOARD).o flash.o
COBJS := $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

432
board/inka4x0/flash.c
View File

@ -1,432 +0,0 @@
/*
* (C) Copyright 2003-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2004
* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*
* CPU to flash interface is 8-bit, so make declaration accordingly
*/
typedef unsigned char FLASH_PORT_WIDTH;
typedef volatile unsigned char FLASH_PORT_WIDTHV;
#define FPW FLASH_PORT_WIDTH
#define FPWV FLASH_PORT_WIDTHV
#define FLASH_CYCLE1 0x0555
#define FLASH_CYCLE2 0x02aa
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size(FPWV *addr, flash_info_t *info);
static void flash_reset(flash_info_t *info);
static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
static flash_info_t *flash_get_info(ulong base);
/*-----------------------------------------------------------------------
* flash_init()
*
* sets up flash_info and returns size of FLASH (bytes)
*/
unsigned long flash_init (void)
{
unsigned long size = 0;
extern void flash_preinit(void);
ulong flashbase = CFG_FLASH_BASE;
flash_preinit();
/* Init: no FLASHes known */
memset(&flash_info[0], 0, sizeof(flash_info_t));
flash_info[0].size =
flash_get_size((FPW *)flashbase, &flash_info[0]);
size = flash_info[0].size;
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE+monitor_flash_len-1,
flash_get_info(CFG_MONITOR_BASE));
#endif
#ifdef CFG_ENV_IS_IN_FLASH
/* ENV protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR+CFG_ENV_SIZE-1,
flash_get_info(CFG_ENV_ADDR));
#endif
return size ? size : 1;
}
/*-----------------------------------------------------------------------
*/
static void flash_reset(flash_info_t *info)
{
FPWV *base = (FPWV *)(info->start[0]);
/* Put FLASH back in read mode */
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
*base = (FPW)0x00FF00FF; /* Intel Read Mode */
else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
*base = (FPW)0x00F000F0; /* AMD Read Mode */
}
/*-----------------------------------------------------------------------
*/
static flash_info_t *flash_get_info(ulong base)
{
int i;
flash_info_t * info;
for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
info = & flash_info[i];
if (info->size && info->start[0] <= base &&
base <= info->start[0] + info->size - 1)
break;
}
return i == CFG_MAX_FLASH_BANKS ? 0 : info;
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t *info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD: printf ("AMD "); break;
case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
case FLASH_MAN_SST: printf ("SST "); break;
case FLASH_MAN_STM: printf ("STM "); break;
case FLASH_MAN_INTEL: printf ("INTEL "); break;
default: printf ("Unknown Vendor "); break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AM116DB:
printf ("AM29LV116DB (16Mbit, bottom boot sect)\n");
break;
case FLASH_AMLV128U:
printf ("AM29LV128ML (128Mbit, uniform sector size)\n");
break;
case FLASH_AM160B:
printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
break;
default:
printf ("Unknown Chip Type\n");
break;
}
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20,
info->sector_count);
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i) {
if ((i % 5) == 0) {
printf ("\n ");
}
printf (" %08lX%s",
info->start[i],
info->protect[i] ? " (RO)" : " ");
}
printf ("\n");
return;
}
/*-----------------------------------------------------------------------
*/
/*
* The following code cannot be run from FLASH!
*/
ulong flash_get_size (FPWV *addr, flash_info_t *info)
{
int i;
ulong base = (ulong)addr;
/* Write auto select command: read Manufacturer ID */
/* Write auto select command sequence and test FLASH answer */
addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */
addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */
addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */
/* The manufacturer codes are only 1 byte, so just use 1 byte.
* This works for any bus width and any FLASH device width.
*/
udelay(100);
switch (addr[0] & 0xff) {
case (uchar)AMD_MANUFACT:
debug ("Manufacturer: AMD (Spansion)\n");
info->flash_id = FLASH_MAN_AMD;
break;
case (uchar)INTEL_MANUFACT:
debug ("Manufacturer: Intel (not supported yet)\n");
info->flash_id = FLASH_MAN_INTEL;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
break;
}
/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) {
case (uchar)AMD_ID_LV116DB:
debug ("Chip: AM29LV116DB\n");
info->flash_id += FLASH_AM116DB;
info->sector_count = 35;
info->size = 0x00200000;
/*
* The first 4 sectors are 16 kB, 8 kB, 8 kB and 32 kB, all
* the other ones are 64 kB
*/
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00004000;
info->start[2] = base + 0x00006000;
info->start[3] = base + 0x00008000;
for( i = 4; i < info->sector_count; i++ )
info->start[i] =
base + (i * (64 << 10)) - 0x00030000;
break; /* => 2 MB */
case (FPW)AMD_ID_LV160B:
debug ("Chip: AM29LV160MB\n");
info->flash_id += FLASH_AM160B;
info->sector_count = 35;
info->size = 0x00400000;
/*
* The first 4 sectors are 16 kB, 8 kB, 8 kB and 32 kB, all
* the other ones are 64 kB
*/
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00008000;
info->start[2] = base + 0x0000C000;
info->start[3] = base + 0x00010000;
for( i = 4; i < info->sector_count; i++ )
info->start[i] =
base + (i * 2 * (64 << 10)) - 0x00060000;
break; /* => 4 MB */
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
}
/* Put FLASH back in read mode */
flash_reset(info);
return (info->size);
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
FPWV *addr = (FPWV*)(info->start[0]);
int flag, prot, sect, l_sect;
ulong start, now, last;
debug ("flash_erase: first: %d last: %d\n", s_first, s_last);
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
if ((info->flash_id == FLASH_UNKNOWN) ||
(info->flash_id > FLASH_AMD_COMP)) {
printf ("Can't erase unknown flash type %08lx - aborted\n",
info->flash_id);
return 1;
}
prot = 0;
for (sect=s_first; sect<=s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("\n");
}
l_sect = -1;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr[0x0555] = (FPW)0x00AA00AA;
addr[0x02AA] = (FPW)0x00550055;
addr[0x0555] = (FPW)0x00800080;
addr[0x0555] = (FPW)0x00AA00AA;
addr[0x02AA] = (FPW)0x00550055;
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr = (FPWV*)(info->start[sect]);
addr[0] = (FPW)0x00300030;
l_sect = sect;
}
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
/*
* We wait for the last triggered sector
*/
if (l_sect < 0)
goto DONE;
start = get_timer (0);
last = start;
addr = (FPWV*)(info->start[l_sect]);
while ((addr[0] & (FPW)0x00800080) != (FPW)0x00800080) {
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return 1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
}
DONE:
/* reset to read mode */
addr = (FPWV*)info->start[0];
addr[0] = (FPW)0x00F000F0; /* reset bank */
printf (" done\n");
return 0;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
int i, rc = 0;
for (i = 0; i < cnt; i++)
if ((rc = write_word_amd(info, (FPW *)(addr+i), src[i])) != 0) {
return (rc);
}
return rc;
}
/*-----------------------------------------------------------------------
* Write a word to Flash for AMD FLASH
* A word is 16 or 32 bits, whichever the bus width of the flash bank
* (not an individual chip) is.
*
* returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
{
ulong start;
int flag;
FPWV *base; /* first address in flash bank */
/* Check if Flash is (sufficiently) erased */
if ((*dest & data) != data) {
return (2);
}
base = (FPWV *)(info->start[0]);
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */
*dest = data; /* start programming the data */
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
start = get_timer (0);
/* data polling for D7 */
while ((*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
*dest = (FPW)0x00F000F0; /* reset bank */
return (1);
}
}
return (0);
}

32
board/inka4x0/hyb25d512160bf-5.h Normal file
View File

@ -0,0 +1,32 @@
/*
* Copyright (C) 2007 Semihalf
* Written by Marian Balakowicz <m8@semihalf.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#define SDRAM_DDR 1 /* is DDR */
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x018D0000
#define SDRAM_EMODE 0x40090000
#define SDRAM_CONTROL 0x714F0F00
#define SDRAM_CONFIG1 0x73711930
#define SDRAM_CONFIG2 0x46770000
#define SDRAM_TAPDELAY 0x10000000

20
board/inka4x0/inka4x0.c
View File

@ -31,10 +31,18 @@
#include <mpc5xxx.h>
#include <pci.h>
#if defined(CONFIG_MPC5200_DDR)
#if defined(CONFIG_DDR_MT46V16M16)
#include "mt46v16m16-75.h"
#else
#elif defined(CONFIG_SDR_MT48LC16M16A2)
#include "mt48lc16m16a2-75.h"
#elif defined(CONFIG_DDR_MT46V32M16)
#include "mt46v32m16.h"
#elif defined(CONFIG_DDR_HYB25D512160BF)
#include "hyb25d512160bf.h"
#elif defined(CONFIG_DDR_K4H511638C)
#include "k4h511638c.h"
#else
#error "INKA4x0 SDRAM: invalid chip type specified!"
#endif
#ifndef CFG_RAMBOOT
@ -88,7 +96,7 @@ long int initdram (int board_type)
{
ulong dramsize = 0;
#ifndef CFG_RAMBOOT
ulong test1, test2;
long test1, test2;
/* setup SDRAM chip selects */
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
@ -108,9 +116,9 @@ long int initdram (int board_type)
/* find RAM size using SDRAM CS0 only */
sdram_start(0);
test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
sdram_start(1);
test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
if (test1 > test2) {
sdram_start(0);
dramsize = test1;
@ -175,7 +183,7 @@ void flash_preinit(void)
int misc_init_f (void)
{
uchar tmp[10];
char tmp[10];
int i, br;
i = getenv_r("brightness", tmp, sizeof(tmp));

32
board/inka4x0/k4h511638c.h Normal file
View File

@ -0,0 +1,32 @@
/*
* Copyright (C) 2007 Semihalf
* Written by Marian Balakowicz <m8@semihalf.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#define SDRAM_DDR 1 /* is DDR */
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x018D0000
#define SDRAM_EMODE 0x40090000
#define SDRAM_CONTROL 0x714F0F00
#define SDRAM_CONFIG1 0x73722930
#define SDRAM_CONFIG2 0x46770000
#define SDRAM_TAPDELAY 0x10000000

7
board/inka4x0/mt46v16m16-75.h
View File

@ -23,15 +23,10 @@
#define SDRAM_DDR 1 /* is DDR */
#if defined(CONFIG_MPC5200)
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x018D0000
#define SDRAM_EMODE 0x40090000
#define SDRAM_CONTROL 0x714f0f00
#define SDRAM_CONTROL 0x714F0F00
#define SDRAM_CONFIG1 0x73722930
#define SDRAM_CONFIG2 0x47770000
#define SDRAM_TAPDELAY 0x10000000
#else
#error CONFIG_MPC5200 not defined
#endif

32
board/inka4x0/mt46v32m16-75.h Normal file
View File

@ -0,0 +1,32 @@
/*
* Copyright (C) 2007 Semihalf
* Written by Marian Balakowicz <m8@semihalf.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#define SDRAM_DDR 1 /* is DDR */
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x018D0000
#define SDRAM_EMODE 0x40090000
#define SDRAM_CONTROL 0x714F0F00
#define SDRAM_CONFIG1 0x73711930
#define SDRAM_CONFIG2 0x46770000
#define SDRAM_TAPDELAY 0x10000000

19
board/inka4x0/mt48lc16m16a2-75.h
View File

@ -21,27 +21,10 @@
* MA 02111-1307 USA
*/
#define SDRAM_DDR 1 /* is SDR */
#define SDRAM_DDR 0 /* is SDR */
#if defined(CONFIG_MPC5200)
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x00CD0000
/* #define SDRAM_MODE 0x008D0000 */ /* CAS latency 2 */
#define SDRAM_CONTROL 0x504F0000
#define SDRAM_CONFIG1 0xD2322800
/* #define SDRAM_CONFIG1 0xD2222800 */ /* CAS latency 2 */
/*#define SDRAM_CONFIG1 0xD7322800 */ /* SDRAM controller bug workaround */
#define SDRAM_CONFIG2 0x8AD70000
/*#define SDRAM_CONFIG2 0xDDD70000 */ /* SDRAM controller bug workaround */
#elif defined(CONFIG_MGT5100)
/* Settings for XLB = 66 MHz */
#define SDRAM_MODE 0x008D0000
#define SDRAM_CONTROL 0x504F0000
#define SDRAM_CONFIG1 0xC2222600
#define SDRAM_CONFIG2 0x88B70004
#define SDRAM_ADDRSEL 0x02000000
#else
#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
#endif

117
board/korat/korat.c
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2007
* (C) Copyright 2007-2008
* Larry Johnson, lrj@acm.org
*
* (C) Copyright 2006
@ -26,6 +26,7 @@
*/
#include <common.h>
#include <asm/gpio.h>
#include <asm/processor.h>
#include <asm-ppc/io.h>
#include <i2c.h>
@ -40,109 +41,12 @@ ulong flash_get_size(ulong base, int banknum);
int board_early_init_f(void)
{
u32 sdr0_pfc1, sdr0_pfc2;
u32 gpio0_ir;
u32 reg;
int eth;
mtdcr(ebccfga, xbcfg);
mtdcr(ebccfgd, 0xb8400000);
/*--------------------------------------------------------------------
* Setup the GPIO pins
*
* Korat GPIO usage:
*
* Init.
* Pin Source I/O value Function
* ------ ------ --- ----- ---------------------------------
* GPIO00 Alt1 I/O x PerAddr07
* GPIO01 Alt1 I/O x PerAddr06
* GPIO02 Alt1 I/O x PerAddr05
* GPIO03 GPIO x x GPIO03 to expansion bus connector
* GPIO04 GPIO x x GPIO04 to expansion bus connector
* GPIO05 GPIO x x GPIO05 to expansion bus connector
* GPIO06 Alt1 O x PerCS1 (2nd NOR flash)
* GPIO07 Alt1 O x PerCS2 (CPLD)
* GPIO08 Alt1 O x PerCS3 to expansion bus connector
* GPIO09 Alt1 O x PerCS4 to expansion bus connector
* GPIO10 Alt1 O x PerCS5 to expansion bus connector
* GPIO11 Alt1 I x PerErr
* GPIO12 GPIO O 0 ATMega !Reset
* GPIO13 GPIO O 1 SPI Atmega !SS
* GPIO14 GPIO O 1 Write protect EEPROM #1 (0xA8)
* GPIO15 GPIO O 0 CPU Run LED !On
* GPIO16 Alt1 O x GMC1TxD0
* GPIO17 Alt1 O x GMC1TxD1
* GPIO18 Alt1 O x GMC1TxD2
* GPIO19 Alt1 O x GMC1TxD3
* GPIO20 Alt1 O x RejectPkt0
* GPIO21 Alt1 O x RejectPkt1
* GPIO22 GPIO I x PGOOD_DDR
* GPIO23 Alt1 O x SCPD0
* GPIO24 Alt1 O x GMC0TxD2
* GPIO25 Alt1 O x GMC0TxD3
* GPIO26 GPIO? I/O x IIC0SDA (selected in SDR0_PFC4)
* GPIO27 GPIO O 0 PHY #0 1000BASE-X
* GPIO28 GPIO O 0 PHY #1 1000BASE-X
* GPIO29 GPIO I x Test jumper !Present
* GPIO30 GPIO I x SFP module #0 !Present
* GPIO31 GPIO I x SFP module #1 !Present
*
* GPIO32 GPIO O 1 SFP module #0 Tx !Enable
* GPIO33 GPIO O 1 SFP module #1 Tx !Enable
* GPIO34 Alt2 I x !UART1_CTS
* GPIO35 Alt2 O x !UART1_RTS
* GPIO36 Alt1 I x !UART0_CTS
* GPIO37 Alt1 O x !UART0_RTS
* GPIO38 Alt2 O x UART1_Tx
* GPIO39 Alt2 I x UART1_Rx
* GPIO40 Alt1 I x IRQ0 (Ethernet 0)
* GPIO41 Alt1 I x IRQ1 (Ethernet 1)
* GPIO42 Alt1 I x IRQ2 (PCI interrupt)
* GPIO43 Alt1 I x IRQ3 (System Alert from CPLD)
* GPIO44 xxxx x x (grounded through pulldown)
* GPIO45 GPIO O 0 PHY #0 Enable
* GPIO46 GPIO O 0 PHY #1 Enable
* GPIO47 GPIO I x Reset switch !Pressed
* GPIO48 GPIO I x Shutdown switch !Pressed
* GPIO49 xxxx x x (reserved for trace port)
* . . . . .
* . . . . .
* . . . . .
* GPIO63 xxxx x x (reserved for trace port)
*-------------------------------------------------------------------*/
out_be32((u32 *) GPIO0_OR, 0x00060000);
out_be32((u32 *) GPIO1_OR, 0xC0000000);
out_be32((u32 *) GPIO0_OSRL, 0x54055400);
out_be32((u32 *) GPIO0_OSRH, 0x55015000);
out_be32((u32 *) GPIO1_OSRL, 0x02180000);
out_be32((u32 *) GPIO1_OSRH, 0x00000000);
out_be32((u32 *) GPIO0_TSRL, 0x54055500);
out_be32((u32 *) GPIO0_TSRH, 0x00015000);
out_be32((u32 *) GPIO1_TSRL, 0x00000000);
out_be32((u32 *) GPIO1_TSRH, 0x00000000);
out_be32((u32 *) GPIO0_TCR, 0x000FF0D8);
out_be32((u32 *) GPIO1_TCR, 0xD6060000);
out_be32((u32 *) GPIO0_ISR1L, 0x54000100);
out_be32((u32 *) GPIO0_ISR1H, 0x00500000);
out_be32((u32 *) GPIO1_ISR1L, 0x00405500);
out_be32((u32 *) GPIO1_ISR1H, 0x00000000);
out_be32((u32 *) GPIO0_ISR2L, 0x00000000);
out_be32((u32 *) GPIO0_ISR2H, 0x00000000);
out_be32((u32 *) GPIO1_ISR2L, 0x04010000);
out_be32((u32 *) GPIO1_ISR2H, 0x00000000);
out_be32((u32 *) GPIO0_ISR3L, 0x00000000);
out_be32((u32 *) GPIO0_ISR3H, 0x00000000);
out_be32((u32 *) GPIO1_ISR3L, 0x00000000);
out_be32((u32 *) GPIO1_ISR3H, 0x00000000);
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
@ -176,9 +80,8 @@ int board_early_init_f(void)
/* Configure the two Ethernet PHYs. For each PHY, configure for fiber
* if the SFP module is present, and for copper if it is not present.
*/
gpio0_ir = in_be32((u32 *) GPIO0_IR);
for (eth = 0; eth < 2; ++eth) {
if (gpio0_ir & (0x00000001 << (1 - eth))) {
if (gpio_read_in_bit(CFG_GPIO_SFP0_PRESENT_ + eth)) {
/* SFP module not present: configure PHY for copper. */
/* Set PHY to autonegotate 10 MB, 100MB, or 1 GB */
out_8((u8 *) CFG_CPLD_BASE + 0x06,
@ -187,14 +90,13 @@ int board_early_init_f(void)
} else {
/* SFP module present: configure PHY for fiber and
enable output */
out_be32((u32 *) GPIO0_OR, in_be32((u32 *) GPIO0_OR) |
(0x00000001 << (4 - eth)));
out_be32((u32 *) GPIO1_OR, in_be32((u32 *) GPIO1_OR) &
~(0x00000001 << (31 - eth)));
gpio_write_bit(CFG_GPIO_PHY0_FIBER_SEL + eth, 1);
gpio_write_bit(CFG_GPIO_SFP0_TX_EN_ + eth, 0);
}
}
/* enable Ethernet: set GPIO45 and GPIO46 to 1 */
out_be32((u32 *) GPIO1_OR, in_be32((u32 *) GPIO1_OR) | 0x00060000);
gpio_write_bit(CFG_GPIO_PHY0_EN, 1);
gpio_write_bit(CFG_GPIO_PHY1_EN, 1);
/* select Ethernet pins */
mfsdr(SDR0_PFC1, sdr0_pfc1);
@ -525,20 +427,19 @@ int checkboard(void)
{
char const *const s = getenv("serial#");
u8 const rev = in_8((u8 *) CFG_CPLD_BASE + 0);
u32 const gpio0_or = in_be32((u32 *) GPIO0_OR);
printf("Board: Korat, Rev. %X", rev);
if (s != NULL)
printf(", serial# %s", s);
printf(", Ethernet PHY 0: ");
if (gpio0_or & 0x00000010)
if (gpio_read_out_bit(CFG_GPIO_PHY0_FIBER_SEL))
printf("fiber");
else
printf("copper");
printf(", PHY 1: ");
if (gpio0_or & 0x00000008)
if (gpio_read_out_bit(CFG_GPIO_PHY1_FIBER_SEL))
printf("fiber");
else
printf("copper");

2
board/lwmon5/init.S
View File

@ -57,7 +57,7 @@ tlbtab:
#ifdef CFG_INIT_RAM_DCACHE
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
tlbentry(CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
#endif
/* TLB-entry for PCI Memory */

357
board/lwmon5/sdram.c
View File

@ -36,8 +36,6 @@
#include <asm/io.h>
#include <ppc440.h>
#include "sdram.h"
/*
* This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
* region. Right now the cache should still be disabled in U-Boot because of the
@ -54,8 +52,13 @@
#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
#endif
void dcbz_area(u32 start_address, u32 num_bytes);
void dflush(void);
/*-----------------------------------------------------------------------------+
* Prototypes
*-----------------------------------------------------------------------------*/
extern int denali_wait_for_dlllock(void);
extern void denali_core_search_data_eye(void);
extern void dcbz_area(u32 start_address, u32 num_bytes);
extern void dflush(void);
static u32 is_ecc_enabled(void)
{
@ -87,330 +90,6 @@ void board_add_ram_info(int use_default)
printf(", CL%d)", val);
}
static int wait_for_dlllock(void)
{
u32 val;
int wait = 0;
/*
* Wait for the DCC master delay line to finish calibration
*/
mtdcr(ddrcfga, DDR0_17);
val = DDR0_17_DLLLOCKREG_UNLOCKED;
while (wait != 0xffff) {
val = mfdcr(ddrcfgd);
if ((val & DDR0_17_DLLLOCKREG_MASK) == DDR0_17_DLLLOCKREG_LOCKED)
/* dlllockreg bit on */
return 0;
else
wait++;
}
debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val);
debug("Waiting for dlllockreg bit to raise\n");
return -1;
}
#if defined(CONFIG_DDR_DATA_EYE)
int wait_for_dram_init_complete(void)
{
u32 val;
int wait = 0;
/*
* Wait for 'DRAM initialization complete' bit in status register
*/
mtdcr(ddrcfga, DDR0_00);
while (wait != 0xffff) {
val = mfdcr(ddrcfgd);
if ((val & DDR0_00_INT_STATUS_BIT6) == DDR0_00_INT_STATUS_BIT6)
/* 'DRAM initialization complete' bit */
return 0;
else
wait++;
}
debug("DRAM initialization complete bit in status register did not rise\n");
return -1;
}
#define NUM_TRIES 64
#define NUM_READS 10
void denali_core_search_data_eye(u32 start_addr, u32 memory_size)
{
int k, j;
u32 val;
u32 wr_dqs_shift, dqs_out_shift, dll_dqs_delay_X;
u32 max_passing_cases = 0, wr_dqs_shift_with_max_passing_cases = 0;
u32 passing_cases = 0, dll_dqs_delay_X_sw_val = 0;
u32 dll_dqs_delay_X_start_window = 0, dll_dqs_delay_X_end_window = 0;
volatile u32 *ram_pointer;
u32 test[NUM_TRIES] = {
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
ram_pointer = (volatile u32 *)start_addr;
for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) {
/*for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) {*/
/*
* De-assert 'start' parameter.
*/
mtdcr(ddrcfga, DDR0_02);
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
mtdcr(ddrcfgd, val);
/*
* Set 'wr_dqs_shift'
*/
mtdcr(ddrcfga, DDR0_09);
val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
mtdcr(ddrcfgd, val);
/*
* Set 'dqs_out_shift' = wr_dqs_shift + 32
*/
dqs_out_shift = wr_dqs_shift + 32;
mtdcr(ddrcfga, DDR0_22);
val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
mtdcr(ddrcfgd, val);
passing_cases = 0;
for (dll_dqs_delay_X = 1; dll_dqs_delay_X < 64; dll_dqs_delay_X++) {
/*for (dll_dqs_delay_X=1; dll_dqs_delay_X<128; dll_dqs_delay_X++) {*/
/*
* Set 'dll_dqs_delay_X'.
*/
/* dll_dqs_delay_0 */
mtdcr(ddrcfga, DDR0_17);
val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
/* dll_dqs_delay_1 to dll_dqs_delay_4 */
mtdcr(ddrcfga, DDR0_18);
val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
/* dll_dqs_delay_5 to dll_dqs_delay_8 */
mtdcr(ddrcfga, DDR0_19);
val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
ppcMsync();
ppcMbar();
/*
* Assert 'start' parameter.
*/
mtdcr(ddrcfga, DDR0_02);
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
mtdcr(ddrcfgd, val);
ppcMsync();
ppcMbar();
/*
* Wait for the DCC master delay line to finish calibration
*/
if (wait_for_dlllock() != 0) {
printf("dlllock did not occur !!!\n");
printf("denali_core_search_data_eye!!!\n");
printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
wr_dqs_shift, dll_dqs_delay_X);
hang();
}
ppcMsync();
ppcMbar();
if (wait_for_dram_init_complete() != 0) {
printf("dram init complete did not occur !!!\n");
printf("denali_core_search_data_eye!!!\n");
printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
wr_dqs_shift, dll_dqs_delay_X);
hang();
}
udelay(100); /* wait 100us to ensure init is really completed !!! */
/* write values */
for (j=0; j<NUM_TRIES; j++) {
ram_pointer[j] = test[j];
/* clear any cache at ram location */
__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
}
/* read values back */
for (j=0; j<NUM_TRIES; j++) {
for (k=0; k<NUM_READS; k++) {
/* clear any cache at ram location */
__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
if (ram_pointer[j] != test[j])
break;
}
/* read error */
if (k != NUM_READS)
break;
}
/* See if the dll_dqs_delay_X value passed.*/
if (j < NUM_TRIES) {
/* Failed */
passing_cases = 0;
/* break; */
} else {
/* Passed */
if (passing_cases == 0)
dll_dqs_delay_X_sw_val = dll_dqs_delay_X;
passing_cases++;
if (passing_cases >= max_passing_cases) {
max_passing_cases = passing_cases;
wr_dqs_shift_with_max_passing_cases = wr_dqs_shift;
dll_dqs_delay_X_start_window = dll_dqs_delay_X_sw_val;
dll_dqs_delay_X_end_window = dll_dqs_delay_X;
}
}
/*
* De-assert 'start' parameter.
*/
mtdcr(ddrcfga, DDR0_02);
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
mtdcr(ddrcfgd, val);
} /* for (dll_dqs_delay_X=0; dll_dqs_delay_X<128; dll_dqs_delay_X++) */
} /* for (wr_dqs_shift=0; wr_dqs_shift<96; wr_dqs_shift++) */
/*
* Largest passing window is now detected.
*/
/* Compute dll_dqs_delay_X value */
dll_dqs_delay_X = (dll_dqs_delay_X_end_window + dll_dqs_delay_X_start_window) / 2;
wr_dqs_shift = wr_dqs_shift_with_max_passing_cases;
debug("DQS calibration - Window detected:\n");
debug("max_passing_cases = %d\n", max_passing_cases);
debug("wr_dqs_shift = %d\n", wr_dqs_shift);
debug("dll_dqs_delay_X = %d\n", dll_dqs_delay_X);
debug("dll_dqs_delay_X window = %d - %d\n",
dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window);
/*
* De-assert 'start' parameter.
*/
mtdcr(ddrcfga, DDR0_02);
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
mtdcr(ddrcfgd, val);
/*
* Set 'wr_dqs_shift'
*/
mtdcr(ddrcfga, DDR0_09);
val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
mtdcr(ddrcfgd, val);
debug("DDR0_09=0x%08lx\n", val);
/*
* Set 'dqs_out_shift' = wr_dqs_shift + 32
*/
dqs_out_shift = wr_dqs_shift + 32;
mtdcr(ddrcfga, DDR0_22);
val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
mtdcr(ddrcfgd, val);
debug("DDR0_22=0x%08lx\n", val);
/*
* Set 'dll_dqs_delay_X'.
*/
/* dll_dqs_delay_0 */
mtdcr(ddrcfga, DDR0_17);
val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
debug("DDR0_17=0x%08lx\n", val);
/* dll_dqs_delay_1 to dll_dqs_delay_4 */
mtdcr(ddrcfga, DDR0_18);
val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
debug("DDR0_18=0x%08lx\n", val);
/* dll_dqs_delay_5 to dll_dqs_delay_8 */
mtdcr(ddrcfga, DDR0_19);
val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
debug("DDR0_19=0x%08lx\n", val);
/*
* Assert 'start' parameter.
*/
mtdcr(ddrcfga, DDR0_02);
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
mtdcr(ddrcfgd, val);
ppcMsync();
ppcMbar();
/*
* Wait for the DCC master delay line to finish calibration
*/
if (wait_for_dlllock() != 0) {
printf("dlllock did not occur !!!\n");
hang();
}
ppcMsync();
ppcMbar();
if (wait_for_dram_init_complete() != 0) {
printf("dram init complete did not occur !!!\n");
hang();
}
udelay(100); /* wait 100us to ensure init is really completed !!! */
}
#endif /* CONFIG_DDR_DATA_EYE */
#ifdef CONFIG_DDR_ECC
static void wait_ddr_idle(void)
{
@ -610,12 +289,23 @@ long int initdram (int board_type)
mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
#endif
wait_for_dlllock();
denali_wait_for_dlllock();
#if defined(CONFIG_DDR_DATA_EYE)
/* -----------------------------------------------------------+
* Perform data eye search if requested.
* ----------------------------------------------------------*/
program_tlb(0, CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20,
TLB_WORD2_I_ENABLE);
denali_core_search_data_eye();
remove_tlb(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
#endif
/*
* Program tlb entries for this size (dynamic)
*/
program_tlb(0, 0, CFG_MBYTES_SDRAM << 20, MY_TLB_WORD2_I_ENABLE);
program_tlb(0, CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20,
MY_TLB_WORD2_I_ENABLE);
/*
* Setup 2nd TLB with same physical address but different virtual address
@ -623,13 +313,6 @@ long int initdram (int board_type)
*/
program_tlb(0, CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
#ifdef CONFIG_DDR_DATA_EYE
/*
* Perform data eye search if requested.
*/
denali_core_search_data_eye(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20);
#endif
#ifdef CONFIG_DDR_ECC
/*
* If ECC is enabled, initialize the parity bits.

505
board/lwmon5/sdram.h
View File

@ -1,505 +0,0 @@
/*
* (C) Copyright 2006
* Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
* Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
* Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _SPD_SDRAM_DENALI_H_
#define _SPD_SDRAM_DENALI_H_
#define ppcMsync sync
#define ppcMbar eieio
/* General definitions */
#define MAX_SPD_BYTE 128 /* highest SPD byte # to read */
#define DENALI_REG_NUMBER 45 /* 45 Regs in PPC440EPx Denali Core */
#define SUPPORTED_DIMMS_NB 7 /* Number of supported DIMM modules types */
#define SDRAM_NONE 0 /* No DIMM detected in Slot */
#define MAXRANKS 2 /* 2 ranks maximum */
/* Supported PLB Frequencies */
#define PLB_FREQ_133MHZ 133333333
#define PLB_FREQ_152MHZ 152000000
#define PLB_FREQ_160MHZ 160000000
#define PLB_FREQ_166MHZ 166666666
/* Denali Core Registers */
#define SDRAM_DCR_BASE 0x10
#define DDR_DCR_BASE 0x10
#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */
#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */
/*-----------------------------------------------------------------------------+
| Values for ddrcfga register - indirect addressing of these regs
+-----------------------------------------------------------------------------*/
#define DDR0_00 0x00
#define DDR0_00_INT_ACK_MASK 0x7F000000 /* Write only */
#define DDR0_00_INT_ACK_ALL 0x7F000000
#define DDR0_00_INT_ACK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
#define DDR0_00_INT_ACK_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
/* Status */
#define DDR0_00_INT_STATUS_MASK 0x00FF0000 /* Read only */
/* Bit0. A single access outside the defined PHYSICAL memory space detected. */
#define DDR0_00_INT_STATUS_BIT0 0x00010000
/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */
#define DDR0_00_INT_STATUS_BIT1 0x00020000
/* Bit2. Single correctable ECC event detected */
#define DDR0_00_INT_STATUS_BIT2 0x00040000
/* Bit3. Multiple correctable ECC events detected. */
#define DDR0_00_INT_STATUS_BIT3 0x00080000
/* Bit4. Single uncorrectable ECC event detected. */
#define DDR0_00_INT_STATUS_BIT4 0x00100000
/* Bit5. Multiple uncorrectable ECC events detected. */
#define DDR0_00_INT_STATUS_BIT5 0x00200000
/* Bit6. DRAM initialization complete. */
#define DDR0_00_INT_STATUS_BIT6 0x00400000
/* Bit7. Logical OR of all lower bits. */
#define DDR0_00_INT_STATUS_BIT7 0x00800000
#define DDR0_00_INT_STATUS_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
#define DDR0_00_INT_STATUS_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
#define DDR0_00_DLL_INCREMENT_MASK 0x00007F00
#define DDR0_00_DLL_INCREMENT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_00_DLL_INCREMENT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_00_DLL_START_POINT_MASK 0x0000007F
#define DDR0_00_DLL_START_POINT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_00_DLL_START_POINT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_01 0x01
#define DDR0_01_PLB0_DB_CS_LOWER_MASK 0x1F000000
#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
#define DDR0_01_PLB0_DB_CS_UPPER_MASK 0x001F0000
#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n) ((((unsigned long)(n))>>16)&0x1F)
#define DDR0_01_OUT_OF_RANGE_TYPE_MASK 0x00000700 /* Read only */
#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
#define DDR0_01_INT_MASK_MASK 0x000000FF
#define DDR0_01_INT_MASK_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
#define DDR0_01_INT_MASK_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
#define DDR0_01_INT_MASK_ALL_ON 0x000000FF
#define DDR0_01_INT_MASK_ALL_OFF 0x00000000
#define DDR0_02 0x02
#define DDR0_02_MAX_CS_REG_MASK 0x02000000 /* Read only */
#define DDR0_02_MAX_CS_REG_ENCODE(n) ((((unsigned long)(n))&0x2)<<24)
#define DDR0_02_MAX_CS_REG_DECODE(n) ((((unsigned long)(n))>>24)&0x2)
#define DDR0_02_MAX_COL_REG_MASK 0x000F0000 /* Read only */
#define DDR0_02_MAX_COL_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<16)
#define DDR0_02_MAX_COL_REG_DECODE(n) ((((unsigned long)(n))>>16)&0xF)
#define DDR0_02_MAX_ROW_REG_MASK 0x00000F00 /* Read only */
#define DDR0_02_MAX_ROW_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
#define DDR0_02_MAX_ROW_REG_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
#define DDR0_02_START_MASK 0x00000001
#define DDR0_02_START_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
#define DDR0_02_START_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
#define DDR0_02_START_OFF 0x00000000
#define DDR0_02_START_ON 0x00000001
#define DDR0_03 0x03
#define DDR0_03_BSTLEN_MASK 0x07000000
#define DDR0_03_BSTLEN_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
#define DDR0_03_BSTLEN_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
#define DDR0_03_CASLAT_MASK 0x00070000
#define DDR0_03_CASLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
#define DDR0_03_CASLAT_LIN_MASK 0x00000F00
#define DDR0_03_CASLAT_LIN_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
#define DDR0_03_CASLAT_LIN_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
#define DDR0_03_INITAREF_MASK 0x0000000F
#define DDR0_03_INITAREF_ENCODE(n) ((((unsigned long)(n))&0xF)<<0)
#define DDR0_03_INITAREF_DECODE(n) ((((unsigned long)(n))>>0)&0xF)
#define DDR0_04 0x04
#define DDR0_04_TRC_MASK 0x1F000000
#define DDR0_04_TRC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
#define DDR0_04_TRC_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
#define DDR0_04_TRRD_MASK 0x00070000
#define DDR0_04_TRRD_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
#define DDR0_04_TRRD_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
#define DDR0_04_TRTP_MASK 0x00000700
#define DDR0_04_TRTP_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
#define DDR0_04_TRTP_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
#define DDR0_05 0x05
#define DDR0_05_TMRD_MASK 0x1F000000
#define DDR0_05_TMRD_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
#define DDR0_05_TMRD_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
#define DDR0_05_TEMRS_MASK 0x00070000
#define DDR0_05_TEMRS_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
#define DDR0_05_TEMRS_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
#define DDR0_05_TRP_MASK 0x00000F00
#define DDR0_05_TRP_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
#define DDR0_05_TRP_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
#define DDR0_05_TRAS_MIN_MASK 0x000000FF
#define DDR0_05_TRAS_MIN_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
#define DDR0_05_TRAS_MIN_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
#define DDR0_06 0x06
#define DDR0_06_WRITEINTERP_MASK 0x01000000
#define DDR0_06_WRITEINTERP_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
#define DDR0_06_WRITEINTERP_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
#define DDR0_06_TWTR_MASK 0x00070000
#define DDR0_06_TWTR_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
#define DDR0_06_TWTR_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
#define DDR0_06_TDLL_MASK 0x0000FF00
#define DDR0_06_TDLL_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
#define DDR0_06_TDLL_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
#define DDR0_06_TRFC_MASK 0x0000007F
#define DDR0_06_TRFC_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_06_TRFC_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_07 0x07
#define DDR0_07_NO_CMD_INIT_MASK 0x01000000
#define DDR0_07_NO_CMD_INIT_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
#define DDR0_07_NO_CMD_INIT_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
#define DDR0_07_TFAW_MASK 0x001F0000
#define DDR0_07_TFAW_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
#define DDR0_07_TFAW_DECODE(n) ((((unsigned long)(n))>>16)&0x1F)
#define DDR0_07_AUTO_REFRESH_MODE_MASK 0x00000100
#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
#define DDR0_07_AREFRESH_MASK 0x00000001
#define DDR0_07_AREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
#define DDR0_07_AREFRESH_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
#define DDR0_08 0x08
#define DDR0_08_WRLAT_MASK 0x07000000
#define DDR0_08_WRLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
#define DDR0_08_WRLAT_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
#define DDR0_08_TCPD_MASK 0x00FF0000
#define DDR0_08_TCPD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
#define DDR0_08_TCPD_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
#define DDR0_08_DQS_N_EN_MASK 0x00000100
#define DDR0_08_DQS_N_EN_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
#define DDR0_08_DQS_N_EN_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
#define DDR0_08_DDRII_SDRAM_MODE_MASK 0x00000001
#define DDR0_08_DDRII_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
#define DDR0_08_DDRII_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
#define DDR0_09 0x09
#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK 0x1F000000
#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
#define DDR0_09_RTT_0_MASK 0x00030000
#define DDR0_09_RTT_0_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
#define DDR0_09_RTT_0_DECODE(n) ((((unsigned long)(n))>>16)&0x3)
#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK 0x00007F00
#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_09_WR_DQS_SHIFT_MASK 0x0000007F
#define DDR0_09_WR_DQS_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_09_WR_DQS_SHIFT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_10 0x0A
#define DDR0_10_WRITE_MODEREG_MASK 0x00010000 /* Write only */
#define DDR0_10_WRITE_MODEREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
#define DDR0_10_WRITE_MODEREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
#define DDR0_10_CS_MAP_MASK 0x00000300
#define DDR0_10_CS_MAP_NO_MEM 0x00000000
#define DDR0_10_CS_MAP_RANK0_INSTALLED 0x00000100
#define DDR0_10_CS_MAP_RANK1_INSTALLED 0x00000200
#define DDR0_10_CS_MAP_ENCODE(n) ((((unsigned long)(n))&0x3)<<8)
#define DDR0_10_CS_MAP_DECODE(n) ((((unsigned long)(n))>>8)&0x3)
#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK 0x0000001F
#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<0)
#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x1F)
#define DDR0_11 0x0B
#define DDR0_11_SREFRESH_MASK 0x01000000
#define DDR0_11_SREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
#define DDR0_11_SREFRESH_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
#define DDR0_11_TXSNR_MASK 0x00FF0000
#define DDR0_11_TXSNR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
#define DDR0_11_TXSNR_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
#define DDR0_11_TXSR_MASK 0x0000FF00
#define DDR0_11_TXSR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
#define DDR0_11_TXSR_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
#define DDR0_12 0x0C
#define DDR0_12_TCKE_MASK 0x0000007
#define DDR0_12_TCKE_ENCODE(n) ((((unsigned long)(n))&0x7)<<0)
#define DDR0_12_TCKE_DECODE(n) ((((unsigned long)(n))>>0)&0x7)
#define DDR0_13 0x0D
#define DDR0_14 0x0E
#define DDR0_14_DLL_BYPASS_MODE_MASK 0x01000000
#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
#define DDR0_14_DLL_BYPASS_MODE_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
#define DDR0_14_REDUC_MASK 0x00010000
#define DDR0_14_REDUC_64BITS 0x00000000
#define DDR0_14_REDUC_32BITS 0x00010000
#define DDR0_14_REDUC_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
#define DDR0_14_REDUC_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
#define DDR0_14_REG_DIMM_ENABLE_MASK 0x00000100
#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
#define DDR0_14_REG_DIMM_ENABLE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
#define DDR0_15 0x0F
#define DDR0_16 0x10
#define DDR0_17 0x11
#define DDR0_17_DLL_DQS_DELAY_0_MASK 0x7F000000
#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */
#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000
#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000
#define DDR0_17_DLLLOCKREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
#define DDR0_17_DLLLOCKREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
#define DDR0_17_DLL_LOCK_MASK 0x00007F00 /* Read only */
#define DDR0_17_DLL_LOCK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_17_DLL_LOCK_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_18 0x12
#define DDR0_18_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
#define DDR0_18_DLL_DQS_DELAY_4_MASK 0x7F000000
#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
#define DDR0_18_DLL_DQS_DELAY_3_MASK 0x007F0000
#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
#define DDR0_18_DLL_DQS_DELAY_2_MASK 0x00007F00
#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_18_DLL_DQS_DELAY_1_MASK 0x0000007F
#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_19 0x13
#define DDR0_19_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
#define DDR0_19_DLL_DQS_DELAY_8_MASK 0x7F000000
#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
#define DDR0_19_DLL_DQS_DELAY_7_MASK 0x007F0000
#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
#define DDR0_19_DLL_DQS_DELAY_6_MASK 0x00007F00
#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_19_DLL_DQS_DELAY_5_MASK 0x0000007F
#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_20 0x14
#define DDR0_20_DLL_DQS_BYPASS_3_MASK 0x7F000000
#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
#define DDR0_20_DLL_DQS_BYPASS_2_MASK 0x007F0000
#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
#define DDR0_20_DLL_DQS_BYPASS_1_MASK 0x00007F00
#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_20_DLL_DQS_BYPASS_0_MASK 0x0000007F
#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_21 0x15
#define DDR0_21_DLL_DQS_BYPASS_7_MASK 0x7F000000
#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
#define DDR0_21_DLL_DQS_BYPASS_6_MASK 0x007F0000
#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
#define DDR0_21_DLL_DQS_BYPASS_5_MASK 0x00007F00
#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_21_DLL_DQS_BYPASS_4_MASK 0x0000007F
#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_22 0x16
/* ECC */
#define DDR0_22_CTRL_RAW_MASK 0x03000000
#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not being used */
#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC checking is on, but no attempts to correct*/
#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* No ECC RAM storage available */
#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC checking and correcting on */
#define DDR0_22_CTRL_RAW_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
#define DDR0_22_CTRL_RAW_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000
#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
#define DDR0_22_DQS_OUT_SHIFT_MASK 0x00007F00
#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_22_DQS_OUT_SHIFT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_22_DLL_DQS_BYPASS_8_MASK 0x0000007F
#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_23 0x17
#define DDR0_23_ODT_RD_MAP_CS0_MASK 0x03000000
#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
#define DDR0_23_ECC_C_SYND_MASK 0x00FF0000 /* Read only */
#define DDR0_23_ECC_C_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
#define DDR0_23_ECC_C_SYND_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
#define DDR0_23_ECC_U_SYND_MASK 0x0000FF00 /* Read only */
#define DDR0_23_ECC_U_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
#define DDR0_23_ECC_U_SYND_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
#define DDR0_23_FWC_MASK 0x00000001 /* Write only */
#define DDR0_23_FWC_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
#define DDR0_23_FWC_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
#define DDR0_24 0x18
#define DDR0_24_RTT_PAD_TERMINATION_MASK 0x03000000
#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
#define DDR0_24_ODT_WR_MAP_CS1_MASK 0x00030000
#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>16)&0x3)
#define DDR0_24_ODT_RD_MAP_CS1_MASK 0x00000300
#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<8)
#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>8)&0x3)
#define DDR0_24_ODT_WR_MAP_CS0_MASK 0x00000003
#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<0)
#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>0)&0x3)
#define DDR0_25 0x19
#define DDR0_25_VERSION_MASK 0xFFFF0000 /* Read only */
#define DDR0_25_VERSION_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
#define DDR0_25_VERSION_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK 0x000003FF /* Read only */
#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
#define DDR0_26 0x1A
#define DDR0_26_TRAS_MAX_MASK 0xFFFF0000
#define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
#define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
#define DDR0_26_TREF_MASK 0x00003FFF
#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0)
#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF)
#define DDR0_27 0x1B
#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000
#define DDR0_27_EMRS_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16)
#define DDR0_27_EMRS_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF)
#define DDR0_27_TINIT_MASK 0x0000FFFF
#define DDR0_27_TINIT_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0)
#define DDR0_27_TINIT_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF)
#define DDR0_28 0x1C
#define DDR0_28_EMRS3_DATA_MASK 0x3FFF0000
#define DDR0_28_EMRS3_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16)
#define DDR0_28_EMRS3_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF)
#define DDR0_28_EMRS2_DATA_MASK 0x00003FFF
#define DDR0_28_EMRS2_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0)
#define DDR0_28_EMRS2_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF)
#define DDR0_29 0x1D
#define DDR0_30 0x1E
#define DDR0_31 0x1F
#define DDR0_31_XOR_CHECK_BITS_MASK 0x0000FFFF
#define DDR0_31_XOR_CHECK_BITS_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0)
#define DDR0_31_XOR_CHECK_BITS_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF)
#define DDR0_32 0x20
#define DDR0_32_OUT_OF_RANGE_ADDR_MASK 0xFFFFFFFF /* Read only */
#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
#define DDR0_33 0x21
#define DDR0_33_OUT_OF_RANGE_ADDR_MASK 0x00000001 /* Read only */
#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
#define DDR0_34 0x22
#define DDR0_34_ECC_U_ADDR_MASK 0xFFFFFFFF /* Read only */
#define DDR0_34_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
#define DDR0_34_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
#define DDR0_35 0x23
#define DDR0_35_ECC_U_ADDR_MASK 0x00000001 /* Read only */
#define DDR0_35_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
#define DDR0_35_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
#define DDR0_36 0x24
#define DDR0_36_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
#define DDR0_36_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
#define DDR0_36_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
#define DDR0_37 0x25
#define DDR0_37_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
#define DDR0_37_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
#define DDR0_37_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
#define DDR0_38 0x26
#define DDR0_38_ECC_C_ADDR_MASK 0xFFFFFFFF /* Read only */
#define DDR0_38_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
#define DDR0_38_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
#define DDR0_39 0x27
#define DDR0_39_ECC_C_ADDR_MASK 0x00000001 /* Read only */
#define DDR0_39_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
#define DDR0_39_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
#define DDR0_40 0x28
#define DDR0_40_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
#define DDR0_40_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
#define DDR0_40_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
#define DDR0_41 0x29
#define DDR0_41_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
#define DDR0_41_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
#define DDR0_41_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
#define DDR0_42 0x2A
#define DDR0_42_ADDR_PINS_MASK 0x07000000
#define DDR0_42_ADDR_PINS_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
#define DDR0_42_ADDR_PINS_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
#define DDR0_42_CASLAT_LIN_GATE_MASK 0x0000000F
#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n) ((((unsigned long)(n))&0xF)<<0)
#define DDR0_42_CASLAT_LIN_GATE_DECODE(n) ((((unsigned long)(n))>>0)&0xF)
#define DDR0_43 0x2B
#define DDR0_43_TWR_MASK 0x07000000
#define DDR0_43_TWR_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
#define DDR0_43_TWR_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
#define DDR0_43_APREBIT_MASK 0x000F0000
#define DDR0_43_APREBIT_ENCODE(n) ((((unsigned long)(n))&0xF)<<16)
#define DDR0_43_APREBIT_DECODE(n) ((((unsigned long)(n))>>16)&0xF)
#define DDR0_43_COLUMN_SIZE_MASK 0x00000700
#define DDR0_43_COLUMN_SIZE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
#define DDR0_43_COLUMN_SIZE_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
#define DDR0_43_EIGHT_BANK_MODE_MASK 0x00000001
#define DDR0_43_EIGHT_BANK_MODE_8_BANKS 0x00000001
#define DDR0_43_EIGHT_BANK_MODE_4_BANKS 0x00000000
#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
#define DDR0_43_EIGHT_BANK_MODE_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
#define DDR0_44 0x2C
#define DDR0_44_TRCD_MASK 0x000000FF
#define DDR0_44_TRCD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
#define DDR0_44_TRCD_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
#endif /* _SPD_SDRAM_DENALI_H_ */

50
board/sbc8349/pci.c
View File

@ -30,6 +30,10 @@
#include <pci.h>
#include <asm/mpc8349_pci.h>
#include <i2c.h>
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#include <fdt_support.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
@ -323,26 +327,40 @@ pci_init_board(void)
}
#ifdef CONFIG_OF_FLAT_TREE
void
ft_pci_setup(void *blob, bd_t *bd)
#if defined(CONFIG_OF_LIBFDT)
void ft_pci_setup(void *blob, bd_t *bd)
{
u32 *p;
int len;
int nodeoffset;
int tmp[2];
const char *path;
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
if (p != NULL) {
p[0] = pci_hose[0].first_busno;
p[1] = pci_hose[0].last_busno;
nodeoffset = fdt_path_offset(blob, "/aliases");
if (nodeoffset >= 0) {
path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
if (path) {
tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
do_fixup_by_path(blob, path, "bus-range",
&tmp, sizeof(tmp), 1);
tmp[0] = cpu_to_be32(gd->pci_clk);
do_fixup_by_path(blob, path, "clock-frequency",
&tmp, sizeof(tmp[0]), 1);
}
#ifdef CONFIG_MPC83XX_PCI2
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len);
if (p != NULL) {
p[0] = pci_hose[1].first_busno;
p[1] = pci_hose[1].last_busno;
}
path = fdt_getprop(blob, nodeoffset, "pci1", NULL);
if (path) {
tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
do_fixup_by_path(blob, path, "bus-range",
&tmp, sizeof(tmp), 1);
tmp[0] = cpu_to_be32(gd->pci_clk);
do_fixup_by_path(blob, path, "clock-frequency",
&tmp, sizeof(tmp[0]), 1);
}
#endif
}
}
#endif /* CONFIG_OF_FLAT_TREE */
#endif /* CONFIG_OF_LIBFDT */
#endif /* CONFIG_PCI */

347
board/sbc8349/sbc8349.c
View File

@ -32,12 +32,11 @@
#include <i2c.h>
#include <spd.h>
#include <miiphy.h>
#include <command.h>
#if defined(CONFIG_SPD_EEPROM)
#include <spd_sdram.h>
#endif
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
int fixed_sdram(void);
@ -235,348 +234,12 @@ void sdram_init(void)
}
#endif
#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
/*
* ECC user commands
*/
void ecc_print_status(void)
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ddr83xx_t *ddr = &immap->ddr;
printf("\nECC mode: %s\n\n", (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
/* Interrupts */
printf("Memory Error Interrupt Enable:\n");
printf(" Multiple-Bit Error Interrupt Enable: %d\n",
(ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0);
printf(" Single-Bit Error Interrupt Enable: %d\n",
(ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0);
printf(" Memory Select Error Interrupt Enable: %d\n\n",
(ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0);
/* Error disable */
printf("Memory Error Disable:\n");
printf(" Multiple-Bit Error Disable: %d\n",
(ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
printf(" Sinle-Bit Error Disable: %d\n",
(ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
printf(" Memory Select Error Disable: %d\n\n",
(ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);
/* Error injection */
printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n",
ddr->data_err_inject_hi, ddr->data_err_inject_lo);
printf("Memory Data Path Error Injection Mask ECC:\n");
printf(" ECC Mirror Byte: %d\n",
(ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0);
printf(" ECC Injection Enable: %d\n",
(ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0);
printf(" ECC Error Injection Mask: 0x%02x\n\n",
ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM);
/* SBE counter/threshold */
printf("Memory Single-Bit Error Management (0..255):\n");
printf(" Single-Bit Error Threshold: %d\n",
(ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT);
printf(" Single-Bit Error Counter: %d\n\n",
(ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT);
/* Error detect */
printf("Memory Error Detect:\n");
printf(" Multiple Memory Errors: %d\n",
(ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0);
printf(" Multiple-Bit Error: %d\n",
(ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0);
printf(" Single-Bit Error: %d\n",
(ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0);
printf(" Memory Select Error: %d\n\n",
(ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0);
/* Capture data */
printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address);
printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n",
ddr->capture_data_hi, ddr->capture_data_lo);
printf("Memory Data Path Read Capture ECC: 0x%02x\n\n",
ddr->capture_ecc & CAPTURE_ECC_ECE);
printf("Memory Error Attributes Capture:\n");
printf(" Data Beat Number: %d\n",
(ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >> ECC_CAPT_ATTR_BNUM_SHIFT);
printf(" Transaction Size: %d\n",
(ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >> ECC_CAPT_ATTR_TSIZ_SHIFT);
printf(" Transaction Source: %d\n",
(ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >> ECC_CAPT_ATTR_TSRC_SHIFT);
printf(" Transaction Type: %d\n",
(ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >> ECC_CAPT_ATTR_TTYP_SHIFT);
printf(" Error Information Valid: %d\n\n",
ddr->capture_attributes & ECC_CAPT_ATTR_VLD);
}
int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ddr83xx_t *ddr = &immap->ddr;
volatile u32 val;
u64 *addr, count, val64;
register u64 *i;
if (argc > 4) {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
if (argc == 2) {
if (strcmp(argv[1], "status") == 0) {
ecc_print_status();
return 0;
} else if (strcmp(argv[1], "captureclear") == 0) {
ddr->capture_address = 0;
ddr->capture_data_hi = 0;
ddr->capture_data_lo = 0;
ddr->capture_ecc = 0;
ddr->capture_attributes = 0;
return 0;
}
}
if (argc == 3) {
if (strcmp(argv[1], "sbecnt") == 0) {
val = simple_strtoul(argv[2], NULL, 10);
if (val > 255) {
printf("Incorrect Counter value, should be 0..255\n");
return 1;
}
val = (val << ECC_ERROR_MAN_SBEC_SHIFT);
val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET);
ddr->err_sbe = val;
return 0;
} else if (strcmp(argv[1], "sbethr") == 0) {
val = simple_strtoul(argv[2], NULL, 10);
if (val > 255) {
printf("Incorrect Counter value, should be 0..255\n");
return 1;
}
val = (val << ECC_ERROR_MAN_SBET_SHIFT);
val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC);
ddr->err_sbe = val;
return 0;
} else if (strcmp(argv[1], "errdisable") == 0) {
val = ddr->err_disable;
if (strcmp(argv[2], "+sbe") == 0) {
val |= ECC_ERROR_DISABLE_SBED;
} else if (strcmp(argv[2], "+mbe") == 0) {
val |= ECC_ERROR_DISABLE_MBED;
} else if (strcmp(argv[2], "+mse") == 0) {
val |= ECC_ERROR_DISABLE_MSED;
} else if (strcmp(argv[2], "+all") == 0) {
val |= (ECC_ERROR_DISABLE_SBED |
ECC_ERROR_DISABLE_MBED |
ECC_ERROR_DISABLE_MSED);
} else if (strcmp(argv[2], "-sbe") == 0) {
val &= ~ECC_ERROR_DISABLE_SBED;
} else if (strcmp(argv[2], "-mbe") == 0) {
val &= ~ECC_ERROR_DISABLE_MBED;
} else if (strcmp(argv[2], "-mse") == 0) {
val &= ~ECC_ERROR_DISABLE_MSED;
} else if (strcmp(argv[2], "-all") == 0) {
val &= ~(ECC_ERROR_DISABLE_SBED |
ECC_ERROR_DISABLE_MBED |
ECC_ERROR_DISABLE_MSED);
} else {
printf("Incorrect err_disable field\n");
return 1;
}
ddr->err_disable = val;
__asm__ __volatile__ ("sync");
__asm__ __volatile__ ("isync");
return 0;
} else if (strcmp(argv[1], "errdetectclr") == 0) {
val = ddr->err_detect;
if (strcmp(argv[2], "mme") == 0) {
val |= ECC_ERROR_DETECT_MME;
} else if (strcmp(argv[2], "sbe") == 0) {
val |= ECC_ERROR_DETECT_SBE;
} else if (strcmp(argv[2], "mbe") == 0) {
val |= ECC_ERROR_DETECT_MBE;
} else if (strcmp(argv[2], "mse") == 0) {
val |= ECC_ERROR_DETECT_MSE;
} else if (strcmp(argv[2], "all") == 0) {
val |= (ECC_ERROR_DETECT_MME |
ECC_ERROR_DETECT_MBE |
ECC_ERROR_DETECT_SBE |
ECC_ERROR_DETECT_MSE);
} else {
printf("Incorrect err_detect field\n");
return 1;
}
ddr->err_detect = val;
return 0;
} else if (strcmp(argv[1], "injectdatahi") == 0) {
val = simple_strtoul(argv[2], NULL, 16);
ddr->data_err_inject_hi = val;
return 0;
} else if (strcmp(argv[1], "injectdatalo") == 0) {
val = simple_strtoul(argv[2], NULL, 16);
ddr->data_err_inject_lo = val;
return 0;
} else if (strcmp(argv[1], "injectecc") == 0) {
val = simple_strtoul(argv[2], NULL, 16);
if (val > 0xff) {
printf("Incorrect ECC inject mask, should be 0x00..0xff\n");
return 1;
}
val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM);
ddr->ecc_err_inject = val;
return 0;
} else if (strcmp(argv[1], "inject") == 0) {
val = ddr->ecc_err_inject;
if (strcmp(argv[2], "en") == 0)
val |= ECC_ERR_INJECT_EIEN;
else if (strcmp(argv[2], "dis") == 0)
val &= ~ECC_ERR_INJECT_EIEN;
else
printf("Incorrect command\n");
ddr->ecc_err_inject = val;
__asm__ __volatile__ ("sync");
__asm__ __volatile__ ("isync");
return 0;
} else if (strcmp(argv[1], "mirror") == 0) {
val = ddr->ecc_err_inject;
if (strcmp(argv[2], "en") == 0)
val |= ECC_ERR_INJECT_EMB;
else if (strcmp(argv[2], "dis") == 0)
val &= ~ECC_ERR_INJECT_EMB;
else
printf("Incorrect command\n");
ddr->ecc_err_inject = val;
return 0;
}
}
if (argc == 4) {
if (strcmp(argv[1], "test") == 0) {
addr = (u64 *)simple_strtoul(argv[2], NULL, 16);
count = simple_strtoul(argv[3], NULL, 16);
if ((u32)addr % 8) {
printf("Address not alligned on double word boundary\n");
return 1;
}
disable_interrupts();
icache_disable();
for (i = addr; i < addr + count; i++) {
/* enable injects */
ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
__asm__ __volatile__ ("sync");
__asm__ __volatile__ ("isync");
/* write memory location injecting errors */
*i = 0x1122334455667788ULL;
__asm__ __volatile__ ("sync");
/* disable injects */
ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
__asm__ __volatile__ ("sync");
__asm__ __volatile__ ("isync");
/* read data, this generates ECC error */
val64 = *i;
__asm__ __volatile__ ("sync");
/* disable errors for ECC */
ddr->err_disable |= ~ECC_ERROR_ENABLE;
__asm__ __volatile__ ("sync");
__asm__ __volatile__ ("isync");
/* re-initialize memory, write the location again
* NOT injecting errors this time */
*i = 0xcafecafecafecafeULL;
__asm__ __volatile__ ("sync");
/* enable errors for ECC */
ddr->err_disable &= ECC_ERROR_ENABLE;
__asm__ __volatile__ ("sync");
__asm__ __volatile__ ("isync");
}
icache_enable();
enable_interrupts();
return 0;
}
}
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
U_BOOT_CMD(
ecc, 4, 0, do_ecc,
"ecc - support for DDR ECC features\n",
"status - print out status info\n"
"ecc captureclear - clear capture regs data\n"
"ecc sbecnt <val> - set Single-Bit Error counter\n"
"ecc sbethr <val> - set Single-Bit Threshold\n"
"ecc errdisable <flag> - clear/set disable Memory Error Disable, flag:\n"
" [-|+]sbe - Single-Bit Error\n"
" [-|+]mbe - Multiple-Bit Error\n"
" [-|+]mse - Memory Select Error\n"
" [-|+]all - all errors\n"
"ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n"
" mme - Multiple Memory Errors\n"
" sbe - Single-Bit Error\n"
" mbe - Multiple-Bit Error\n"
" mse - Memory Select Error\n"
" all - all errors\n"
"ecc injectdatahi <hi> - set Memory Data Path Error Injection Mask High\n"
"ecc injectdatalo <lo> - set Memory Data Path Error Injection Mask Low\n"
"ecc injectecc <ecc> - set ECC Error Injection Mask\n"
"ecc inject <en|dis> - enable/disable error injection\n"
"ecc mirror <en|dis> - enable/disable mirror byte\n"
"ecc test <addr> <cnt> - test mem region:\n"
" - enables injects\n"
" - writes pattern injecting errors\n"
" - disables injects\n"
" - reads pattern back, generates error\n"
" - re-inits memory"
);
#endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
void
ft_board_setup(void *blob, bd_t *bd)
{
u32 *p;
int len;
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
ft_cpu_setup(blob, bd);
p = ft_get_prop(blob, "/memory/reg", &len);
if (p != NULL) {
*p++ = cpu_to_be32(bd->bi_memstart);
*p = cpu_to_be32(bd->bi_memsize);
}
}
#endif

4
common/ACEX1K.c
View File

@ -28,7 +28,7 @@
#include <common.h> /* core U-Boot definitions */
#include <ACEX1K.h> /* ACEX device family */
#if (CONFIG_FPGA & (CFG_ALTERA | CFG_ACEX1K))
#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA) && defined(CONFIG_FPGA_ACEX1K)
/* Define FPGA_DEBUG to get debug printf's */
#ifdef FPGA_DEBUG
@ -363,4 +363,4 @@ static int ACEX1K_ps_reloc (Altera_desc * desc, ulong reloc_offset)
}
#endif /* (CONFIG_FPGA & (CFG_ALTERA | CFG_ACEX1K)) */
#endif /* CONFIG_FPGA && CONFIG_FPGA_ALTERA && CONFIG_FPGA_ACEX1K */

1
common/Makefile
View File

@ -86,6 +86,7 @@ COBJS-$(CONFIG_CMD_REISER) += cmd_reiser.o
COBJS-y += cmd_sata.o
COBJS-$(CONFIG_CMD_SCSI) += cmd_scsi.o
COBJS-$(CONFIG_CMD_SPI) += cmd_spi.o
COBJS-$(CONFIG_CMD_TERMINAL) += cmd_terminal.o
COBJS-$(CONFIG_CMD_UNIVERSE) += cmd_universe.o
COBJS-$(CONFIG_CMD_USB) += cmd_usb.o
COBJS-y += cmd_vfd.o

18
common/altera.c
View File

@ -40,7 +40,7 @@
#define PRINTF(fmt,args...)
#endif
#if (CONFIG_FPGA & CFG_FPGA_ALTERA)
#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA)
/* Local Static Functions */
static int altera_validate (Altera_desc * desc, char *fn);
@ -56,11 +56,11 @@ int altera_load( Altera_desc *desc, void *buf, size_t bsize )
switch (desc->family) {
case Altera_ACEX1K:
case Altera_CYC2:
#if (CONFIG_FPGA & CFG_ACEX1K)
#if defined(CONFIG_FPGA_ACEX1K)
PRINTF ("%s: Launching the ACEX1K Loader...\n",
__FUNCTION__);
ret_val = ACEX1K_load (desc, buf, bsize);
#elif (CONFIG_FPGA & CFG_CYCLON2)
#elif defined CONFIG_FPGA_CYCLON2
PRINTF ("%s: Launching the CYCLON II Loader...\n",
__FUNCTION__);
ret_val = CYC2_load (desc, buf, bsize);
@ -88,7 +88,7 @@ int altera_dump( Altera_desc *desc, void *buf, size_t bsize )
} else {
switch (desc->family) {
case Altera_ACEX1K:
#if (CONFIG_FPGA & CFG_ACEX)
#if defined(CONFIG_FPGA_ACEX)
PRINTF ("%s: Launching the ACEX1K Reader...\n",
__FUNCTION__);
ret_val = ACEX1K_dump (desc, buf, bsize);
@ -156,9 +156,9 @@ int altera_info( Altera_desc *desc )
switch (desc->family) {
case Altera_ACEX1K:
case Altera_CYC2:
#if (CONFIG_FPGA & CFG_ACEX1K)
#if defined(CONFIG_FPGA_ACEX1K)
ACEX1K_info (desc);
#elif (CONFIG_FPGA & CFG_CYCLON2)
#elif defined(CONFIG_FPGA_CYCLON2)
CYC2_info (desc);
#else
/* just in case */
@ -192,7 +192,7 @@ int altera_reloc( Altera_desc *desc, ulong reloc_offset)
} else {
switch (desc->family) {
case Altera_ACEX1K:
#if (CONFIG_FPGA & CFG_ACEX1K)
#if defined(CONFIG_FPGA_ACEX1K)
ret_val = ACEX1K_reloc (desc, reloc_offset);
#else
printf ("%s: No support for ACEX devices.\n",
@ -200,7 +200,7 @@ int altera_reloc( Altera_desc *desc, ulong reloc_offset)
#endif
break;
case Altera_CYC2:
#if (CONFIG_FPGA & CFG_CYCLON2)
#if defined(CONFIG_FPGA_CYCLON2)
ret_val = CYC2_reloc (desc, reloc_offset);
#else
printf ("%s: No support for CYCLON II devices.\n",
@ -249,4 +249,4 @@ static int altera_validate (Altera_desc * desc, char *fn)
/* ------------------------------------------------------------------------- */
#endif /* CONFIG_FPGA & CFG_FPGA_ALTERA */
#endif /* CONFIG_FPGA & CONFIG_FPGA_ALTERA */

134
common/cmd_bmp.c
View File

@ -36,6 +36,62 @@ static int bmp_display (ulong addr, int x, int y);
int gunzip(void *, int, unsigned char *, unsigned long *);
/*
* Allocate and decompress a BMP image using gunzip().
*
* Returns a pointer to the decompressed image data. Must be freed by
* the caller after use.
*
* Returns NULL if decompression failed, or if the decompressed data
* didn't contain a valid BMP signature.
*/
#ifdef CONFIG_VIDEO_BMP_GZIP
static bmp_image_t *gunzip_bmp(unsigned long addr, unsigned long *lenp)
{
void *dst;
unsigned long len;
bmp_image_t *bmp;
/*
* Decompress bmp image
*/
len = CFG_VIDEO_LOGO_MAX_SIZE;
dst = malloc(CFG_VIDEO_LOGO_MAX_SIZE);
if (dst == NULL) {
puts("Error: malloc in gunzip failed!\n");
return NULL;
}
if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE, (uchar *)addr, &len) != 0) {
free(dst);
return NULL;
}
if (len == CFG_VIDEO_LOGO_MAX_SIZE)
puts("Image could be truncated"
" (increase CFG_VIDEO_LOGO_MAX_SIZE)!\n");
bmp = dst;
/*
* Check for bmp mark 'BM'
*/
if (!((bmp->header.signature[0] == 'B') &&
(bmp->header.signature[1] == 'M'))) {
free(dst);
return NULL;
}
puts("Gzipped BMP image detected!\n");
return bmp;
}
#else
static bmp_image_t *gunzip_bmp(unsigned long addr)
{
return NULL;
}
#endif
/*
* Subroutine: do_bmp
*
@ -101,63 +157,24 @@ U_BOOT_CMD(
static int bmp_info(ulong addr)
{
bmp_image_t *bmp=(bmp_image_t *)addr;
#ifdef CONFIG_VIDEO_BMP_GZIP
unsigned char *dst = NULL;
ulong len;
#endif /* CONFIG_VIDEO_BMP_GZIP */
unsigned long len;
if (!((bmp->header.signature[0]=='B') &&
(bmp->header.signature[1]=='M'))) {
(bmp->header.signature[1]=='M')))
bmp = gunzip_bmp(addr, &len);
#ifdef CONFIG_VIDEO_BMP_GZIP
/*
* Decompress bmp image
*/
len = CFG_VIDEO_LOGO_MAX_SIZE;
dst = malloc(CFG_VIDEO_LOGO_MAX_SIZE);
if (dst == NULL) {
printf("Error: malloc in gunzip failed!\n");
return(1);
}
if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE, (uchar *)addr, &len) != 0) {
printf("There is no valid bmp file at the given address\n");
return(1);
}
if (len == CFG_VIDEO_LOGO_MAX_SIZE) {
printf("Image could be truncated (increase CFG_VIDEO_LOGO_MAX_SIZE)!\n");
}
/*
* Set addr to decompressed image
*/
bmp = (bmp_image_t *)dst;
/*
* Check for bmp mark 'BM'
*/
if (!((bmp->header.signature[0] == 'B') &&
(bmp->header.signature[1] == 'M'))) {
printf("There is no valid bmp file at the given address\n");
free(dst);
return(1);
}
printf("Gzipped BMP image detected!\n");
#else /* CONFIG_VIDEO_BMP_GZIP */
if (bmp == NULL) {
printf("There is no valid bmp file at the given address\n");
return(1);
#endif /* CONFIG_VIDEO_BMP_GZIP */
return 1;
}
printf("Image size : %d x %d\n", le32_to_cpu(bmp->header.width),
le32_to_cpu(bmp->header.height));
printf("Bits per pixel: %d\n", le16_to_cpu(bmp->header.bit_count));
printf("Compression : %d\n", le32_to_cpu(bmp->header.compression));
#ifdef CONFIG_VIDEO_BMP_GZIP
if (dst) {
free(dst);
}
#endif /* CONFIG_VIDEO_BMP_GZIP */
if ((unsigned long)bmp != addr)
free(bmp);
return(0);
}
@ -174,14 +191,33 @@ static int bmp_info(ulong addr)
*/
static int bmp_display(ulong addr, int x, int y)
{
int ret;
bmp_image_t *bmp = (bmp_image_t *)addr;
unsigned long len;
if (!((bmp->header.signature[0]=='B') &&
(bmp->header.signature[1]=='M')))
bmp = gunzip_bmp(addr, &len);
if (!bmp) {
printf("There is no valid bmp file at the given address\n");
return 1;
}
#if defined(CONFIG_LCD)
extern int lcd_display_bitmap (ulong, int, int);
return (lcd_display_bitmap (addr, x, y));
ret = lcd_display_bitmap ((unsigned long)bmp, x, y);
#elif defined(CONFIG_VIDEO)
extern int video_display_bitmap (ulong, int, int);
return (video_display_bitmap (addr, x, y));
ret = video_display_bitmap ((unsigned long)bmp, x, y);
#else
# error bmp_display() requires CONFIG_LCD or CONFIG_VIDEO
#endif
if ((unsigned long)bmp != addr)
free(bmp);
return ret;
}

26
common/cmd_fdt.c
View File

@ -184,23 +184,28 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
} else if (argv[1][0] == 's') {
char *pathp; /* path */
char *prop; /* property */
char *newval; /* value from the user (as a string) */
int nodeoffset; /* node offset from libfdt */
static char data[SCRATCHPAD]; /* storage for the property */
int len; /* new length of the property */
int ret; /* return value */
/*
* Parameters: Node path, property, value.
* Parameters: Node path, property, optional value.
*/
if (argc < 5) {
if (argc < 4) {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
pathp = argv[2];
prop = argv[3];
newval = argv[4];
if (argc == 4) {
len = 0;
} else {
ret = fdt_parse_prop(pathp, prop, argv[4], data, &len);
if (ret != 0)
return ret;
}
nodeoffset = fdt_path_offset (fdt, pathp);
if (nodeoffset < 0) {
@ -211,9 +216,6 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
fdt_strerror(nodeoffset));
return 1;
}
ret = fdt_parse_prop(pathp, prop, newval, data, &len);
if (ret != 0)
return ret;
ret = fdt_setprop(fdt, nodeoffset, prop, data, len);
if (ret < 0) {
@ -681,7 +683,7 @@ U_BOOT_CMD(
#ifdef CONFIG_OF_BOARD_SETUP
"fdt boardsetup - Do board-specific set up\n"
#endif
"fdt move <fdt> <newaddr> <length> - Copy the fdt to <addr>\n"
"fdt move <fdt> <newaddr> <length> - Copy the fdt to <addr> and make it active\n"
"fdt print <path> [<prop>] - Recursive print starting at <path>\n"
"fdt list <path> [<prop>] - Print one level starting at <path>\n"
"fdt set <path> <prop> [<val>] - Set <property> [to <val>]\n"
@ -694,10 +696,6 @@ U_BOOT_CMD(
#ifdef CONFIG_OF_HAS_BD_T
"fdt bd_t - Add/replace the /bd_t branch in the tree\n"
#endif
"Hints:\n"
" If the property you are setting/printing has a '#' character or spaces,\n"
" you MUST escape it with a \\ character or quote it with \".\n"
"Examples: fdt print / # print the whole tree\n"
" fdt print /cpus \"#address-cells\"\n"
" fdt set /cpus \"#address-cells\" \"[00 00 00 01]\"\n"
"NOTE: If the path or property you are setting/printing has a '#' character\n"
" or spaces, you MUST escape it with a \\ character or quote it with \".\n"
);

39
common/cmd_fpga.c
View File

@ -58,14 +58,11 @@ static int fpga_get_op (char *opstr);
/* Convert bitstream data and load into the fpga */
int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
{
#if (CONFIG_FPGA & CFG_FPGA_XILINX)
#if defined(CONFIG_FPGA_XILINX)
unsigned int length;
unsigned char* swapdata;
unsigned int swapsize;
char buffer[80];
unsigned char *ptr;
unsigned char *dataptr;
unsigned char data;
unsigned int i;
int rc;
@ -143,39 +140,7 @@ int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
dataptr+=4;
printf(" bytes in bitstream = %d\n", swapsize);
/* check consistency of length obtained */
if (swapsize >= size) {
printf("%s: Could not find right length of data in bitstream\n",
__FUNCTION__);
return FPGA_FAIL;
}
/* allocate memory */
swapdata = (unsigned char *)malloc(swapsize);
if (swapdata == NULL) {
printf("%s: Could not allocate %d bytes memory !\n",
__FUNCTION__, swapsize);
return FPGA_FAIL;
}
/* read data into memory and swap bits */
ptr = swapdata;
for (i = 0; i < swapsize; i++) {
data = 0x00;
data |= (*dataptr & 0x01) << 7;
data |= (*dataptr & 0x02) << 5;
data |= (*dataptr & 0x04) << 3;
data |= (*dataptr & 0x08) << 1;
data |= (*dataptr & 0x10) >> 1;
data |= (*dataptr & 0x20) >> 3;
data |= (*dataptr & 0x40) >> 5;
data |= (*dataptr & 0x80) >> 7;
*ptr++ = data;
dataptr++;
}
rc = fpga_load(dev, swapdata, swapsize);
free(swapdata);
rc = fpga_load(dev, dataptr, swapsize);
return rc;
#else
printf("Bitstream support only for Xilinx devices\n");

9
common/cmd_jffs2.c
View File

@ -167,10 +167,19 @@ struct list_head devices;
static struct mtd_device *current_dev = NULL;
static u8 current_partnum = 0;
#if defined(CONFIG_CMD_CRAMFS)
extern int cramfs_check (struct part_info *info);
extern int cramfs_load (char *loadoffset, struct part_info *info, char *filename);
extern int cramfs_ls (struct part_info *info, char *filename);
extern int cramfs_info (struct part_info *info);
#else
/* defining empty macros for function names is ugly but avoids ifdef clutter
* all over the code */
#define cramfs_check(x) (0)
#define cramfs_load(x,y,z) (-1)
#define cramfs_ls(x,y) (0)
#define cramfs_info(x) (0)
#endif
static struct part_info* jffs2_part_info(struct mtd_device *dev, unsigned int part_num);

8
common/cmd_nand.c
View File

@ -347,6 +347,14 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
opts.quiet = quiet;
ret = nand_write_opts(nand, &opts);
}
} else if (s != NULL && !strcmp(s, ".oob")) {
/* read out-of-band data */
if (read)
ret = nand->read_oob(nand, off, size, &size,
(u_char *) addr);
else
ret = nand->write_oob(nand, off, size, &size,
(u_char *) addr);
} else {
if (read)
ret = nand_read(nand, off, &size, (u_char *)addr);

102
common/cmd_terminal.c Normal file
View File

@ -0,0 +1,102 @@
/*
* (C) Copyright 2007 OpenMoko, Inc.
* Written by Harald Welte <laforge@openmoko.org>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Boot support
*/
#include <common.h>
#include <command.h>
#include <devices.h>
#if defined(CONFIG_CMD_TERMINAL)
int do_terminal(cmd_tbl_t * cmd, int flag, int argc, char *argv[])
{
int i, l;
int last_tilde = 0;
device_t *dev = NULL;
if (argc < 1)
return -1;
/* Scan for selected output/input device */
for (i = 1; i <= ListNumItems (devlist); i++) {
device_t *tmp = ListGetPtrToItem (devlist, i);
if (!strcmp(tmp->name, argv[1])) {
dev = tmp;
break;
}
}
if (!dev)
return -1;
serial_reinit_all();
printf("Entering terminal mode for port %s\n", dev->name);
puts("Use '~.' to leave the terminal and get back to u-boot\n");
while (1) {
int c;
/* read from console and display on serial port */
if (stdio_devices[0]->tstc()) {
c = stdio_devices[0]->getc();
if (last_tilde == 1) {
if (c == '.') {
putc(c);
putc('\n');
break;
} else {
last_tilde = 0;
/* write the delayed tilde */
dev->putc('~');
/* fall-through to print current
* character */
}
}
if (c == '~') {
last_tilde = 1;
puts("[u-boot]");
putc(c);
}
dev->putc(c);
}
/* read from serial port and display on console */
if (dev->tstc()) {
c = dev->getc();
putc(c);
}
}
return 0;
}
/***************************************************/
U_BOOT_CMD(
terminal, 3, 1, do_terminal,
"terminal - start terminal emulator\n",
""
);
#endif /* CONFIG_CMD_TERMINAL */

4
common/cyclon2.c
View File

@ -27,7 +27,7 @@
#include <altera.h>
#include <ACEX1K.h> /* ACEX device family */
#if (CONFIG_FPGA & (CFG_ALTERA | CFG_CYCLON2))
#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA) && defined(CONFIG_FPGA_CYCLON2)
/* Define FPGA_DEBUG to get debug printf's */
#ifdef FPGA_DEBUG
@ -302,4 +302,4 @@ static int CYC2_ps_reloc (Altera_desc * desc, ulong reloc_offset)
return ret_val;
}
#endif /* (CONFIG_FPGA & (CFG_ALTERA | CFG_CYCLON2)) */
#endif /* CONFIG_FPGA && CONFIG_FPGA_ALTERA && CONFIG_FPGA_CYCLON2 */

4
common/env_onenand.c
View File

@ -64,7 +64,7 @@ void env_relocate_spec(void)
DECLARE_GLOBAL_DATA_PTR;
unsigned long env_addr;
int use_default = 0;
int retlen;
size_t retlen;
env_addr = CFG_ENV_ADDR;
env_addr -= (unsigned long)onenand_chip.base;
@ -96,7 +96,7 @@ int saveenv(void)
{
unsigned long env_addr = CFG_ENV_ADDR;
struct erase_info instr;
int retlen;
size_t retlen;
instr.len = CFG_ENV_SIZE;
instr.addr = env_addr;

73
common/fdt_support.c
View File

@ -111,6 +111,7 @@ int fdt_chosen(void *fdt, ulong initrd_start, ulong initrd_end, int force)
int err;
u32 tmp; /* used to set 32 bit integer properties */
char *str; /* used to set string properties */
const char *path;
err = fdt_check_header(fdt);
if (err < 0) {
@ -148,14 +149,7 @@ int fdt_chosen(void *fdt, ulong initrd_start, ulong initrd_end, int force)
nodeoffset = fdt_path_offset (fdt, "/chosen");
/*
* If we have a "chosen" node already the "force the writing"
* is not set, our job is done.
*/
if ((nodeoffset >= 0) && !force)
return 0;
/*
* No "chosen" node in the blob: create it.
* If there is no "chosen" node in the blob, create it.
*/
if (nodeoffset < 0) {
/*
@ -170,42 +164,55 @@ int fdt_chosen(void *fdt, ulong initrd_start, ulong initrd_end, int force)
}
/*
* Update pre-existing properties, create them if non-existant.
* Create /chosen properites that don't exist in the fdt.
* If the property exists, update it only if the "force" parameter
* is true.
*/
str = getenv("bootargs");
if (str != NULL) {
err = fdt_setprop(fdt, nodeoffset,
"bootargs", str, strlen(str)+1);
if (err < 0)
printf("WARNING: could not set bootargs %s.\n",
fdt_strerror(err));
path = fdt_getprop(fdt, nodeoffset, "bootargs", NULL);
if ((path == NULL) || force) {
err = fdt_setprop(fdt, nodeoffset,
"bootargs", str, strlen(str)+1);
if (err < 0)
printf("WARNING: could not set bootargs %s.\n",
fdt_strerror(err));
}
}
if (initrd_start && initrd_end) {
tmp = __cpu_to_be32(initrd_start);
err = fdt_setprop(fdt, nodeoffset,
"linux,initrd-start", &tmp, sizeof(tmp));
if (err < 0)
printf("WARNING: "
"could not set linux,initrd-start %s.\n",
fdt_strerror(err));
tmp = __cpu_to_be32(initrd_end);
err = fdt_setprop(fdt, nodeoffset,
"linux,initrd-end", &tmp, sizeof(tmp));
if (err < 0)
printf("WARNING: could not set linux,initrd-end %s.\n",
fdt_strerror(err));
path = fdt_getprop(fdt, nodeoffset, "linux,initrd-start", NULL);
if ((path == NULL) || force) {
tmp = __cpu_to_be32(initrd_start);
err = fdt_setprop(fdt, nodeoffset,
"linux,initrd-start", &tmp, sizeof(tmp));
if (err < 0)
printf("WARNING: "
"could not set linux,initrd-start %s.\n",
fdt_strerror(err));
tmp = __cpu_to_be32(initrd_end);
err = fdt_setprop(fdt, nodeoffset,
"linux,initrd-end", &tmp, sizeof(tmp));
if (err < 0)
printf("WARNING: could not set linux,initrd-end %s.\n",
fdt_strerror(err));
}
}
#ifdef CONFIG_OF_STDOUT_VIA_ALIAS
err = fdt_fixup_stdout(fdt, nodeoffset);
path = fdt_getprop(fdt, nodeoffset, "linux,stdout-path", NULL);
if ((path == NULL) || force)
err = fdt_fixup_stdout(fdt, nodeoffset);
#endif
#ifdef OF_STDOUT_PATH
err = fdt_setprop(fdt, nodeoffset,
"linux,stdout-path", OF_STDOUT_PATH, strlen(OF_STDOUT_PATH)+1);
if (err < 0)
printf("WARNING: could not set linux,stdout-path %s.\n",
fdt_strerror(err));
path = fdt_getprop(fdt, nodeoffset, "linux,stdout-path", NULL);
if ((path == NULL) || force) {
err = fdt_setprop(fdt, nodeoffset,
"linux,stdout-path", OF_STDOUT_PATH, strlen(OF_STDOUT_PATH)+1);
if (err < 0)
printf("WARNING: could not set linux,stdout-path %s.\n",
fdt_strerror(err));
}
#endif
return err;

30
common/fpga.c
View File

@ -67,14 +67,11 @@ static int fpga_dev_info( int devnum );
static void fpga_no_sup( char *fn, char *msg )
{
if ( fn && msg ) {
printf( "%s: No support for %s. CONFIG_FPGA defined as 0x%x.\n",
fn, msg, CONFIG_FPGA );
printf( "%s: No support for %s.\n", fn, msg);
} else if ( msg ) {
printf( "No support for %s. CONFIG_FPGA defined as 0x%x.\n",
msg, CONFIG_FPGA );
printf( "No support for %s.\n", msg);
} else {
printf( "No FPGA suport! CONFIG_FPGA defined as 0x%x.\n",
CONFIG_FPGA );
printf( "No FPGA suport!\n");
}
}
@ -112,11 +109,6 @@ static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_va
printf( "%s: Null buffer.\n", fn );
return (fpga_desc * const)NULL;
}
if ( !bsize ) {
printf( "%s: Null buffer size.\n", fn );
return (fpga_desc * const)NULL;
}
return desc;
}
@ -135,7 +127,7 @@ static int fpga_dev_info( int devnum )
switch ( desc->devtype ) {
case fpga_xilinx:
#if CONFIG_FPGA & CFG_FPGA_XILINX
#if defined(CONFIG_FPGA_XILINX)
printf( "Xilinx Device\nDescriptor @ 0x%p\n", desc );
ret_val = xilinx_info( desc->devdesc );
#else
@ -143,7 +135,7 @@ static int fpga_dev_info( int devnum )
#endif
break;
case fpga_altera:
#if CONFIG_FPGA & CFG_FPGA_ALTERA
#if defined(CONFIG_FPGA_ALTERA)
printf( "Altera Device\nDescriptor @ 0x%p\n", desc );
ret_val = altera_info( desc->devdesc );
#else
@ -175,14 +167,14 @@ int fpga_reloc( fpga_type devtype, void *desc, ulong reloc_off )
switch ( devtype ) {
case fpga_xilinx:
#if CONFIG_FPGA & CFG_FPGA_XILINX
#if defined(CONFIG_FPGA_XILINX)
ret_val = xilinx_reloc( desc, reloc_off );
#else
fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" );
#endif
break;
case fpga_altera:
#if CONFIG_FPGA & CFG_FPGA_ALTERA
#if defined(CONFIG_FPGA_ALTERA)
ret_val = altera_reloc( desc, reloc_off );
#else
fpga_no_sup( (char *)__FUNCTION__, "Altera devices" );
@ -268,14 +260,14 @@ int fpga_load( int devnum, void *buf, size_t bsize )
if ( desc ) {
switch ( desc->devtype ) {
case fpga_xilinx:
#if CONFIG_FPGA & CFG_FPGA_XILINX
#if defined(CONFIG_FPGA_XILINX)
ret_val = xilinx_load( desc->devdesc, buf, bsize );
#else
fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" );
#endif
break;
case fpga_altera:
#if CONFIG_FPGA & CFG_FPGA_ALTERA
#if defined(CONFIG_FPGA_ALTERA)
ret_val = altera_load( desc->devdesc, buf, bsize );
#else
fpga_no_sup( (char *)__FUNCTION__, "Altera devices" );
@ -301,14 +293,14 @@ int fpga_dump( int devnum, void *buf, size_t bsize )
if ( desc ) {
switch ( desc->devtype ) {
case fpga_xilinx:
#if CONFIG_FPGA & CFG_FPGA_XILINX
#if defined(CONFIG_FPGA_XILINX)
ret_val = xilinx_dump( desc->devdesc, buf, bsize );
#else
fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" );
#endif
break;
case fpga_altera:
#if CONFIG_FPGA & CFG_FPGA_ALTERA
#if defined(CONFIG_FPGA_ALTERA)
ret_val = altera_dump( desc->devdesc, buf, bsize );
#else
fpga_no_sup( (char *)__FUNCTION__, "Altera devices" );

26
common/main.c
View File

@ -696,7 +696,7 @@ static void cread_add_str(char *str, int strsize, int insert, unsigned long *num
}
}
static int cread_line(char *buf, unsigned int *len)
static int cread_line(const char *const prompt, char *buf, unsigned int *len)
{
unsigned long num = 0;
unsigned long eol_num = 0;
@ -818,6 +818,7 @@ static int cread_line(char *buf, unsigned int *len)
insert = !insert;
break;
case CTL_CH('x'):
case CTL_CH('u'):
BEGINNING_OF_LINE();
ERASE_TO_EOL();
break;
@ -867,6 +868,27 @@ static int cread_line(char *buf, unsigned int *len)
REFRESH_TO_EOL();
continue;
}
#ifdef CONFIG_AUTO_COMPLETE
case '\t': {
int num2, col;
/* do not autocomplete when in the middle */
if (num < eol_num) {
getcmd_cbeep();
break;
}
buf[num] = '\0';
col = strlen(prompt) + eol_num;
num2 = num;
if (cmd_auto_complete(prompt, buf, &num2, &col)) {
col = num2 - num;
num += col;
eol_num += col;
}
break;
}
#endif
default:
cread_add_char(ichar, insert, &num, &eol_num, buf, *len);
break;
@ -909,7 +931,7 @@ int readline (const char *const prompt)
puts (prompt);
rc = cread_line(p, &len);
rc = cread_line(prompt, p, &len);
return rc < 0 ? rc : len;
#else
char *p = console_buffer;

4
common/serial.c
View File

@ -33,7 +33,7 @@ static struct serial_device *serial_devices = NULL;
static struct serial_device *serial_current = NULL;
#if !defined(CONFIG_LWMON) && !defined(CONFIG_PXA27X)
struct serial_device *default_serial_console (void)
struct serial_device *__default_serial_console (void)
{
#if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2)
return &serial_smc_device;
@ -64,6 +64,8 @@ struct serial_device *default_serial_console (void)
#error No default console
#endif
}
struct serial_device *default_serial_console(void) __attribute__((weak, alias("__default_serial_console")));
#endif
int serial_register (struct serial_device *dev)

22
common/spartan2.c
View File

@ -25,7 +25,7 @@
#include <common.h> /* core U-Boot definitions */
#include <spartan2.h> /* Spartan-II device family */
#if (CONFIG_FPGA & (CFG_XILINX | CFG_SPARTAN2))
#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_SPARTAN2)
/* Define FPGA_DEBUG to get debug printf's */
#ifdef FPGA_DEBUG
@ -441,7 +441,7 @@ static int Spartan2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
int ret_val = FPGA_FAIL; /* assume the worst */
Xilinx_Spartan2_Slave_Serial_fns *fn = desc->iface_fns;
int i;
char val;
unsigned char val;
PRINTF ("%s: start with interface functions @ 0x%p\n",
__FUNCTION__, fn);
@ -561,6 +561,13 @@ static int Spartan2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
}
putc ('\n'); /* terminate the dotted line */
/*
* Run the post configuration function if there is one.
*/
if (*fn->post) {
(*fn->post) (cookie);
}
#ifdef CFG_FPGA_PROG_FEEDBACK
if (ret_val == FPGA_SUCCESS) {
puts ("Done.\n");
@ -615,8 +622,10 @@ static int Spartan2_ss_reloc (Xilinx_desc * desc, ulong reloc_offset)
PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__,
desc);
addr = (ulong) (fn->pre) + reloc_offset;
fn_r->pre = (Xilinx_pre_fn) addr;
if (fn->pre) {
addr = (ulong) (fn->pre) + reloc_offset;
fn_r->pre = (Xilinx_pre_fn) addr;
}
addr = (ulong) (fn->pgm) + reloc_offset;
fn_r->pgm = (Xilinx_pgm_fn) addr;
@ -633,6 +642,11 @@ static int Spartan2_ss_reloc (Xilinx_desc * desc, ulong reloc_offset)
addr = (ulong) (fn->wr) + reloc_offset;
fn_r->wr = (Xilinx_wr_fn) addr;
if (fn->post) {
addr = (ulong) (fn->post) + reloc_offset;
fn_r->post = (Xilinx_post_fn) addr;
}
fn_r->relocated = TRUE;
} else {

22
common/spartan3.c
View File

@ -30,7 +30,7 @@
#include <common.h> /* core U-Boot definitions */
#include <spartan3.h> /* Spartan-II device family */
#if (CONFIG_FPGA & (CFG_XILINX | CFG_SPARTAN3))
#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_SPARTAN3)
/* Define FPGA_DEBUG to get debug printf's */
#ifdef FPGA_DEBUG
@ -446,7 +446,7 @@ static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
int ret_val = FPGA_FAIL; /* assume the worst */
Xilinx_Spartan3_Slave_Serial_fns *fn = desc->iface_fns;
int i;
char val;
unsigned char val;
PRINTF ("%s: start with interface functions @ 0x%p\n",
__FUNCTION__, fn);
@ -566,6 +566,13 @@ static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
}
putc ('\n'); /* terminate the dotted line */
/*
* Run the post configuration function if there is one.
*/
if (*fn->post) {
(*fn->post) (cookie);
}
#ifdef CFG_FPGA_PROG_FEEDBACK
if (ret_val == FPGA_SUCCESS) {
puts ("Done.\n");
@ -620,8 +627,10 @@ static int Spartan3_ss_reloc (Xilinx_desc * desc, ulong reloc_offset)
PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__,
desc);
addr = (ulong) (fn->pre) + reloc_offset;
fn_r->pre = (Xilinx_pre_fn) addr;
if (fn->pre) {
addr = (ulong) (fn->pre) + reloc_offset;
fn_r->pre = (Xilinx_pre_fn) addr;
}
addr = (ulong) (fn->pgm) + reloc_offset;
fn_r->pgm = (Xilinx_pgm_fn) addr;
@ -638,6 +647,11 @@ static int Spartan3_ss_reloc (Xilinx_desc * desc, ulong reloc_offset)
addr = (ulong) (fn->wr) + reloc_offset;
fn_r->wr = (Xilinx_wr_fn) addr;
if (fn->post) {
addr = (ulong) (fn->post) + reloc_offset;
fn_r->post = (Xilinx_post_fn) addr;
}
fn_r->relocated = TRUE;
} else {

2
common/virtex2.c
View File

@ -31,7 +31,7 @@
#include <common.h>
#include <virtex2.h>
#if (CONFIG_FPGA & (CFG_XILINX | CFG_VIRTEX2))
#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_VIRTEX2)
#if 0
#define FPGA_DEBUG

28
common/xilinx.c
View File

@ -32,7 +32,7 @@
#include <spartan2.h>
#include <spartan3.h>
#if (CONFIG_FPGA & CFG_FPGA_XILINX)
#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_XILINX)
#if 0
#define FPGA_DEBUG
@ -59,7 +59,7 @@ int xilinx_load (Xilinx_desc * desc, void *buf, size_t bsize)
} else
switch (desc->family) {
case Xilinx_Spartan2:
#if (CONFIG_FPGA & CFG_SPARTAN2)
#if defined(CONFIG_FPGA_SPARTAN2)
PRINTF ("%s: Launching the Spartan-II Loader...\n",
__FUNCTION__);
ret_val = Spartan2_load (desc, buf, bsize);
@ -69,7 +69,7 @@ int xilinx_load (Xilinx_desc * desc, void *buf, size_t bsize)
#endif
break;
case Xilinx_Spartan3:
#if (CONFIG_FPGA & CFG_SPARTAN3)
#if defined(CONFIG_FPGA_SPARTAN3)
PRINTF ("%s: Launching the Spartan-III Loader...\n",
__FUNCTION__);
ret_val = Spartan3_load (desc, buf, bsize);
@ -79,7 +79,7 @@ int xilinx_load (Xilinx_desc * desc, void *buf, size_t bsize)
#endif
break;
case Xilinx_Virtex2:
#if (CONFIG_FPGA & CFG_VIRTEX2)
#if defined(CONFIG_FPGA_VIRTEX2)
PRINTF ("%s: Launching the Virtex-II Loader...\n",
__FUNCTION__);
ret_val = Virtex2_load (desc, buf, bsize);
@ -106,7 +106,7 @@ int xilinx_dump (Xilinx_desc * desc, void *buf, size_t bsize)
} else
switch (desc->family) {
case Xilinx_Spartan2:
#if (CONFIG_FPGA & CFG_SPARTAN2)
#if defined(CONFIG_FPGA_SPARTAN2)
PRINTF ("%s: Launching the Spartan-II Reader...\n",
__FUNCTION__);
ret_val = Spartan2_dump (desc, buf, bsize);
@ -116,7 +116,7 @@ int xilinx_dump (Xilinx_desc * desc, void *buf, size_t bsize)
#endif
break;
case Xilinx_Spartan3:
#if (CONFIG_FPGA & CFG_SPARTAN3)
#if defined(CONFIG_FPGA_SPARTAN3)
PRINTF ("%s: Launching the Spartan-III Reader...\n",
__FUNCTION__);
ret_val = Spartan3_dump (desc, buf, bsize);
@ -126,7 +126,7 @@ int xilinx_dump (Xilinx_desc * desc, void *buf, size_t bsize)
#endif
break;
case Xilinx_Virtex2:
#if (CONFIG_FPGA & CFG_VIRTEX2)
#if defined( CONFIG_FPGA_VIRTEX2)
PRINTF ("%s: Launching the Virtex-II Reader...\n",
__FUNCTION__);
ret_val = Virtex2_dump (desc, buf, bsize);
@ -198,7 +198,7 @@ int xilinx_info (Xilinx_desc * desc)
printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
switch (desc->family) {
case Xilinx_Spartan2:
#if (CONFIG_FPGA & CFG_SPARTAN2)
#if defined(CONFIG_FPGA_SPARTAN2)
Spartan2_info (desc);
#else
/* just in case */
@ -207,7 +207,7 @@ int xilinx_info (Xilinx_desc * desc)
#endif
break;
case Xilinx_Spartan3:
#if (CONFIG_FPGA & CFG_SPARTAN3)
#if defined(CONFIG_FPGA_SPARTAN3)
Spartan3_info (desc);
#else
/* just in case */
@ -216,7 +216,7 @@ int xilinx_info (Xilinx_desc * desc)
#endif
break;
case Xilinx_Virtex2:
#if (CONFIG_FPGA & CFG_VIRTEX2)
#if defined(CONFIG_FPGA_VIRTEX2)
Virtex2_info (desc);
#else
/* just in case */
@ -249,7 +249,7 @@ int xilinx_reloc (Xilinx_desc * desc, ulong reloc_offset)
} else
switch (desc->family) {
case Xilinx_Spartan2:
#if (CONFIG_FPGA & CFG_SPARTAN2)
#if defined(CONFIG_FPGA_SPARTAN2)
ret_val = Spartan2_reloc (desc, reloc_offset);
#else
printf ("%s: No support for Spartan-II devices.\n",
@ -257,7 +257,7 @@ int xilinx_reloc (Xilinx_desc * desc, ulong reloc_offset)
#endif
break;
case Xilinx_Spartan3:
#if (CONFIG_FPGA & CFG_SPARTAN3)
#if defined(CONFIG_FPGA_SPARTAN3)
ret_val = Spartan3_reloc (desc, reloc_offset);
#else
printf ("%s: No support for Spartan-III devices.\n",
@ -265,7 +265,7 @@ int xilinx_reloc (Xilinx_desc * desc, ulong reloc_offset)
#endif
break;
case Xilinx_Virtex2:
#if (CONFIG_FPGA & CFG_VIRTEX2)
#if defined(CONFIG_FPGA_VIRTEX2)
ret_val = Virtex2_reloc (desc, reloc_offset);
#else
printf ("%s: No support for Virtex-II devices.\n",
@ -308,4 +308,4 @@ static int xilinx_validate (Xilinx_desc * desc, char *fn)
return ret_val;
}
#endif /* CONFIG_FPGA & CFG_FPGA_XILINX */
#endif /* CONFIG_FPGA && CONFIG_FPGA_XILINX */

22
cpu/ixp/serial.c
View File

@ -31,6 +31,13 @@
#include <common.h>
#include <asm/arch/ixp425.h>
/*
* 14.7456 MHz
* Baud Rate = --------------
* 16 x Divisor
*/
#define SERIAL_CLOCK 921600
DECLARE_GLOBAL_DATA_PTR;
void serial_setbrg (void)
@ -38,18 +45,8 @@ void serial_setbrg (void)
unsigned int quot = 0;
int uart = CFG_IXP425_CONSOLE;
if (gd->baudrate == 1200)
quot = 192;
else if (gd->baudrate == 9600)
quot = 96;
else if (gd->baudrate == 19200)
quot = 48;
else if (gd->baudrate == 38400)
quot = 24;
else if (gd->baudrate == 57600)
quot = 16;
else if (gd->baudrate == 115200)
quot = 8;
if ((gd->baudrate <= SERIAL_CLOCK) && (SERIAL_CLOCK % gd->baudrate == 0))
quot = SERIAL_CLOCK / gd->baudrate;
else
hang ();
@ -65,7 +62,6 @@ void serial_setbrg (void)
IER(uart) = IER_UUE;
}
/*
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.

2
cpu/mpc83xx/Makefile
View File

@ -29,7 +29,7 @@ LIB = $(obj)lib$(CPU).a
START = start.o
COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \
spd_sdram.o ecc.o qe_io.o pci.o
spd_sdram.o ecc.o qe_io.o pci.o fdt.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))

348
cpu/mpc83xx/cpu.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -31,12 +31,7 @@
#include <command.h>
#include <mpc83xx.h>
#include <asm/processor.h>
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#elif defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#include <fdt_support.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
@ -65,6 +60,10 @@ int checkcpu(void)
printf("e300c3, ");
break;
case PVR_E300C4:
printf("e300c4, ");
break;
default:
printf("Unknown core, ");
}
@ -149,6 +148,36 @@ int checkcpu(void)
case SPR_8313E_REV10:
puts("MPC8313E, ");
break;
case SPR_8315E_REV10:
puts("MPC8315E, ");
break;
case SPR_8315_REV10:
puts("MPC8315, ");
break;
case SPR_8314E_REV10:
puts("MPC8314E, ");
break;
case SPR_8314_REV10:
puts("MPC8314, ");
break;
case SPR_8379E_REV10:
puts("MPC8379E, ");
break;
case SPR_8379_REV10:
puts("MPC8379, ");
break;
case SPR_8378E_REV10:
puts("MPC8378E, ");
break;
case SPR_8378_REV10:
puts("MPC8378, ");
break;
case SPR_8377E_REV10:
puts("MPC8377E, ");
break;
case SPR_8377_REV10:
puts("MPC8377, ");
break;
default:
printf("Rev: Unknown revision number:%08x\n"
"Warning: Unsupported cpu revision!\n",spridr);
@ -325,313 +354,6 @@ void watchdog_reset (void)
}
#endif
#if defined(CONFIG_OF_LIBFDT)
/*
* "Setter" functions used to add/modify FDT entries.
*/
static int fdt_set_eth0(void *blob, int nodeoffset, const char *name, bd_t *bd)
{
/* Fix it up if it exists, don't create it if it doesn't exist */
if (fdt_get_property(blob, nodeoffset, name, 0)) {
return fdt_setprop(blob, nodeoffset, name, bd->bi_enetaddr, 6);
}
return 0;
}
#ifdef CONFIG_HAS_ETH1
/* second onboard ethernet port */
static int fdt_set_eth1(void *blob, int nodeoffset, const char *name, bd_t *bd)
{
/* Fix it up if it exists, don't create it if it doesn't exist */
if (fdt_get_property(blob, nodeoffset, name, 0)) {
return fdt_setprop(blob, nodeoffset, name, bd->bi_enet1addr, 6);
}
return 0;
}
#endif
#ifdef CONFIG_HAS_ETH2
/* third onboard ethernet port */
static int fdt_set_eth2(void *blob, int nodeoffset, const char *name, bd_t *bd)
{
/* Fix it up if it exists, don't create it if it doesn't exist */
if (fdt_get_property(blob, nodeoffset, name, 0)) {
return fdt_setprop(blob, nodeoffset, name, bd->bi_enet2addr, 6);
}
return 0;
}
#endif
#ifdef CONFIG_HAS_ETH3
/* fourth onboard ethernet port */
static int fdt_set_eth3(void *blob, int nodeoffset, const char *name, bd_t *bd)
{
/* Fix it up if it exists, don't create it if it doesn't exist */
if (fdt_get_property(blob, nodeoffset, name, 0)) {
return fdt_setprop(blob, nodeoffset, name, bd->bi_enet3addr, 6);
}
return 0;
}
#endif
static int fdt_set_busfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
{
u32 tmp;
/* Create or update the property */
tmp = cpu_to_be32(bd->bi_busfreq);
return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
}
static int fdt_set_tbfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
{
u32 tmp;
/* Create or update the property */
tmp = cpu_to_be32(OF_TBCLK);
return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
}
static int fdt_set_clockfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
{
u32 tmp;
/* Create or update the property */
tmp = cpu_to_be32(gd->core_clk);
return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
}
#ifdef CONFIG_QE
static int fdt_set_qe_busfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
{
u32 tmp;
/* Create or update the property */
tmp = cpu_to_be32(gd->qe_clk);
return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
}
static int fdt_set_qe_brgfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
{
u32 tmp;
/* Create or update the property */
tmp = cpu_to_be32(gd->brg_clk);
return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
}
#endif
/*
* Fixups to the fdt.
*/
static const struct {
char *node;
char *prop;
int (*set_fn)(void *blob, int nodeoffset, const char *name, bd_t *bd);
} fixup_props[] = {
{ "/cpus/" OF_CPU,
"timebase-frequency",
fdt_set_tbfreq
},
{ "/cpus/" OF_CPU,
"bus-frequency",
fdt_set_busfreq
},
{ "/cpus/" OF_CPU,
"clock-frequency",
fdt_set_clockfreq
},
{ "/" OF_SOC,
"bus-frequency",
fdt_set_busfreq
},
{ "/" OF_SOC "/serial@4500",
"clock-frequency",
fdt_set_busfreq
},
{ "/" OF_SOC "/serial@4600",
"clock-frequency",
fdt_set_busfreq
},
#ifdef CONFIG_TSEC1
{ "/" OF_SOC "/ethernet@24000",
"mac-address",
fdt_set_eth0
},
{ "/" OF_SOC "/ethernet@24000",
"local-mac-address",
fdt_set_eth0
},
#endif
#ifdef CONFIG_TSEC2
{ "/" OF_SOC "/ethernet@25000",
"mac-address",
fdt_set_eth1
},
{ "/" OF_SOC "/ethernet@25000",
"local-mac-address",
fdt_set_eth1
},
#endif
#ifdef CONFIG_QE
{ "/" OF_QE,
"brg-frequency",
fdt_set_qe_brgfreq
},
{ "/" OF_QE,
"bus-frequency",
fdt_set_qe_busfreq
},
#ifdef CONFIG_UEC_ETH1
#if CFG_UEC1_UCC_NUM == 0 /* UCC1 */
{ "/" OF_QE "/ucc@2000",
"mac-address",
fdt_set_eth0
},
{ "/" OF_QE "/ucc@2000",
"local-mac-address",
fdt_set_eth0
},
#elif CFG_UEC1_UCC_NUM == 2 /* UCC3 */
{ "/" OF_QE "/ucc@2200",
"mac-address",
fdt_set_eth0
},
{ "/" OF_QE "/ucc@2200",
"local-mac-address",
fdt_set_eth0
},
#endif
#endif /* CONFIG_UEC_ETH1 */
#ifdef CONFIG_UEC_ETH2
#if CFG_UEC2_UCC_NUM == 1 /* UCC2 */
{ "/" OF_QE "/ucc@3000",
"mac-address",
fdt_set_eth1
},
{ "/" OF_QE "/ucc@3000",
"local-mac-address",
fdt_set_eth1
},
#elif CFG_UEC2_UCC_NUM == 3 /* UCC4 */
{ "/" OF_QE "/ucc@3200",
"mac-address",
fdt_set_eth1
},
{ "/" OF_QE "/ucc@3200",
"local-mac-address",
fdt_set_eth1
},
#endif
#endif /* CONFIG_UEC_ETH2 */
#endif /* CONFIG_QE */
};
void
ft_cpu_setup(void *blob, bd_t *bd)
{
int nodeoffset;
int err;
int j;
for (j = 0; j < (sizeof(fixup_props) / sizeof(fixup_props[0])); j++) {
nodeoffset = fdt_path_offset(blob, fixup_props[j].node);
if (nodeoffset >= 0) {
err = fixup_props[j].set_fn(blob, nodeoffset,
fixup_props[j].prop, bd);
if (err < 0)
debug("Problem setting %s = %s: %s\n",
fixup_props[j].node, fixup_props[j].prop,
fdt_strerror(err));
} else {
debug("Couldn't find %s: %s\n",
fixup_props[j].node, fdt_strerror(nodeoffset));
}
}
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
}
#elif defined(CONFIG_OF_FLAT_TREE)
void
ft_cpu_setup(void *blob, bd_t *bd)
{
u32 *p;
int len;
ulong clock;
clock = bd->bi_busfreq;
p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
if (p != NULL)
*p = cpu_to_be32(clock);
p = ft_get_prop(blob, "/" OF_SOC "/bus-frequency", &len);
if (p != NULL)
*p = cpu_to_be32(clock);
p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
if (p != NULL)
*p = cpu_to_be32(clock);
p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
if (p != NULL)
*p = cpu_to_be32(clock);
#ifdef CONFIG_TSEC1
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
if (p != NULL)
memcpy(p, bd->bi_enetaddr, 6);
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/local-mac-address", &len);
if (p != NULL)
memcpy(p, bd->bi_enetaddr, 6);
#endif
#ifdef CONFIG_TSEC2
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
if (p != NULL)
memcpy(p, bd->bi_enet1addr, 6);
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len);
if (p != NULL)
memcpy(p, bd->bi_enet1addr, 6);
#endif
#ifdef CONFIG_UEC_ETH1
#if CFG_UEC1_UCC_NUM == 0 /* UCC1 */
p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/mac-address", &len);
if (p != NULL)
memcpy(p, bd->bi_enetaddr, 6);
p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/local-mac-address", &len);
if (p != NULL)
memcpy(p, bd->bi_enetaddr, 6);
#elif CFG_UEC1_UCC_NUM == 2 /* UCC3 */
p = ft_get_prop(blob, "/" OF_QE "/ucc@2200/mac-address", &len);
if (p != NULL)
memcpy(p, bd->bi_enetaddr, 6);
p = ft_get_prop(blob, "/" OF_QE "/ucc@2200/local-mac-address", &len);
if (p != NULL)
memcpy(p, bd->bi_enetaddr, 6);
#endif
#endif
#ifdef CONFIG_UEC_ETH2
#if CFG_UEC2_UCC_NUM == 1 /* UCC2 */
p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/mac-address", &len);
if (p != NULL)
memcpy(p, bd->bi_enet1addr, 6);
p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/local-mac-address", &len);
if (p != NULL)
memcpy(p, bd->bi_enet1addr, 6);
#elif CFG_UEC2_UCC_NUM == 3 /* UCC4 */
p = ft_get_prop(blob, "/" OF_QE "/ucc@3200/mac-address", &len);
if (p != NULL)
memcpy(p, bd->bi_enet1addr, 6);
p = ft_get_prop(blob, "/" OF_QE "/ucc@3200/local-mac-address", &len);
if (p != NULL)
memcpy(p, bd->bi_enet1addr, 6);
#endif
#endif
}
#endif
#if defined(CONFIG_DDR_ECC)
void dma_init(void)
{

6
cpu/mpc83xx/cpu_init.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -155,6 +155,10 @@ void cpu_init_f (volatile immap_t * im)
#ifdef CFG_DDRCDR
im->sysconf.ddrcdr = CFG_DDRCDR;
#endif
/* Output buffer impedance register */
#ifdef CFG_OBIR
im->sysconf.obir = CFG_OBIR;
#endif
#ifdef CONFIG_QE
/* Config QE ioports */

72
cpu/mpc83xx/fdt.c Normal file
View File

@ -0,0 +1,72 @@
/*
* Copyright 2007 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#include <fdt_support.h>
DECLARE_GLOBAL_DATA_PTR;
void ft_cpu_setup(void *blob, bd_t *bd)
{
#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
fdt_fixup_ethernet(blob, bd);
#endif
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"timebase-frequency", (bd->bi_busfreq / 4), 1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"bus-frequency", bd->bi_busfreq, 1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"clock-frequency", gd->core_clk, 1);
do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
"bus-frequency", bd->bi_busfreq, 1);
#ifdef CONFIG_QE
do_fixup_by_prop_u32(blob, "device_type", "qe", 4,
"bus-frequency", gd->qe_clk, 1);
do_fixup_by_prop_u32(blob, "device_type", "qe", 4,
"brg-frequency", gd->brg_clk, 1);
#endif
#ifdef CFG_NS16550
do_fixup_by_compat_u32(blob, "ns16550",
"clock-frequency", bd->bi_busfreq, 1);
#endif
#ifdef CONFIG_CPM2
do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart",
"current-speed", bd->bi_baudrate, 1);
do_fixup_by_compat_u32(blob, "fsl,cpm2-brg",
"clock-frequency", bd->bi_brgfreq, 1);
#endif
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
}
#endif /* CONFIG_OF_LIBFDT */

75
cpu/mpc83xx/pci.c
View File

@ -28,8 +28,7 @@
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#elif defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#include <fdt_support.h>
#endif
#include <asm/mpc8349_pci.h>
@ -173,63 +172,41 @@ void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot)
void ft_pci_setup(void *blob, bd_t *bd)
{
int nodeoffset;
int err;
int tmp[2];
const char *path;
if (pci_num_buses < 1)
return;
nodeoffset = fdt_path_offset(blob, "/" OF_SOC "/pci@8500");
nodeoffset = fdt_path_offset(blob, "/aliases");
if (nodeoffset >= 0) {
tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
err = fdt_setprop(blob, nodeoffset, "bus-range",
tmp, sizeof(tmp));
path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
if (path) {
tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
do_fixup_by_path(blob, path, "bus-range",
&tmp, sizeof(tmp), 1);
tmp[0] = cpu_to_be32(gd->pci_clk);
err = fdt_setprop(blob, nodeoffset, "clock-frequency",
tmp, sizeof(tmp[0]));
}
tmp[0] = cpu_to_be32(gd->pci_clk);
do_fixup_by_path(blob, path, "clock-frequency",
&tmp, sizeof(tmp[0]), 1);
}
if (pci_num_buses < 2)
return;
if (pci_num_buses < 2)
return;
nodeoffset = fdt_path_offset(blob, "/" OF_SOC "/pci@8600");
if (nodeoffset >= 0) {
tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
err = fdt_setprop(blob, nodeoffset, "bus-range",
tmp, sizeof(tmp));
path = fdt_getprop(blob, nodeoffset, "pci1", NULL);
if (path) {
tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
do_fixup_by_path(blob, path, "bus-range",
&tmp, sizeof(tmp), 1);
tmp[0] = cpu_to_be32(gd->pci_clk);
err = fdt_setprop(blob, nodeoffset, "clock-frequency",
tmp, sizeof(tmp[0]));
tmp[0] = cpu_to_be32(gd->pci_clk);
do_fixup_by_path(blob, path, "clock-frequency",
&tmp, sizeof(tmp[0]), 1);
}
}
}
#elif CONFIG_OF_FLAT_TREE
void ft_pci_setup(void *blob, bd_t *bd)
{
u32 *p;
int len;
if (pci_num_buses < 1)
return;
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
if (p) {
p[0] = pci_hose[0].first_busno;
p[1] = pci_hose[0].last_busno;
}
if (pci_num_buses < 2)
return;
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len);
if (p) {
p[0] = pci_hose[1].first_busno;
p[1] = pci_hose[1].last_busno;
}
}
#endif /* CONFIG_OF_FLAT_TREE */
#endif /* CONFIG_OF_LIBFDT */
#endif /* CONFIG_83XX_GENERIC_PCI */

7
cpu/mpc83xx/spd_sdram.c
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2006 Freescale Semiconductor, Inc.
* (C) Copyright 2006-2007 Freescale Semiconductor, Inc.
*
* (C) Copyright 2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@ -198,6 +198,7 @@ long int spd_sdram()
if(spd.mem_type == SPD_MEMTYPE_DDR2) {
immap->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
}
udelay(50000);
#endif
/*
@ -576,7 +577,7 @@ long int spd_sdram()
if (effective_data_rate == 266 || effective_data_rate == 333) {
cpo = 0x7; /* READ_LAT + 5/4 */
} else if (effective_data_rate == 400) {
cpo = 0x9; /* READ_LAT + 7/4 */
cpo = 0x7; /* READ_LAT + 5/4 */
} else {
/* Automatic calibration */
cpo = 0x1f;
@ -705,9 +706,11 @@ long int spd_sdram()
* SDRAM Cfg 2
*/
odt_cfg = 0;
#ifndef CONFIG_NEVER_ASSERT_ODT_TO_CPU
if (odt_rd_cfg | odt_wr_cfg) {
odt_cfg = 0x2; /* ODT to IOs during reads */
}
#endif
if (spd.mem_type == SPD_MEMTYPE_DDR2) {
ddr->sdram_cfg2 = (0
| (0 << 26) /* True DQS */

203
cpu/mpc83xx/speed.c
View File

@ -2,7 +2,7 @@
* (C) Copyright 2000-2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -100,7 +100,7 @@ int get_clocks(void)
u32 lcrr;
u32 csb_clk;
#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X)
#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
u32 tsec1_clk;
u32 tsec2_clk;
u32 usbdr_clk;
@ -112,6 +112,12 @@ int get_clocks(void)
u32 i2c1_clk;
#if !defined(CONFIG_MPC832X)
u32 i2c2_clk;
#endif
#if defined(CONFIG_MPC8315)
u32 tdm_clk;
#endif
#if defined(CONFIG_MPC837X)
u32 sdhc_clk;
#endif
u32 enc_clk;
u32 lbiu_clk;
@ -126,6 +132,13 @@ int get_clocks(void)
u32 qe_clk;
u32 brg_clk;
#endif
#if defined(CONFIG_MPC837X)
u32 pciexp1_clk;
u32 pciexp2_clk;
#endif
#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
u32 sata_clk;
#endif
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
return -1;
@ -151,7 +164,7 @@ int get_clocks(void)
sccr = im->clk.sccr;
#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X)
#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
case 0:
tsec1_clk = 0;
@ -167,7 +180,7 @@ int get_clocks(void)
break;
default:
/* unkown SCCR_TSEC1CM value */
return -4;
return -2;
}
switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
@ -185,11 +198,11 @@ int get_clocks(void)
break;
default:
/* unkown SCCR_USBDRCM value */
return -8;
return -3;
}
#endif
#if defined(CONFIG_MPC834X)
#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
case 0:
tsec2_clk = 0;
@ -205,11 +218,18 @@ int get_clocks(void)
break;
default:
/* unkown SCCR_TSEC2CM value */
return -5;
return -4;
}
#elif defined(CONFIG_MPC8313)
tsec2_clk = tsec1_clk;
i2c1_clk = tsec2_clk;
if (!(sccr & SCCR_TSEC1ON))
tsec1_clk = 0;
if (!(sccr & SCCR_TSEC2ON))
tsec2_clk = 0;
#endif
#if defined(CONFIG_MPC834X)
switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
case 0:
usbmph_clk = 0;
@ -225,7 +245,7 @@ int get_clocks(void)
break;
default:
/* unkown SCCR_USBMPHCM value */
return -7;
return -5;
}
if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
@ -233,24 +253,9 @@ int get_clocks(void)
* USB DR clock is not disabled then
* USB MPH & USB DR must have the same rate
*/
return -9;
return -6;
}
#elif defined(CONFIG_MPC831X)
tsec2_clk = tsec1_clk;
if (!(sccr & SCCR_TSEC1ON))
tsec1_clk = 0;
if (!(sccr & SCCR_TSEC2ON))
tsec2_clk = 0;
#endif
#if !defined(CONFIG_MPC834X)
i2c1_clk = csb_clk;
#endif
#if !defined(CONFIG_MPC832X)
i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
#endif
switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
case 0:
enc_clk = 0;
@ -266,9 +271,121 @@ int get_clocks(void)
break;
default:
/* unkown SCCR_ENCCM value */
return -6;
return -7;
}
#if defined(CONFIG_MPC837X)
switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
case 0:
sdhc_clk = 0;
break;
case 1:
sdhc_clk = csb_clk;
break;
case 2:
sdhc_clk = csb_clk / 2;
break;
case 3:
sdhc_clk = csb_clk / 3;
break;
default:
/* unkown SCCR_SDHCCM value */
return -8;
}
#endif
#if defined(CONFIG_MPC8315)
switch ((sccr & SCCR_TDMCM) >> SCCR_TDMCM_SHIFT) {
case 0:
tdm_clk = 0;
break;
case 1:
tdm_clk = csb_clk;
break;
case 2:
tdm_clk = csb_clk / 2;
break;
case 3:
tdm_clk = csb_clk / 3;
break;
default:
/* unkown SCCR_TDMCM value */
return -8;
}
#endif
#if defined(CONFIG_MPC834X)
i2c1_clk = tsec2_clk;
#elif defined(CONFIG_MPC8360)
i2c1_clk = csb_clk;
#elif defined(CONFIG_MPC832X)
i2c1_clk = enc_clk;
#elif defined(CONFIG_MPC831X)
i2c1_clk = enc_clk;
#elif defined(CONFIG_MPC837X)
i2c1_clk = sdhc_clk;
#endif
#if !defined(CONFIG_MPC832X)
i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
#endif
#if defined(CONFIG_MPC837X)
switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
case 0:
pciexp1_clk = 0;
break;
case 1:
pciexp1_clk = csb_clk;
break;
case 2:
pciexp1_clk = csb_clk / 2;
break;
case 3:
pciexp1_clk = csb_clk / 3;
break;
default:
/* unkown SCCR_PCIEXP1CM value */
return -9;
}
switch ((sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT) {
case 0:
pciexp2_clk = 0;
break;
case 1:
pciexp2_clk = csb_clk;
break;
case 2:
pciexp2_clk = csb_clk / 2;
break;
case 3:
pciexp2_clk = csb_clk / 3;
break;
default:
/* unkown SCCR_PCIEXP2CM value */
return -10;
}
#endif
#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
case 0:
sata_clk = 0;
break;
case 1:
sata_clk = csb_clk;
break;
case 2:
sata_clk = csb_clk / 2;
break;
case 3:
sata_clk = csb_clk / 3;
break;
default:
/* unkown SCCR_SATA1CM value */
return -11;
}
#endif
lbiu_clk = csb_clk *
(1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
@ -280,7 +397,7 @@ int get_clocks(void)
break;
default:
/* unknown lcrr */
return -10;
return -12;
}
ddr_clk = csb_clk *
@ -316,7 +433,7 @@ int get_clocks(void)
break;
default:
/* unkown core to csb ratio */
return -12;
return -13;
}
#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
@ -327,13 +444,19 @@ int get_clocks(void)
#endif
gd->csb_clk = csb_clk;
#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X)
#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
gd->tsec1_clk = tsec1_clk;
gd->tsec2_clk = tsec2_clk;
gd->usbdr_clk = usbdr_clk;
#endif
#if defined(CONFIG_MPC834X)
gd->usbmph_clk = usbmph_clk;
#endif
#if defined(CONFIG_MPC8315)
gd->tdm_clk = tdm_clk;
#endif
#if defined(CONFIG_MPC837X)
gd->sdhc_clk = sdhc_clk;
#endif
gd->core_clk = core_clk;
gd->i2c1_clk = i2c1_clk;
@ -350,6 +473,13 @@ int get_clocks(void)
#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
gd->qe_clk = qe_clk;
gd->brg_clk = brg_clk;
#endif
#if defined(CONFIG_MPC837X)
gd->pciexp1_clk = pciexp1_clk;
gd->pciexp2_clk = pciexp2_clk;
#endif
#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
gd->sata_clk = sata_clk;
#endif
gd->pci_clk = pci_sync_in;
gd->cpu_clk = gd->core_clk;
@ -387,13 +517,26 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
#if !defined(CONFIG_MPC832X)
printf(" I2C2: %4d MHz\n", gd->i2c2_clk / 1000000);
#endif
#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X)
#if defined(CONFIG_MPC8315)
printf(" TDM: %4d MHz\n", gd->tdm_clk / 1000000);
#endif
#if defined(CONFIG_MPC837X)
printf(" SDHC: %4d MHz\n", gd->sdhc_clk / 1000000);
#endif
#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
printf(" TSEC1: %4d MHz\n", gd->tsec1_clk / 1000000);
printf(" TSEC2: %4d MHz\n", gd->tsec2_clk / 1000000);
printf(" USB DR: %4d MHz\n", gd->usbdr_clk / 1000000);
#endif
#if defined(CONFIG_MPC834X)
printf(" USB MPH: %4d MHz\n", gd->usbmph_clk / 1000000);
#endif
#if defined(CONFIG_MPC837X)
printf(" PCIEXP1: %4d MHz\n", gd->pciexp1_clk / 1000000);
printf(" PCIEXP2: %4d MHz\n", gd->pciexp2_clk / 1000000);
#endif
#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
printf(" SATA: %4d MHz\n", gd->sata_clk / 1000000);
#endif
return 0;
}

15
cpu/mpc86xx/cpu.c
View File

@ -41,6 +41,8 @@ checkcpu(void)
uint major, minor;
uint lcrr; /* local bus clock ratio register */
uint clkdiv; /* clock divider portion of lcrr */
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
puts("Freescale PowerPC\n");
@ -54,8 +56,14 @@ checkcpu(void)
switch (ver) {
case PVR_VER(PVR_86xx):
puts("E600");
break;
{
uint msscr0 = mfspr(MSSCR0);
printf("E600 Core %d", (msscr0 & 0x20) ? 1 : 0 );
if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE)
puts("\n Core1Translation Enabled");
debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr);
}
break;
default:
puts("Unknown");
break;
@ -76,6 +84,9 @@ checkcpu(void)
puts("8641");
}
break;
case SVR_8610:
puts("8610");
break;
default:
puts("Unknown");
break;

107
cpu/mpc8xx/fec.c
View File

@ -143,6 +143,7 @@ static int fec_send(struct eth_device* dev, volatile void *packet, int length);
static int fec_recv(struct eth_device* dev);
static int fec_init(struct eth_device* dev, bd_t * bd);
static void fec_halt(struct eth_device* dev);
static void __mii_init(void);
int fec_initialize(bd_t *bis)
{
@ -539,6 +540,30 @@ static void fec_pin_init(int fecidx)
}
}
static int fec_reset(volatile fec_t *fecp)
{
int i;
/* Whack a reset.
* A delay is required between a reset of the FEC block and
* initialization of other FEC registers because the reset takes
* some time to complete. If you don't delay, subsequent writes
* to FEC registers might get killed by the reset routine which is
* still in progress.
*/
fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
for (i = 0;
(fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
++i) {
udelay (1);
}
if (i == FEC_RESET_DELAY)
return -1;
return 0;
}
static int fec_init (struct eth_device *dev, bd_t * bd)
{
struct ether_fcc_info_s *efis = dev->priv;
@ -573,23 +598,17 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
#endif /* CONFIG_FADS */
}
/* Whack a reset.
* A delay is required between a reset of the FEC block and
* initialization of other FEC registers because the reset takes
* some time to complete. If you don't delay, subsequent writes
* to FEC registers might get killed by the reset routine which is
* still in progress.
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
/* the MII interface is connected to FEC1
* so for the miiphy_xxx function to work we must
* call mii_init since fec_halt messes the thing up
*/
fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
for (i = 0;
(fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
++i) {
udelay (1);
}
if (i == FEC_RESET_DELAY) {
if (efis->ether_index != 0)
__mii_init();
#endif
if (fec_reset(fecp) < 0)
printf ("FEC_RESET_DELAY timeout\n");
return 0;
}
/* We use strictly polling mode only
*/
@ -603,7 +622,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
/* Set station address
*/
#define ea eth_get_dev()->enetaddr
#define ea dev->enetaddr
fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
fecp->fec_addr_high = (ea[4] << 8) | (ea[5]);
#undef ea
@ -716,15 +735,8 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
} else {
efis->actual_phy_addr = efis->phy_addr;
}
#if defined(CONFIG_MII) && defined(CONFIG_RMII)
/* the MII interface is connected to FEC1
* so for the miiphy_xxx function to work we must
* call mii_init since fec_halt messes the thing up
*/
if (efis->ether_index != 0)
mii_init();
/*
* adapt the RMII speed to the speed of the phy
*/
@ -874,15 +886,14 @@ static int mii_discover_phy(struct eth_device *dev)
udelay(10000); /* wait 10ms */
}
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
#ifdef ET_DEBUG
printf("PHY type 0x%x pass %d type ", phytype, pass);
#endif
if (phytype != 0xffff) {
phyaddr = phyno;
phytype <<= 16;
phytype |= mii_send(mk_mii_read(phyno,
PHY_PHYIDR2));
PHY_PHYIDR1)) << 16;
#ifdef ET_DEBUG
printf("PHY @ 0x%x pass %d type ",phyno,pass);
@ -929,36 +940,17 @@ static int mii_discover_phy(struct eth_device *dev)
#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && !defined(CONFIG_BITBANGMII)
/****************************************************************************
* mii_init -- Initialize the MII for MII command without ethernet
* mii_init -- Initialize the MII via FEC 1 for MII command without ethernet
* This function is a subset of eth_init
****************************************************************************
*/
void mii_init (void)
static void __mii_init(void)
{
volatile immap_t *immr = (immap_t *) CFG_IMMR;
volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
int i, j;
for (j = 0; j < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); j++) {
/* Whack a reset.
* A delay is required between a reset of the FEC block and
* initialization of other FEC registers because the reset takes
* some time to complete. If you don't delay, subsequent writes
* to FEC registers might get killed by the reset routine which is
* still in progress.
*/
fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
for (i = 0;
(fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
++i) {
udelay (1);
}
if (i == FEC_RESET_DELAY) {
if (fec_reset(fecp) < 0)
printf ("FEC_RESET_DELAY timeout\n");
return;
}
/* We use strictly polling mode only
*/
@ -968,14 +960,21 @@ void mii_init (void)
*/
fecp->fec_ievent = 0xffc0;
/* Setup the pin configuration of the FEC(s)
*/
fec_pin_init(ether_fcc_info[i].ether_index);
/* Now enable the transmit and receive processing
*/
fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
}
}
void mii_init (void)
{
int i;
__mii_init();
/* Setup the pin configuration of the FEC(s)
*/
for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++)
fec_pin_init(ether_fcc_info[i].ether_index);
}
/*****************************************************************************

96
cpu/ppc4xx/44x_spd_ddr2.c
View File

@ -3,7 +3,7 @@
* This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
* DDR2 controller (non Denali Core). Those are 440SP/SPe.
*
* (C) Copyright 2007
* (C) Copyright 2007-2008
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* COPYRIGHT AMCC CORPORATION 2004
@ -111,8 +111,6 @@
#define NUMMEMWORDS 8
#define NUMLOOPS 64 /* memory test loops */
#undef CONFIG_ECC_ERROR_RESET /* test-only: see description below, at check_ecc() */
/*
* This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
* region. Right now the cache should still be disabled in U-Boot because of the
@ -2268,39 +2266,6 @@ static void program_ecc(unsigned long *dimm_populated,
return;
}
#ifdef CONFIG_ECC_ERROR_RESET
/*
* Check for ECC errors and reset board upon any error here
*
* On the Katmai 440SPe eval board, from time to time, the first
* lword write access after DDR2 initializazion with ECC checking
* enabled, leads to an ECC error. I couldn't find a configuration
* without this happening. On my board with the current setup it
* happens about 1 from 10 times.
*
* The ECC modules used for testing are:
* - Kingston ValueRAM KVR667D2E5/512 (tested with 1 and 2 DIMM's)
*
* This has to get fixed for the Katmai and tested for the other
* board (440SP/440SPe) that will eventually use this code in the
* future.
*
* 2007-03-01, sr
*/
static void check_ecc(void)
{
u32 val;
mfsdram(SDRAM_ECCCR, val);
if (val != 0) {
printf("\nECC error: MCIF0_ECCES=%08lx MQ0_ESL=%08lx address=%08lx\n",
val, mfdcr(0x4c), mfdcr(0x4e));
printf("ECC error occured, resetting board...\n");
do_reset(NULL, 0, 0, NULL);
}
}
#endif
static void wait_ddr_idle(void)
{
u32 val;
@ -2375,15 +2340,6 @@ static void program_ecc_addr(unsigned long start_address,
sync();
eieio();
wait_ddr_idle();
#ifdef CONFIG_ECC_ERROR_RESET
/*
* One write to 0 is enough to trigger this ECC error
* (see description above)
*/
out_be32(0, 0x12345678);
check_ecc();
#endif
}
}
#endif
@ -2409,17 +2365,10 @@ static void program_DQS_calibration(unsigned long *dimm_populated,
* Read sample cycle auto-update enable
*-----------------------------------------------------------------*/
/*
* Modified for the Katmai platform: with some DIMMs, the DDR2
* controller automatically selects the T2 read cycle, but this
* proves unreliable. Go ahead and force the DDR2 controller
* to use the T4 sample and disable the automatic update of the
* RDSS field.
*/
mfsdram(SDRAM_RDCC, val);
mtsdram(SDRAM_RDCC,
(val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
| (SDRAM_RDCC_RDSS_T4 | SDRAM_RDCC_RSAE_DISABLE));
| SDRAM_RDCC_RSAE_ENABLE);
/*------------------------------------------------------------------
* Program RQDC register
@ -2512,10 +2461,7 @@ static void DQS_calibration_process(void)
{
unsigned long rfdc_reg;
unsigned long rffd;
unsigned long rqdc_reg;
unsigned long rqfd;
unsigned long val;
long rqfd_average;
long rffd_average;
long max_start;
long min_end;
@ -2533,10 +2479,14 @@ static void DQS_calibration_process(void)
long max_end;
unsigned char fail_found;
unsigned char pass_found;
#if !defined(CONFIG_DDR_RQDC_FIXED)
u32 rqdc_reg;
u32 rqfd;
u32 rqfd_start;
u32 rqfd_average;
int loopi = 0;
char str[] = "Auto calibration -";
char slash[] = "\\|/-\\|/-";
int loopi = 0;
/*------------------------------------------------------------------
* Test to determine the best read clock delay tuning bits.
@ -2571,6 +2521,16 @@ calibration_loop:
mfsdram(SDRAM_RQDC, rqdc_reg);
mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
#else /* CONFIG_DDR_RQDC_FIXED */
/*
* On Katmai the complete auto-calibration somehow doesn't seem to
* produce the best results, meaning optimal values for RQFD/RFFD.
* This was discovered by GDA using a high bandwidth scope,
* analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
* so now on Katmai "only" RFFD is auto-calibrated.
*/
mtsdram(SDRAM_RQDC, CONFIG_DDR_RQDC_FIXED);
#endif /* CONFIG_DDR_RQDC_FIXED */
max_start = 0;
min_end = 0;
@ -2655,6 +2615,7 @@ calibration_loop:
/* now fix RFDC[RFFD] found and find RQDC[RQFD] */
mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
#if !defined(CONFIG_DDR_RQDC_FIXED)
max_pass_length = 0;
max_start = 0;
max_end = 0;
@ -2727,8 +2688,6 @@ calibration_loop:
spd_ddr_init_hang ();
}
blank_string(strlen(str));
if (rqfd_average < 0)
rqfd_average = 0;
@ -2739,12 +2698,31 @@ calibration_loop:
(rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
blank_string(strlen(str));
#endif /* CONFIG_DDR_RQDC_FIXED */
/*
* Now complete RDSS configuration as mentioned on page 7 of the AMCC
* PowerPC440SP/SPe DDR2 application note:
* "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
*/
mfsdram(SDRAM_RTSR, val);
if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
mfsdram(SDRAM_RDCC, val);
if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
val += 0x40000000;
mtsdram(SDRAM_RDCC, val);
}
}
mfsdram(SDRAM_DLCR, val);
debug("%s[%d] DLCR: 0x%08X\n", __FUNCTION__, __LINE__, val);
mfsdram(SDRAM_RQDC, val);
debug("%s[%d] RQDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
mfsdram(SDRAM_RFDC, val);
debug("%s[%d] RFDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
mfsdram(SDRAM_RDCC, val);
debug("%s[%d] RDCC: 0x%08X\n", __FUNCTION__, __LINE__, val);
}
#else /* calibration test with hardvalues */
/*-----------------------------------------------------------------------------+

7
cpu/ppc4xx/4xx_enet.c
View File

@ -90,7 +90,7 @@
#include <405_mal.h>
#include <miiphy.h>
#include <malloc.h>
#include "vecnum.h"
#include <asm/ppc4xx-intvec.h>
/*
* Only compile for platform with AMCC EMAC ethernet controller and
@ -1036,7 +1036,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
hw_p->bis = bis;
hw_p->first_init = 1;
return (1);
return 0;
}
@ -1755,7 +1755,8 @@ int ppc_4xx_eth_initialize (bd_t * bis)
#endif
#endif
} /* end for each supported device */
return (1);
return 0;
}
#if !defined(CONFIG_NET_MULTI)

2
cpu/ppc4xx/4xx_uart.c
View File

@ -46,7 +46,7 @@
#include <asm/processor.h>
#include <asm/io.h>
#include <watchdog.h>
#include "vecnum.h"
#include <asm/ppc4xx-intvec.h>
#ifdef CONFIG_SERIAL_MULTI
#include <serial.h>

14
cpu/ppc4xx/commproc.c
View File

@ -26,10 +26,21 @@
#include <common.h>
#include <commproc.h>
#include <asm/io.h>
#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
#if defined(CFG_POST_ALT_WORD_ADDR)
void post_word_store (ulong a)
{
out_be32((void *)CFG_POST_ALT_WORD_ADDR, a);
}
ulong post_word_load (void)
{
return in_be32((void *)CFG_POST_ALT_WORD_ADDR);
}
#else /* CFG_POST_ALT_WORD_ADDR */
void post_word_store (ulong a)
{
volatile void *save_addr = (volatile void *)(CFG_OCM_DATA_ADDR + CFG_POST_WORD_ADDR);
@ -41,6 +52,7 @@ ulong post_word_load (void)
volatile void *save_addr = (volatile void *)(CFG_OCM_DATA_ADDR + CFG_POST_WORD_ADDR);
return *(volatile ulong *) save_addr;
}
#endif /* CFG_POST_ALT_WORD_ADDR */
#endif /* CONFIG_POST || CONFIG_LOGBUFFER*/

7
cpu/ppc4xx/denali_data_eye.c
View File

@ -99,14 +99,7 @@ static int wait_for_dram_init_complete(void)
/*-----------------------------------------------------------------------------+
* denali_core_search_data_eye.
+----------------------------------------------------------------------------*/
/*
* Avoid conflict with implementations of denali_core_search_data_eye in board-
* specific code.
*/
void denali_core_search_data_eye(void)
__attribute__ ((weak, alias("__denali_core_search_data_eye")));
void __denali_core_search_data_eye(void)
{
int k, j;
u32 val;

63
cpu/ppc4xx/gpio.c
View File

@ -27,7 +27,7 @@
#include <asm/gpio.h>
#if defined(CFG_4xx_GPIO_TABLE)
gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_4xx_GPIO_TABLE;
gpio_param_s const gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_4xx_GPIO_TABLE;
#endif
#if defined(GPIO0_OSRL)
@ -120,6 +120,18 @@ int gpio_read_out_bit(int pin)
return (in_be32((void *)GPIO0_OR + offs) & GPIO_VAL(pin) ? 1 : 0);
}
int gpio_read_in_bit(int pin)
{
u32 offs = 0;
if (pin >= GPIO_MAX) {
offs = 0x100;
pin -= GPIO_MAX;
}
return (in_be32((void *)GPIO0_IR + offs) & GPIO_VAL(pin) ? 1 : 0);
}
#if defined(CFG_4xx_GPIO_TABLE)
void gpio_set_chip_configuration(void)
{
@ -171,6 +183,8 @@ void gpio_set_chip_configuration(void)
if ((gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
(gpio_tab[gpio_core][i].in_out == GPIO_BI)) {
u32 gpio_alt_sel = 0;
switch (gpio_tab[gpio_core][i].alt_nb) {
case GPIO_SEL:
/*
@ -199,37 +213,40 @@ void gpio_set_chip_configuration(void)
break;
case GPIO_ALT1:
reg = in_be32((void *)GPIO_OS(core_add+offs))
& ~(GPIO_MASK >> (j*2));
reg = reg | (GPIO_ALT1_SEL >> (j*2));
out_be32((void *)GPIO_OS(core_add+offs), reg);
reg = in_be32((void *)GPIO_TS(core_add+offs))
& ~(GPIO_MASK >> (j*2));
reg = reg | (GPIO_ALT1_SEL >> (j*2));
out_be32((void *)GPIO_TS(core_add+offs), reg);
gpio_alt_sel = GPIO_ALT1_SEL;
break;
case GPIO_ALT2:
reg = in_be32((void *)GPIO_OS(core_add+offs))
& ~(GPIO_MASK >> (j*2));
reg = reg | (GPIO_ALT2_SEL >> (j*2));
out_be32((void *)GPIO_OS(core_add+offs), reg);
reg = in_be32((void *)GPIO_TS(core_add+offs))
& ~(GPIO_MASK >> (j*2));
reg = reg | (GPIO_ALT2_SEL >> (j*2));
out_be32((void *)GPIO_TS(core_add+offs), reg);
gpio_alt_sel = GPIO_ALT2_SEL;
break;
case GPIO_ALT3:
gpio_alt_sel = GPIO_ALT3_SEL;
break;
}
if (0 != gpio_alt_sel) {
reg = in_be32((void *)GPIO_OS(core_add+offs))
& ~(GPIO_MASK >> (j*2));
reg = reg | (GPIO_ALT3_SEL >> (j*2));
reg = reg | (gpio_alt_sel >> (j*2));
out_be32((void *)GPIO_OS(core_add+offs), reg);
reg = in_be32((void *)GPIO_TS(core_add+offs))
& ~(GPIO_MASK >> (j*2));
reg = reg | (GPIO_ALT3_SEL >> (j*2));
out_be32((void *)GPIO_TS(core_add+offs), reg);
break;
if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1) {
reg = in_be32((void *)GPIO_TCR(core_add))
| (0x80000000 >> (i));
out_be32((void *)GPIO_TCR(core_add), reg);
reg = in_be32((void *)GPIO_TS(core_add+offs))
& ~(GPIO_MASK >> (j*2));
out_be32((void *)GPIO_TS(core_add+offs), reg);
} else {
reg = in_be32((void *)GPIO_TCR(core_add))
& ~(0x80000000 >> (i));
out_be32((void *)GPIO_TCR(core_add), reg);
reg = in_be32((void *)GPIO_TS(core_add+offs))
& ~(GPIO_MASK >> (j*2));
reg = reg | (gpio_alt_sel >> (j*2));
out_be32((void *)GPIO_TS(core_add+offs), reg);
}
}
}
}

2
cpu/ppc4xx/interrupts.c
View File

@ -34,7 +34,7 @@
#include <ppc4xx.h>
#include <ppc_asm.tmpl>
#include <commproc.h>
#include "vecnum.h"
#include <asm/ppc4xx-intvec.h>
DECLARE_GLOBAL_DATA_PTR;

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