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https://github.com/brain-hackers/u-boot-brain
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x86: apl: Add ITSS driver
This driver models some sort of interrupt thingy but there are so many abreviations that I cannot find out what it stands for. Possibly something to do with interrupts. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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@ -5,5 +5,6 @@
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obj-$(CONFIG_SPL_BUILD) += systemagent.o
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obj-y += hostbridge.o
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obj-y += itss.o
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obj-y += pmc.o
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obj-y += uart.o
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arch/x86/cpu/apollolake/itss.c
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arch/x86/cpu/apollolake/itss.c
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Something to do with Interrupts, but I don't know what ITSS stands for
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*
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* Copyright (C) 2017 Intel Corporation.
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* Copyright (C) 2017 Siemens AG
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* Copyright 2019 Google LLC
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*
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* Taken from coreboot itss.c
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*/
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#include <common.h>
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#include <dm.h>
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#include <dt-structs.h>
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#include <irq.h>
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#include <p2sb.h>
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#include <spl.h>
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#include <asm/arch/itss.h>
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struct apl_itss_platdata {
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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/* Put this first since driver model will copy the data here */
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struct dtd_intel_apl_itss dtplat;
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#endif
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};
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/* struct pmc_route - Routing for PMC to GPIO */
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struct pmc_route {
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u32 pmc;
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u32 gpio;
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};
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struct apl_itss_priv {
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struct pmc_route *route;
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uint route_count;
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u32 irq_snapshot[NUM_IPC_REGS];
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};
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static int apl_set_polarity(struct udevice *dev, uint irq, bool active_low)
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{
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u32 mask;
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uint reg;
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if (irq > ITSS_MAX_IRQ)
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return -EINVAL;
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reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * (irq / IRQS_PER_IPC);
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mask = 1 << (irq % IRQS_PER_IPC);
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pcr_clrsetbits32(dev, reg, mask, active_low ? mask : 0);
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return 0;
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}
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#ifndef CONFIG_TPL_BUILD
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static int apl_snapshot_polarities(struct udevice *dev)
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{
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struct apl_itss_priv *priv = dev_get_priv(dev);
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const int start = GPIO_IRQ_START;
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const int end = GPIO_IRQ_END;
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int reg_start;
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int reg_end;
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int i;
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reg_start = start / IRQS_PER_IPC;
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reg_end = (end + IRQS_PER_IPC - 1) / IRQS_PER_IPC;
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for (i = reg_start; i < reg_end; i++) {
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uint reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * i;
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priv->irq_snapshot[i] = pcr_read32(dev, reg);
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}
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return 0;
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}
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static void show_polarities(struct udevice *dev, const char *msg)
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{
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int i;
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log_info("ITSS IRQ Polarities %s:\n", msg);
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for (i = 0; i < NUM_IPC_REGS; i++) {
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uint reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * i;
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log_info("IPC%d: 0x%08x\n", i, pcr_read32(dev, reg));
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}
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}
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static int apl_restore_polarities(struct udevice *dev)
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{
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struct apl_itss_priv *priv = dev_get_priv(dev);
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const int start = GPIO_IRQ_START;
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const int end = GPIO_IRQ_END;
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int reg_start;
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int reg_end;
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int i;
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show_polarities(dev, "Before");
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reg_start = start / IRQS_PER_IPC;
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reg_end = (end + IRQS_PER_IPC - 1) / IRQS_PER_IPC;
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for (i = reg_start; i < reg_end; i++) {
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u32 mask;
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u16 reg;
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int irq_start;
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int irq_end;
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irq_start = i * IRQS_PER_IPC;
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irq_end = min(irq_start + IRQS_PER_IPC - 1, ITSS_MAX_IRQ);
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if (start > irq_end)
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continue;
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if (end < irq_start)
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break;
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/* Track bits within the bounds of of the register */
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irq_start = max(start, irq_start) % IRQS_PER_IPC;
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irq_end = min(end, irq_end) % IRQS_PER_IPC;
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/* Create bitmask of the inclusive range of start and end */
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mask = (((1U << irq_end) - 1) | (1U << irq_end));
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mask &= ~((1U << irq_start) - 1);
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reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * i;
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pcr_clrsetbits32(dev, reg, mask, mask & priv->irq_snapshot[i]);
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}
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show_polarities(dev, "After");
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return 0;
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}
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#endif
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static int apl_route_pmc_gpio_gpe(struct udevice *dev, uint pmc_gpe_num)
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{
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struct apl_itss_priv *priv = dev_get_priv(dev);
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struct pmc_route *route;
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int i;
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for (i = 0, route = priv->route; i < priv->route_count; i++, route++) {
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if (pmc_gpe_num == route->pmc)
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return route->gpio;
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}
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return -ENOENT;
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}
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static int apl_itss_ofdata_to_platdata(struct udevice *dev)
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{
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struct apl_itss_priv *priv = dev_get_priv(dev);
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int ret;
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct apl_itss_platdata *plat = dev_get_platdata(dev);
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struct dtd_intel_apl_itss *dtplat = &plat->dtplat;
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/*
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* It would be nice to do this in the bind() method, but with
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* of-platdata binding happens in the order that DM finds things in the
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* linker list (i.e. alphabetical order by driver name). So the GPIO
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* device may well be bound before its parent (p2sb), and this call
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* will fail if p2sb is not bound yet.
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*
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* TODO(sjg@chromium.org): Add a parent pointer to child devices in dtoc
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*/
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ret = p2sb_set_port_id(dev, dtplat->intel_p2sb_port_id);
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if (ret)
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return log_msg_ret("Could not set port id", ret);
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priv->route = (struct pmc_route *)dtplat->intel_pmc_routes;
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priv->route_count = ARRAY_SIZE(dtplat->intel_pmc_routes) /
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sizeof(struct pmc_route);
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#else
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int size;
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size = dev_read_size(dev, "intel,pmc-routes");
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if (size < 0)
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return size;
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priv->route = malloc(size);
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if (!priv->route)
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return -ENOMEM;
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ret = dev_read_u32_array(dev, "intel,pmc-routes", (u32 *)priv->route,
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size / sizeof(fdt32_t));
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if (ret)
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return log_msg_ret("Cannot read pmc-routes", ret);
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priv->route_count = size / sizeof(struct pmc_route);
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#endif
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return 0;
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}
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static const struct irq_ops apl_itss_ops = {
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.route_pmc_gpio_gpe = apl_route_pmc_gpio_gpe,
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.set_polarity = apl_set_polarity,
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#ifndef CONFIG_TPL_BUILD
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.snapshot_polarities = apl_snapshot_polarities,
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.restore_polarities = apl_restore_polarities,
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#endif
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};
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static const struct udevice_id apl_itss_ids[] = {
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{ .compatible = "intel,apl-itss"},
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{ }
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};
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U_BOOT_DRIVER(apl_itss_drv) = {
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.name = "intel_apl_itss",
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.id = UCLASS_IRQ,
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.of_match = apl_itss_ids,
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.ops = &apl_itss_ops,
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.ofdata_to_platdata = apl_itss_ofdata_to_platdata,
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.platdata_auto_alloc_size = sizeof(struct apl_itss_platdata),
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.priv_auto_alloc_size = sizeof(struct apl_itss_priv),
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};
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arch/x86/include/asm/arch-apollolake/itss.h
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arch/x86/include/asm/arch-apollolake/itss.h
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2017 Intel Corporation.
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* Copyright 2019 Google LLC
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*
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* Modified from coreboot itss.h
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*/
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#ifndef _ASM_ARCH_ITSS_H
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#define _ASM_ARCH_ITSS_H
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#define GPIO_IRQ_START 50
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#define GPIO_IRQ_END ITSS_MAX_IRQ
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#define ITSS_MAX_IRQ 119
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#define IRQS_PER_IPC 32
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#define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1) / IRQS_PER_IPC)
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/* Max PXRC registers in ITSS */
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#define MAX_PXRC_CONFIG (PCR_ITSS_PIRQH_ROUT - PCR_ITSS_PIRQA_ROUT + 1)
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/* PIRQA Routing Control Register */
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#define PCR_ITSS_PIRQA_ROUT 0x3100
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/* PIRQB Routing Control Register */
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#define PCR_ITSS_PIRQB_ROUT 0x3101
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/* PIRQC Routing Control Register */
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#define PCR_ITSS_PIRQC_ROUT 0x3102
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/* PIRQD Routing Control Register */
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#define PCR_ITSS_PIRQD_ROUT 0x3103
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/* PIRQE Routing Control Register */
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#define PCR_ITSS_PIRQE_ROUT 0x3104
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/* PIRQF Routing Control Register */
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#define PCR_ITSS_PIRQF_ROUT 0x3105
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/* PIRQG Routing Control Register */
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#define PCR_ITSS_PIRQG_ROUT 0x3106
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/* PIRQH Routing Control Register */
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#define PCR_ITSS_PIRQH_ROUT 0x3107
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/* ITSS Interrupt polarity control */
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#define PCR_ITSS_IPC0_CONF 0x3200
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/* ITSS Power reduction control */
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#define PCR_ITSS_ITSSPRC 0x3300
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#endif /* _ASM_ARCH_ITSS_H */
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