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arm: mxs: Add LCDIF registers for i.MX233

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Extend the regs-lcdif.h with registers for i.MX233.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Marek Vasut 2013-04-28 09:20:02 +00:00 committed by Stefano Babic
parent 7411cdf0e2
commit 38e8ce4189
1 changed files with 27 additions and 9 deletions
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36
arch/arm/include/asm/arch-mxs/regs-lcdif.h
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@ -32,10 +32,17 @@
struct mxs_lcdif_regs {
mxs_reg_32(hw_lcdif_ctrl) /* 0x00 */
mxs_reg_32(hw_lcdif_ctrl1) /* 0x10 */
#if defined(CONFIG_MX28)
mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */
mxs_reg_32(hw_lcdif_transfer_count) /* 0x30 */
mxs_reg_32(hw_lcdif_cur_buf) /* 0x40 */
mxs_reg_32(hw_lcdif_next_buf) /* 0x50 */
#endif
mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */
mxs_reg_32(hw_lcdif_cur_buf) /* 0x30/0x40 */
mxs_reg_32(hw_lcdif_next_buf) /* 0x40/0x50 */
#if defined(CONFIG_MX23)
uint32_t reserved1[4];
#endif
mxs_reg_32(hw_lcdif_timing) /* 0x60 */
mxs_reg_32(hw_lcdif_vdctrl0) /* 0x70 */
mxs_reg_32(hw_lcdif_vdctrl1) /* 0x80 */
@ -54,13 +61,19 @@ struct mxs_lcdif_regs {
mxs_reg_32(hw_lcdif_csc_coeffctrl4) /* 0x150 */
mxs_reg_32(hw_lcdif_csc_offset) /* 0x160 */
mxs_reg_32(hw_lcdif_csc_limit) /* 0x170 */
mxs_reg_32(hw_lcdif_data) /* 0x180 */
mxs_reg_32(hw_lcdif_bm_error_stat) /* 0x190 */
#if defined(CONFIG_MX23)
uint32_t reserved2[12];
#endif
mxs_reg_32(hw_lcdif_data) /* 0x1b0/0x180 */
mxs_reg_32(hw_lcdif_bm_error_stat) /* 0x1c0/0x190 */
#if defined(CONFIG_MX28)
mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */
mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1b0 */
mxs_reg_32(hw_lcdif_version) /* 0x1c0 */
mxs_reg_32(hw_lcdif_debug0) /* 0x1d0 */
mxs_reg_32(hw_lcdif_debug1) /* 0x1e0 */
#endif
mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */
mxs_reg_32(hw_lcdif_version) /* 0x1e0/0x1c0 */
mxs_reg_32(hw_lcdif_debug0) /* 0x1f0/0x1d0 */
mxs_reg_32(hw_lcdif_debug1) /* 0x200/0x1e0 */
mxs_reg_32(hw_lcdif_debug2) /* 0x1f0 */
};
#endif
@ -191,8 +204,13 @@ struct mxs_lcdif_regs {
#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK 0xffffffff
#define LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET 0
#if defined(CONFIG_MX23)
#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xff << 24)
#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 24
#elif defined(CONFIG_MX28)
#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0x3fff << 18)
#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 18
#endif
#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK 0x3ffff
#define LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET 0