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apalis_imx6: disable ri and dcd irq in uarts

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If the UART is used in DTE mode the RI and DCD bits in UCR3 become
irq enable bits. Both are set to enabled after reset and both likely
are pending.

Disable the bits also on UARTs not used in the boot loader to prevent
an interrupt storm when Linux enables the UART interrupts.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
This commit is contained in:
Max Krummenacher 2019-02-08 18:12:21 +01:00 committed by Stefano Babic
parent b4707a25d0
commit 389f61ef44
1 changed files with 9 additions and 1 deletions
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10
board/toradex/apalis_imx6/apalis_imx6.c
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@ -238,8 +238,11 @@ iomux_v3_cfg_t const usb_pads[] = {
* UARTs are used in DTE mode, switch the mode on all UARTs before
* any pinmuxing connects a (DCE) output to a transceiver output.
*/
#define UCR3 0x88 /* FIFO Control Register */
#define UCR3_RI BIT(8) /* RIDELT DTE mode */
#define UCR3_DCD BIT(9) /* DCDDELT DTE mode */
#define UFCR 0x90 /* FIFO Control Register */
#define UFCR_DCEDTE (1<<6) /* DCE=0 */
#define UFCR_DCEDTE BIT(6) /* DCE=0 */
static void setup_dtemode_uart(void)
{
@ -247,6 +250,11 @@ static void setup_dtemode_uart(void)
setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
setbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
setbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI);
clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI);
clrbits_le32((u32 *)(UART4_BASE + UCR3), UCR3_DCD | UCR3_RI);
clrbits_le32((u32 *)(UART5_BASE + UCR3), UCR3_DCD | UCR3_RI);
}
static void setup_dcemode_uart(void)
{