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net: phy: dp83867: Clean force link good bit

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On Xilinx ZynqMP revA board initial value of PHYCR register is 0x5448 which
means FORCE_LINK_GOOD is already setup. Origin code was doing write but the
new code is doing read/modify/write and keep this bit untouched. That's why
ethernet stop to work.
The patch is cleaning this bit when PHYCR value is composed.

Tested on Xilinx zcu102-revA and zcu104-rev1.0 boards.

Fixes: 37d6265f2b ("net: phy: dp83867: refactor rgmii configuration")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
This commit is contained in:
Michal Simek 2020-02-06 15:59:23 +01:00
parent 4c2c28a465
commit 380376520f
1 changed files with 4 additions and 0 deletions
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4
drivers/net/phy/dp83867.c
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@ -65,6 +65,7 @@
#define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14
#define DP83867_PHYCR_FIFO_DEPTH_MASK GENMASK(15, 14)
#define DP83867_PHYCR_RESERVED_MASK BIT(11)
#define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10)
#define DP83867_MDI_CROSSOVER 5
#define DP83867_MDI_CROSSOVER_MDIX 2
#define DP83867_PHYCTRL_SGMIIEN 0x0800
@ -284,6 +285,9 @@ static int dp83867_config(struct phy_device *phydev)
val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
/* Do not force link good */
val &= ~DP83867_PHYCR_FORCE_LINK_GOOD;
/* The code below checks if "port mirroring" N/A MODE4 has been
* enabled during power on bootstrap.
*