Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx

Makefile

@@ -2403,20 +2403,7 @@ MVBLM7_config: unconfig
 sbc8349_config \
 sbc8349_PCI_33_config \
 sbc8349_PCI_66_config: unconfig
-	@mkdir -p $(obj)include
+	@$(MKCONFIG) -t $(@:_config=) sbc8349 ppc mpc83xx sbc8349
-	@if [ "$(findstring _PCI_,$@)" ] ; then \
-		$(XECHO) -n "... PCI HOST at " ; \
-		echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \
-	fi ; \
-	if [ "$(findstring _33_,$@)" ] ; then \
-		$(XECHO) -n "33MHz... " ; \
-		echo "#define PCI_33M" >>$(obj)include/config.h ; \
-	fi ; \
-	if [ "$(findstring _66_,$@)" ] ; then \
-		$(XECHO) -n "66MHz... " ; \
-		echo "#define PCI_66M" >>$(obj)include/config.h ; \
-	fi ;
-	@$(MKCONFIG) -a sbc8349 ppc mpc83xx sbc8349
 
 SIMPC8313_LP_config \
 SIMPC8313_SP_config: unconfig

board/freescale/mpc8360emds/mpc8360emds.c

@@ -21,12 +21,16 @@
 #endif
 #include <spd_sdram.h>
 #include <asm/mmu.h>
+#include <asm/io.h>
 #if defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
 #endif
+#include <hwconfig.h>
+#include <fdt_support.h>
 #if defined(CONFIG_PQ_MDS_PIB)
 #include "../common/pq-mds-pib.h"
 #endif
+#include "../../../drivers/qe/uec.h"
 
 const qe_iop_conf_t qe_iop_conf_tab[] = {
 	/* GETH1 */
@@ -89,11 +93,19 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
 	{0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
 };
 
+/* Handle "mpc8360ea rev.2.1 erratum 2: RGMII Timing"? */
+static int board_handle_erratum2(void)
+{
+	const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+
+	return REVID_MAJOR(immr->sysconf.spridr) == 2 &&
+	       REVID_MINOR(immr->sysconf.spridr) == 1;
+}
+
 int board_early_init_f(void)
 {
-
-	u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
 	const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+	u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
 
 	/* Enable flash write */
 	bcsr[0xa] &= ~0x04;
@@ -105,6 +117,21 @@ int board_early_init_f(void)
 	/* Enable second UART */
 	bcsr[0x9] &= ~0x01;
 
+	if (board_handle_erratum2()) {
+		void *immap = (immap_t *)(CONFIG_SYS_IMMR + 0x14a8);
+
+		/*
+		 * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
+		 * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
+		 */
+		setbits_be32(immap, 0x0c003000);
+
+		/*
+		 * IMMR + 0x14AC[20:27] = 10101010
+		 * (data delay for both UCC's)
+		 */
+		clrsetbits_be32(immap + 4, 0xff0, 0xaa0);
+	}
 	return 0;
 }
 
@@ -116,6 +143,28 @@ int board_early_init_r(void)
 	return 0;
 }
 
+#ifdef CONFIG_UEC_ETH
+static uec_info_t uec_info[] = {
+#ifdef CONFIG_UEC_ETH1
+	STD_UEC_INFO(1),
+#endif
+#ifdef CONFIG_UEC_ETH2
+	STD_UEC_INFO(2),
+#endif
+};
+
+int board_eth_init(bd_t *bd)
+{
+	if (board_handle_erratum2()) {
+		int i;
+
+		for (i = 0; i < ARRAY_SIZE(uec_info); i++)
+			uec_info[i].enet_interface = ENET_1000_RGMII_RXID;
+	}
+	return uec_eth_init(bd, uec_info, ARRAY_SIZE(uec_info));
+}
+#endif /* CONFIG_UEC_ETH */
+
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
@@ -126,6 +175,7 @@ phys_size_t initdram(int board_type)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 msize = 0;
+	u32 lbc_sdram_size;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
 		return -1;
@@ -147,7 +197,9 @@ phys_size_t initdram(int board_type)
 	/*
 	 * Initialize SDRAM if it is on local bus.
 	 */
-	msize += sdram_init(msize * 1024 * 1024);
+	lbc_sdram_size = sdram_init(msize * 1024 * 1024);
+	if (!msize)
+		msize = lbc_sdram_size;
 
 	/* return total bus SDRAM size(bytes)  -- DDR */
 	return (msize * 1024 * 1024);
@@ -307,21 +359,28 @@ static int sdram_init(unsigned int base) { return 0; }
 #endif
 
 #if defined(CONFIG_OF_BOARD_SETUP)
+static void ft_board_fixup_qe_usb(void *blob, bd_t *bd)
+{
+	if (!hwconfig_subarg_cmp("qe_usb", "mode", "peripheral"))
+		return;
+
+	do_fixup_by_compat(blob, "fsl,mpc8323-qe-usb", "mode",
+			   "peripheral", sizeof("peripheral"), 1);
+}
+
 void ft_board_setup(void *blob, bd_t *bd)
 {
-	const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-
 	ft_cpu_setup(blob, bd);
 #ifdef CONFIG_PCI
 	ft_pci_setup(blob, bd);
 #endif
+	ft_board_fixup_qe_usb(blob, bd);
 	/*
 	 * mpc8360ea pb mds errata 2: RGMII timing
 	 * if on mpc8360ea rev. 2.1,
 	 * change both ucc phy-connection-types from rgmii-id to rgmii-rxid
 	 */
-	if ((REVID_MAJOR(immr->sysconf.spridr) == 2) &&
+	if (board_handle_erratum2()) {
-	    (REVID_MINOR(immr->sysconf.spridr) == 1)) {
 		int nodeoffset;
 		const char *prop;
 		int path;

cpu/mpc83xx/cpu_init.c

@@ -23,8 +23,8 @@
 #include <common.h>
 #include <mpc83xx.h>
 #include <ioports.h>
-#ifdef CONFIG_USB_EHCI_FSL
 #include <asm/io.h>
+#ifdef CONFIG_USB_EHCI_FSL
 #include <usb/ehci-fsl.h>
 #endif
 
@@ -63,6 +63,115 @@ static void config_qe_ioports(void)
  */
 void cpu_init_f (volatile immap_t * im)
 {
+	__be32 acr_mask =
+#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
+		(ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
+		(ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
+#endif
+		0;
+	__be32 acr_val =
+#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
+		(CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
+		(CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
+#endif
+		0;
+	__be32 spcr_mask =
+#ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */
+		(SPCR_OPT << SPCR_OPT_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
+		(SPCR_TSECEP << SPCR_TSECEP_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
+		(SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
+		(SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) |
+#endif
+		0;
+	__be32 spcr_val =
+#ifdef CONFIG_SYS_SPCR_OPT
+		(CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
+		(CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
+		(CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
+		(CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) |
+#endif
+		0;
+	__be32 sccr_mask =
+#ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
+		(SCCR_ENCCM << SCCR_ENCCM_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
+		(SCCR_PCICM << SCCR_PCICM_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
+		(SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
+		(SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
+		(SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
+		(SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
+		(SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
+		(SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
+		(SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
+		(SCCR_SATACM << SCCR_SATACM_SHIFT) |
+#endif
+		0;
+	__be32 sccr_val =
+#ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
+		(CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
+		(CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
+		(CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
+		(CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
+		(CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
+		(CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
+		(CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
+		(CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
+		(CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
+		(CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
+#endif
+		0;
+
 	/* Pointer is writable since we allocated a register for it */
 	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
 
@@ -70,142 +179,47 @@ void cpu_init_f (volatile immap_t * im)
 	memset ((void *) gd, 0, sizeof (gd_t));
 
 	/* system performance tweaking */
+	clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val);
 
-#ifdef CONFIG_SYS_ACR_PIPE_DEP
+	clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val);
-	/* Arbiter pipeline depth */
-	im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
-			  (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
-#endif
 
-#ifdef CONFIG_SYS_ACR_RPTCNT
+	clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val);
-	/* Arbiter repeat count */
-	im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) |
-			  (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT);
-#endif
-
-#ifdef CONFIG_SYS_SPCR_OPT
-	/* Optimize transactions between CSB and other devices */
-	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) |
-			   (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT);
-#endif
-
-#ifdef CONFIG_SYS_SPCR_TSECEP
-	/* all eTSEC's Emergency priority */
-	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSECEP) |
-			   (CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT);
-#endif
-
-#ifdef CONFIG_SYS_SPCR_TSEC1EP
-	/* TSEC1 Emergency priority */
-	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) |
-			   (CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT);
-#endif
-
-#ifdef CONFIG_SYS_SPCR_TSEC2EP
-	/* TSEC2 Emergency priority */
-	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) |
-			   (CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT);
-#endif
-
-#ifdef CONFIG_SYS_SCCR_ENCCM
-	/* Encryption clock mode */
-	im->clk.sccr = (im->clk.sccr & ~SCCR_ENCCM) |
-		       (CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT);
-#endif
-
-#ifdef CONFIG_SYS_SCCR_PCICM
-	/* PCI & DMA clock mode */
-	im->clk.sccr = (im->clk.sccr & ~SCCR_PCICM) |
-		       (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT);
-#endif
-
-#ifdef CONFIG_SYS_SCCR_TSECCM
-	/* all TSEC's clock mode */
-	im->clk.sccr = (im->clk.sccr & ~SCCR_TSECCM) |
-		       (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT);
-#endif
-
-#ifdef CONFIG_SYS_SCCR_TSEC1CM
-	/* TSEC1 clock mode */
-	im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) |
-		       (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT);
-#endif
-
-#ifdef CONFIG_SYS_SCCR_TSEC2CM
-	/* TSEC2 clock mode */
-	im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) |
-		       (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT);
-#endif
-
-#ifdef CONFIG_SYS_SCCR_TSEC1ON
-	/* TSEC1 clock switch */
-	im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1ON) |
-		       (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT);
-#endif
-
-#ifdef CONFIG_SYS_SCCR_TSEC2ON
-	/* TSEC2 clock switch */
-	im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2ON) |
-		       (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT);
-#endif
-
-#ifdef CONFIG_SYS_SCCR_USBMPHCM
-	/* USB MPH clock mode */
-	im->clk.sccr = (im->clk.sccr & ~SCCR_USBMPHCM) |
-		       (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT);
-#endif
-
-#ifdef CONFIG_SYS_SCCR_USBDRCM
-	/* USB DR clock mode */
-	im->clk.sccr = (im->clk.sccr & ~SCCR_USBDRCM) |
-		       (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT);
-#endif
-
-#ifdef CONFIG_SYS_SCCR_SATACM
-	/* SATA controller clock mode */
-	im->clk.sccr = (im->clk.sccr & ~SCCR_SATACM) |
-		       (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT);
-#endif
 
 	/* RSR - Reset Status Register - clear all status (4.6.1.3) */
-	gd->reset_status = im->reset.rsr;
+	gd->reset_status = __raw_readl(&im->reset.rsr);
-	im->reset.rsr = ~(RSR_RES);
+	__raw_writel(~(RSR_RES), &im->reset.rsr);
 
 	/* AER - Arbiter Event Register - store status */
-	gd->arbiter_event_attributes = im->arbiter.aeatr;
+	gd->arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
-	gd->arbiter_event_address = im->arbiter.aeadr;
+	gd->arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
 
 	/*
 	 * RMR - Reset Mode Register
 	 * contains checkstop reset enable (4.6.1.4)
 	 */
-	im->reset.rmr = (RMR_CSRE & (1<<RMR_CSRE_SHIFT));
+	__raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr);
 
-	/* LCRR - Clock Ratio Register (10.3.1.16) */
+	/* Enable Time Base & Decrementer ( so we will have udelay() )*/
-	im->lbus.lcrr = CONFIG_SYS_LCRR;
+	setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
-
-	/* Enable Time Base & Decrimenter ( so we will have udelay() )*/
-	im->sysconf.spcr |= SPCR_TBEN;
 
 	/* System General Purpose Register */
 #ifdef CONFIG_SYS_SICRH
 #if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8313)
 	/* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
-	im->sysconf.sicrh = (im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH;
+	__raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH,
+		     &im->sysconf.sicrh);
 #else
-	im->sysconf.sicrh = CONFIG_SYS_SICRH;
+	__raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh);
 #endif
 #endif
 #ifdef CONFIG_SYS_SICRL
-	im->sysconf.sicrl = CONFIG_SYS_SICRL;
+	__raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl);
 #endif
-	/* DDR control driver register */
+#ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */
-#ifdef CONFIG_SYS_DDRCDR
+	__raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr);
-	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR;
 #endif
-	/* Output buffer impedance register */
+#ifdef CONFIG_SYS_OBIR /* Output buffer impedance register */
-#ifdef CONFIG_SYS_OBIR
+	__raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir);
-	im->sysconf.obir = CONFIG_SYS_OBIR;
 #endif
 
 #ifdef CONFIG_QE
@@ -308,7 +322,7 @@ void cpu_init_f (volatile immap_t * im)
 
 	/* Wait for clock to stabilize */
 	do {
-		temp = in_be32(&ehci->control);
+		temp = __raw_readl(&ehci->control);
 		udelay(1000);
 	} while (!(temp & PHY_CLK_VALID));
 #endif
@@ -317,8 +331,41 @@ void cpu_init_f (volatile immap_t * im)
 
 int cpu_init_r (void)
 {
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
 #ifdef CONFIG_QE
 	uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */
+#endif
+	__be32 lcrr_mask =
+#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
+		LCRR_DBYP |
+#endif
+#ifdef CONFIG_SYS_LCRR_EADC /* external address delay */
+		LCRR_EADC |
+#endif
+#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
+		LCRR_CLKDIV |
+#endif
+		0;
+	__be32 lcrr_val =
+#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
+		CONFIG_SYS_LCRR_DBYP |
+#endif
+#ifdef CONFIG_SYS_LCRR_EADC
+		CONFIG_SYS_LCRR_EADC |
+#endif
+#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
+		CONFIG_SYS_LCRR_CLKDIV |
+#endif
+		0;
+
+	/* LCRR - Clock Ratio Register (10.3.1.16)
+	 * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
+	 */
+	clrsetbits_be32(&im->lbus.lcrr, lcrr_mask, lcrr_val);
+	__raw_readl(&im->lbus.lcrr);
+	isync();
+
+#ifdef CONFIG_QE
 	qe_init(qe_base);
 	qe_reset();
 #endif

drivers/qe/uccf.h

@@ -25,6 +25,7 @@
 
 #include "common.h"
 #include "qe.h"
+#include "asm/immap_qe.h"
 
 /* Fast or Giga ethernet
 */

drivers/qe/uec.h

@@ -23,6 +23,9 @@
 #ifndef __UEC_H__
 #define __UEC_H__
 
+#include "qe.h"
+#include "uccf.h"
+
 #define MAX_TX_THREADS				8
 #define MAX_RX_THREADS				8
 #define MAX_TX_QUEUES				8
@@ -670,6 +673,7 @@ typedef enum enet_interface {
 	ENET_1000_RGMII,
 	ENET_1000_RGMII_ID,
 	ENET_1000_RGMII_RXID,
+	ENET_1000_RGMII_TXID,
 	ENET_1000_TBI,
 	ENET_1000_RTBI,
 	ENET_1000_SGMII

drivers/qe/uec_phy.c

@@ -429,12 +429,23 @@ static int marvell_init(struct uec_mii_info *mii_info)
 {
 	struct eth_device *edev = mii_info->dev;
 	uec_private_t *uec = edev->priv;
+	enum enet_interface iface = uec->uec_info->enet_interface;
 
-	if (uec->uec_info->enet_interface == ENET_1000_RGMII_ID) {
+	if (iface == ENET_1000_RGMII_ID ||
+			iface == ENET_1000_RGMII_RXID ||
+			iface == ENET_1000_RGMII_TXID) {
 		int temp;
 
 		temp = phy_read(mii_info, MII_M1111_PHY_EXT_CR);
-		temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
+		if (iface == ENET_1000_RGMII_ID) {
+			temp |= MII_M1111_RX_DELAY | MII_M1111_TX_DELAY;
+		} else if (iface == ENET_1000_RGMII_RXID) {
+			temp &= ~MII_M1111_TX_DELAY;
+			temp |= MII_M1111_RX_DELAY;
+		} else if (iface == ENET_1000_RGMII_TXID) {
+			temp &= ~MII_M1111_RX_DELAY;
+			temp |= MII_M1111_TX_DELAY;
+		}
 		phy_write(mii_info, MII_M1111_PHY_EXT_CR, temp);
 
 		temp = phy_read(mii_info, MII_M1111_PHY_EXT_SR);

include/configs/MPC8313ERDB.h

@@ -216,7 +216,8 @@
 /*
  * Local Bus LCRR and LBCR regs
  */
-#define CONFIG_SYS_LCRR	LCRR_EADC_1 | LCRR_CLKDIV_4
+#define CONFIG_SYS_LCRR_EADC	LCRR_EADC_1
+#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
 #define CONFIG_SYS_LBC_LBCR	( 0x00040000 /* TODO */ \
 			| (0xFF << LBCR_BMT_SHIFT) \
 			| 0xF )	/* 0x0004ff0f */

include/configs/MPC8315ERDB.h

@@ -182,7 +182,8 @@
 /*
  * Local Bus Configuration & Clock Setup
  */
-#define CONFIG_SYS_LCRR		(LCRR_DBYP | LCRR_CLKDIV_2)
+#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
 #define CONFIG_SYS_LBC_LBCR		0x00040000
 
 /*

include/configs/MPC8323ERDB.h

@@ -170,7 +170,8 @@
 /*
  * Local Bus Configuration & Clock Setup
  */
-#define CONFIG_SYS_LCRR		(LCRR_DBYP | LCRR_CLKDIV_2)
+#define CONFIG_SYS_LCRR_DBYP		LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
 #define CONFIG_SYS_LBC_LBCR		0x00000000
 
 /*

include/configs/MPC832XEMDS.h

@@ -159,7 +159,8 @@
 /*
  * Local Bus Configuration & Clock Setup
  */
-#define CONFIG_SYS_LCRR		(LCRR_DBYP | LCRR_CLKDIV_2)
+#define CONFIG_SYS_LCRR_DBYP		LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
 #define CONFIG_SYS_LBC_LBCR		0x00000000
 
 /*

include/configs/MPC8349EMDS.h

@@ -206,7 +206,8 @@
  * External Local Bus rate is
  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  */
-#define CONFIG_SYS_LCRR	(LCRR_DBYP | LCRR_CLKDIV_4)
+#define CONFIG_SYS_LCRR_DBYP		LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_4
 #define CONFIG_SYS_LBC_LBCR	0x00000000
 
 /*

include/configs/MPC8349ITX.h

@@ -317,7 +317,8 @@ boards, we say we have two, but don't display a message if we find only one. */
  * External Local Bus rate is
  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  */
-#define CONFIG_SYS_LCRR	(LCRR_DBYP | LCRR_CLKDIV_4)
+#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
 #define CONFIG_SYS_LBC_LBCR	0x00000000
 
 #define CONFIG_SYS_LBC_LSRT	0x32000000    /* LB sdram refresh timer, about 6us */

include/configs/MPC8360EMDS.h

@@ -185,7 +185,8 @@
 /*
  * Local Bus Configuration & Clock Setup
  */
-#define CONFIG_SYS_LCRR		(LCRR_DBYP | LCRR_CLKDIV_4)
+#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
 #define CONFIG_SYS_LBC_LBCR		0x00000000
 
 /*
@@ -382,6 +383,8 @@
 #define CONFIG_NET_MULTI	1
 #endif
 
+#define CONFIG_HWCONFIG		1
+
 /*
  * QE UEC ethernet configuration
  */
@@ -397,7 +400,7 @@
 #define CONFIG_SYS_UEC1_TX_CLK		QE_CLK9
 #define CONFIG_SYS_UEC1_ETH_TYPE	GIGA_ETH
 #define CONFIG_SYS_UEC1_PHY_ADDR	0
-#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_GMII
+#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID
 #endif
 
 #define CONFIG_UEC_ETH2		/* GETH2 */
@@ -408,7 +411,7 @@
 #define CONFIG_SYS_UEC2_TX_CLK		QE_CLK4
 #define CONFIG_SYS_UEC2_ETH_TYPE	GIGA_ETH
 #define CONFIG_SYS_UEC2_PHY_ADDR	1
-#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_GMII
+#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID
 #endif
 
 /*

include/configs/MPC8360ERDK.h

@@ -177,7 +177,8 @@
 /*
  * Local Bus Configuration & Clock Setup
  */
-#define CONFIG_SYS_LCRR		(LCRR_DBYP | LCRR_CLKDIV_4)
+#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
 #define CONFIG_SYS_LBC_LBCR		0x00000000
 
 /*

include/configs/MPC837XEMDS.h

@@ -220,7 +220,8 @@
 /*
  * Local Bus Configuration & Clock Setup
  */
-#define CONFIG_SYS_LCRR		(LCRR_DBYP | LCRR_CLKDIV_8)
+#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_8
 #define CONFIG_SYS_LBC_LBCR		0x00000000
 
 /*

include/configs/MPC837XERDB.h

@@ -243,7 +243,8 @@
 /*
  * Local Bus Configuration & Clock Setup
  */
-#define CONFIG_SYS_LCRR		(LCRR_DBYP | LCRR_CLKDIV_8)
+#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_8
 #define CONFIG_SYS_LBC_LBCR		0x00000000
 
 /*

include/configs/MVBLM7.h

@@ -137,7 +137,8 @@
  * External Local Bus rate is
  *  CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  */
-#define CONFIG_SYS_LCRR	(LCRR_DBYP | LCRR_CLKDIV_4)
+#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
 #define CONFIG_SYS_LBC_LBCR	0x00000000
 
 /* LB sdram refresh timer, about 6us */

include/configs/SIMPC8313.h

@@ -111,7 +111,9 @@
 /*
  * Local Bus LCRR and LBCR regs
  */
-#define CONFIG_SYS_LCRR		(LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2)
+#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
+#define CONFIG_SYS_LCRR_EADC	LCRR_EADC_1
+#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_2
 #define CONFIG_SYS_LBC_LBCR	(0x00040000 /* TODO */ \
 				| (0xFF << LBCR_BMT_SHIFT) \
 				| 0xF )	/* 0x0004ff0f */

include/configs/TQM834x.h

@@ -52,7 +52,8 @@
  * External Local Bus rate is
  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  */
-#define CONFIG_SYS_LCRR		(LCRR_DBYP | LCRR_CLKDIV_8)
+#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_8
 
 /* board pre init: do not call, nothing to do */
 #undef CONFIG_BOARD_EARLY_INIT_F

include/configs/kmeter1.h

@@ -170,7 +170,9 @@
 /*
  * Local Bus Configuration & Clock Setup
  */
-#define CONFIG_SYS_LCRR		(LCRR_DBYP | LCRR_EADC_2 | LCRR_CLKDIV_4)
+#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
+#define CONFIG_SYS_LCRR_EADC	LCRR_EADC_2
+#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
 
 /*
  * Init Local Bus Memory Controller:

include/configs/sbc8349.h

@@ -31,6 +31,21 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+/*
+ * Top level Makefile configuration choices
+ */
+#ifdef CONFIG_MK_PCI
+#define CONFIG_PCI
+#endif
+
+#ifdef CONFIG_MK_66
+#define PCI_66M
+#endif
+
+#ifdef CONFIG_MK_33
+#define PCI_33M
+#endif
+
 /*
  * High Level Configuration Options
  */
@@ -182,7 +197,8 @@
  * External Local Bus rate is
  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  */
-#define CONFIG_SYS_LCRR	(LCRR_DBYP | LCRR_CLKDIV_4)
+#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
 #define CONFIG_SYS_LBC_LBCR	0x00000000
 
 #undef CONFIG_SYS_LB_SDRAM	/* if board has SDRAM on local bus */

include/configs/vme8349.h

@@ -178,7 +178,8 @@
  * External Local Bus rate is
  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  */
-#define CONFIG_SYS_LCRR		(LCRR_DBYP | LCRR_CLKDIV_4)
+#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
 #define CONFIG_SYS_LBC_LBCR	0x00000000
 
 #undef CONFIG_SYS_LB_SDRAM	/* if board has SDRAM on local bus */