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powerpc/corenet2: fix mismatch DDR sync bit from RCW
Corenet 2nd generation Chassis doesn't have ddr_sync bit in RCW. Only async mode is supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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@ -60,7 +60,8 @@ int checkcpu (void)
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uint major, minor;
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uint major, minor;
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struct cpu_type *cpu;
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struct cpu_type *cpu;
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char buf1[32], buf2[32];
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char buf1[32], buf2[32];
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#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
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#if defined(CONFIG_DDR_CLK_FREQ) || \
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(defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2))
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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#endif /* CONFIG_FSL_CORENET */
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#endif /* CONFIG_FSL_CORENET */
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#ifdef CONFIG_DDR_CLK_FREQ
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#ifdef CONFIG_DDR_CLK_FREQ
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@ -68,8 +69,13 @@ int checkcpu (void)
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>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
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>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
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#else
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#else
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#ifdef CONFIG_FSL_CORENET
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#ifdef CONFIG_FSL_CORENET
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u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
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u32 ddr_sync ;
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#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
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ddr_sync = 0; /* only async mode is supported */
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#else
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ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
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>> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
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>> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
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#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
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#else
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#else
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u32 ddr_ratio = 0;
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u32 ddr_ratio = 0;
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#endif /* CONFIG_FSL_CORENET */
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#endif /* CONFIG_FSL_CORENET */
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