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arm64: dts: imx8mm-beacon: Resync imx8mm-beacon-som with 5.11-rc4

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In order to support the QSPI chip on the SOM, the Flexspi bus
needs to be configured to talk with the SPI chip.
Resync the som device tree with 5.11-rc4

Signed-off-by: Adam Ford <aford173@gmail.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Adam Ford 2021-01-18 15:43:09 -06:00 committed by Stefano Babic
parent 415bb8654d
commit 3796ab8fac
1 changed files with 187 additions and 139 deletions
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52
arch/arm/dts/imx8mm-beacon-som.dtsi
View File

@ -4,6 +4,11 @@
*/
/ {
aliases {
rtc0 = &rtc;
rtc1 = &snvs_rtc;
};
usdhc1_pwrseq: usdhc1_pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
@ -24,6 +29,18 @@
cpu-supply = <&buck2_reg>;
};
&A53_1 {
cpu-supply = <&buck2_reg>;
};
&A53_2 {
cpu-supply = <&buck2_reg>;
};
&A53_3 {
cpu-supply = <&buck2_reg>;
};
&ddrc {
operating-points-v2 = <&ddrc_opp_table>;
@ -63,6 +80,22 @@
};
};
&flexspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi>;
status = "okay";
flash@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <80000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
@ -78,6 +111,10 @@
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
rohm,reset-snvs-powered;
#clock-cells = <0>;
clocks = <&osc_32k 0>;
clock-output-names = "clk-32k-out";
regulators {
buck1_reg: BUCK1 {
regulator-name = "buck1";
@ -191,7 +228,7 @@
reg = <0x50>;
};
rtc@51 {
rtc: rtc@51 {
compatible = "nxp,pcf85263";
reg = <0x51>;
};
@ -292,6 +329,17 @@
>;
};
pinctrl_flexspi: flexspigrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
>;
};
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
@ -400,7 +448,7 @@
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
>;
};