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Fix PCI-Express on PPC440SPe rev. A.

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This commit is contained in:
Rafal Jaworowski 2006-08-11 12:35:52 +02:00 committed by Rafal Jaworowski
parent 692519b1ed
commit 36b904a7fd
5 changed files with 25 additions and 36 deletions
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2
CHANGELOG
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@ -2,6 +2,8 @@
Changes since U-Boot 1.1.4: Changes since U-Boot 1.1.4:
====================================================================== ======================================================================
* Fix PCI-Express on PPC440SPe rev. A.
* Add initial support for PCI-Express on PPC440SPe (Yucca board). * Add initial support for PCI-Express on PPC440SPe (Yucca board).
* Fix timer problems on AMCC yucca board. * Fix timer problems on AMCC yucca board.

21
board/amcc/yucca/init.S
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@ -105,17 +105,14 @@ tlbtabA:
tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_XCFGBASE, SZ_4K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_XCFGBASE, SZ_4K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_XCFGBASE, SZ_4K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_REGBASE, SZ_1K, 0x60000400, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE3_REGBASE, SZ_1K, 0x60001400, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE5_REGBASE, SZ_1K, 0x60002400, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbtab_end tlbtab_end
/************************************************************************** /**************************************************************************
@ -152,8 +149,4 @@ tlbtabB:
tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_REGBASE, SZ_1K, 0x60000400, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE3_REGBASE, SZ_1K, 0x60001400, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE5_REGBASE, SZ_1K, 0x60002400, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbtab_end tlbtab_end

1
board/amcc/yucca/yucca.c
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@ -1032,6 +1032,7 @@ void pcie_setup_hoses(void)
continue; continue;
yucca_setup_pcie_fpga_rootpoint(i); yucca_setup_pcie_fpga_rootpoint(i);
if (ppc440spe_init_pcie_rootport(i)) { if (ppc440spe_init_pcie_rootport(i)) {
printf("PCIE%d: initialization failed\n", i); printf("PCIE%d: initialization failed\n", i);
continue; continue;

25
cpu/ppc4xx/440spe_pcie.c
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@ -148,29 +148,27 @@ static void ppc440spe_setup_utl(u32 port) {
*/ */
switch (port) { switch (port) {
case 0: case 0:
mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000d); mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c);
mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x60000400); mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x20000000);
mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0xFFFFFC01); mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001);
mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800); mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800);
utl_base = (unsigned int *)(CFG_PCIE1_REGBASE);
break; break;
case 1: case 1:
mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000d); mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c);
mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x60001400); mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x20001000);
mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0xFFFFFC01); mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001);
mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800); mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800);
utl_base = (unsigned int *)(CFG_PCIE3_REGBASE);
break; break;
case 2: case 2:
mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000d); mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c);
mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x60002400); mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x20002000);
mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0xFFFFFC01); mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001);
mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800); mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800);
utl_base = (unsigned int *)(CFG_PCIE5_REGBASE);
break; break;
} }
utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port);
/* /*
* Set buffer allocations and then assert VRB and TXE. * Set buffer allocations and then assert VRB and TXE.
@ -182,7 +180,7 @@ static void ppc440spe_setup_utl(u32 port) {
out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000); out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000);
out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000); out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000);
out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000); out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
out_be32(utl_base + PEUTL_PCTL, 0x8080007d); out_be32(utl_base + PEUTL_PCTL, 0x80800066);
} }
static int check_error(void) static int check_error(void)
@ -420,6 +418,7 @@ int ppc440spe_init_pcie_rootport(int port)
* PCIE1: 0xd_2000_0000 * PCIE1: 0xd_2000_0000
* PCIE2: 0xd_4000_0000 * PCIE2: 0xd_4000_0000
*/ */
switch (port) { switch (port) {
case 0: case 0:
if (ppc440spe_revB()) { if (ppc440spe_revB()) {

10
include/configs/yucca.h
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@ -67,8 +67,9 @@
#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ #define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
#define CFG_PCI_TARGBASE CFG_PCI_MEMBASE #define CFG_PCI_TARGBASE CFG_PCI_MEMBASE
#define CFG_PCIE_MEMBASE 0xB0000000 /* mapped PCIe memory */ #define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
#define CFG_PCIE_MEMSIZE 0x01000000 #define CFG_PCIE_MEMSIZE 0x01000000
#define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
#define CFG_PCIE0_CFGBASE 0xc0000000 #define CFG_PCIE0_CFGBASE 0xc0000000
#define CFG_PCIE0_XCFGBASE 0xc0000400 #define CFG_PCIE0_XCFGBASE 0xc0000400
@ -77,13 +78,6 @@
#define CFG_PCIE2_CFGBASE 0xc0002000 #define CFG_PCIE2_CFGBASE 0xc0002000
#define CFG_PCIE2_XCFGBASE 0xc0002400 #define CFG_PCIE2_XCFGBASE 0xc0002400
#define CFG_PCIE0_REGBASE 0xc0003000
#define CFG_PCIE1_REGBASE 0xc0003400
#define CFG_PCIE2_REGBASE 0xc0004000
#define CFG_PCIE3_REGBASE 0xc0004400
#define CFG_PCIE4_REGBASE 0xc0005000
#define CFG_PCIE5_REGBASE 0xc0005400
/* System RAM mapped to PCI space */ /* System RAM mapped to PCI space */
#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE