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clk: stm32mp1: fix CK_MPU calculation

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When the CK_MPU used PLL1_MPUDIV, the current rate is
wrong. The clock must use stm32mp1_mpu_div as a shift
value. Fix the check value used to enter PLL_MPUDIV.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
This commit is contained in:
Lionel Debieve 2020-04-24 15:47:57 +02:00 committed by Patrick Delaunay
parent d7244e4a1f
commit 36911fca63
1 changed files with 4 additions and 3 deletions
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7
drivers/clk/clk_stm32mp1.c
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@ -954,10 +954,11 @@ static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
case RCC_MPCKSELR_PLL:
case RCC_MPCKSELR_PLL_MPUDIV:
clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
if (p == RCC_MPCKSELR_PLL_MPUDIV) {
if ((reg & RCC_SELR_SRC_MASK) ==
RCC_MPCKSELR_PLL_MPUDIV) {
reg = readl(priv->base + RCC_MPCKDIVR);
clock /= stm32mp1_mpu_div[reg &
RCC_MPUDIV_MASK];
clock >>= stm32mp1_mpu_div[reg &
RCC_MPUDIV_MASK];
}
break;
}