ARM: dts: rmobile: Factor out U-Boot extras

Pull out u-boot extras into dtsi files to make synchronization of DTS
from Linux kernel as easy as a simple copy. All the U-Boot extras are
now in *-u-boot.dts* files instead.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Marek Vasut 2018-01-10 11:47:03 +01:00 committed by Marek Vasut
parent 62b2bb5374
commit 34df58a95e
21 changed files with 139 additions and 25 deletions

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@ -0,0 +1,10 @@
/*
* Device Tree Source extras for U-Boot for the ULCB board
*
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0
*/
#include "r8a7795-h3ulcb.dts"
#include "r8a7795-u-boot.dtsi"

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@ -0,0 +1,10 @@
/*
* Device Tree Source extras for U-Boot for the Salvator-X board
*
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0
*/
#include "r8a7795-salvator-x.dts"
#include "r8a7795-u-boot.dtsi"

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@ -0,0 +1,13 @@
/*
* Device Tree Source extras for U-Boot on RCar R8A7795 SoC
*
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0
*/
#include "r8a779x-u-boot.dtsi"
&extalr_clk {
u-boot,dm-pre-reloc;
};

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@ -129,7 +129,6 @@
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
u-boot,dm-pre-reloc;
};
extalr_clk: extalr {
@ -137,7 +136,6 @@
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
u-boot,dm-pre-reloc;
};
/*
@ -191,7 +189,6 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
u-boot,dm-pre-reloc;
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
@ -383,7 +380,6 @@
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
u-boot,dm-pre-reloc;
};
rst: reset-controller@e6160000 {
@ -394,7 +390,6 @@
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
u-boot,dm-pre-reloc;
};
sysc: system-controller@e6180000 {

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@ -0,0 +1,10 @@
/*
* Device Tree Source extras for U-Boot for the ULCB board
*
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0
*/
#include "r8a7796-m3ulcb.dts"
#include "r8a7796-u-boot.dtsi"

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@ -0,0 +1,10 @@
/*
* Device Tree Source extras for U-Boot for the Salvator-X board
*
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0
*/
#include "r8a7796-salvator-x.dts"
#include "r8a7796-u-boot.dtsi"

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@ -0,0 +1,13 @@
/*
* Device Tree Source extras for U-Boot on RCar R8A7796 SoC
*
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0
*/
#include "r8a779x-u-boot.dtsi"
&extalr_clk {
u-boot,dm-pre-reloc;
};

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@ -111,7 +111,6 @@
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
u-boot,dm-pre-reloc;
};
extalr_clk: extalr {
@ -119,7 +118,6 @@
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
u-boot,dm-pre-reloc;
};
/*
@ -172,7 +170,6 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
u-boot,dm-pre-reloc;
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
@ -366,7 +363,6 @@
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
u-boot,dm-pre-reloc;
};
rst: reset-controller@e6160000 {
@ -377,7 +373,6 @@
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
u-boot,dm-pre-reloc;
};
sysc: system-controller@e6180000 {

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@ -0,0 +1,10 @@
/*
* Device Tree Source extras for U-Boot for the Eagle board
*
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0
*/
#include "r8a77970-eagle.dts"
#include "r8a77970-u-boot.dtsi"

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@ -0,0 +1,13 @@
/*
* Device Tree Source extras for U-Boot on RCar R8A77970 SoC
*
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0
*/
#include "r8a779x-u-boot.dtsi"
&extalr_clk {
u-boot,dm-pre-reloc;
};

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@ -48,7 +48,6 @@
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
u-boot,dm-pre-reloc;
};
extalr_clk: extalr {
@ -56,7 +55,6 @@
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
u-boot,dm-pre-reloc;
};
/* External SCIF clock - to be overridden by boards that provide it */
@ -73,7 +71,6 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
u-boot,dm-pre-reloc;
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
@ -112,7 +109,6 @@
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
u-boot,dm-pre-reloc;
};
rst: reset-controller@e6160000 {
@ -150,7 +146,6 @@
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
u-boot,dm-pre-reloc;
};
dmac1: dma-controller@e7300000 {

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@ -0,0 +1,10 @@
/*
* Device Tree Source extras for U-Boot for the Draak board
*
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0
*/
#include "r8a77995-draak.dts"
#include "r8a77995-u-boot.dtsi"

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@ -0,0 +1,9 @@
/*
* Device Tree Source extras for U-Boot on RCar R8A77995 SoC
*
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0
*/
#include "r8a779x-u-boot.dtsi"

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@ -47,7 +47,6 @@
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
u-boot,dm-pre-reloc;
};
scif_clk: scif {
@ -62,7 +61,6 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
u-boot,dm-pre-reloc;
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
@ -116,7 +114,6 @@
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
u-boot,dm-pre-reloc;
};
rst: reset-controller@e6160000 {
@ -132,7 +129,6 @@
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
u-boot,dm-pre-reloc;
};
sysc: system-controller@e6180000 {

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@ -0,0 +1,25 @@
/*
* Device Tree Source extras for U-Boot on RCar Gen3
*
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0
*/
/ {
soc {
u-boot,dm-pre-reloc;
};
};
&cpg {
u-boot,dm-pre-reloc;
};
&extal_clk {
u-boot,dm-pre-reloc;
};
&prr {
u-boot,dm-pre-reloc;
};

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@ -3,7 +3,7 @@ CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_SALVATOR_X=y
CONFIG_DEFAULT_DEVICE_TREE="r8a7795-salvator-x"
CONFIG_DEFAULT_DEVICE_TREE="r8a7795-salvator-x-u-boot"
CONFIG_SMBIOS_PRODUCT_NAME=""
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y

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@ -3,7 +3,7 @@ CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_ULCB=y
CONFIG_DEFAULT_DEVICE_TREE="r8a7795-h3ulcb"
CONFIG_DEFAULT_DEVICE_TREE="r8a7795-h3ulcb-u-boot"
CONFIG_SMBIOS_PRODUCT_NAME=""
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y

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@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_RCAR_GEN3=y
CONFIG_R8A7796=y
CONFIG_TARGET_SALVATOR_X=y
CONFIG_DEFAULT_DEVICE_TREE="r8a7796-salvator-x"
CONFIG_DEFAULT_DEVICE_TREE="r8a7796-salvator-x-u-boot"
CONFIG_SMBIOS_PRODUCT_NAME=""
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y

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@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_RCAR_GEN3=y
CONFIG_R8A7796=y
CONFIG_TARGET_ULCB=y
CONFIG_DEFAULT_DEVICE_TREE="r8a7796-m3ulcb"
CONFIG_DEFAULT_DEVICE_TREE="r8a7796-m3ulcb-u-boot"
CONFIG_SMBIOS_PRODUCT_NAME=""
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y

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@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_RCAR_GEN3=y
CONFIG_R8A77970=y
CONFIG_TARGET_EAGLE=y
CONFIG_DEFAULT_DEVICE_TREE="r8a77970-eagle"
CONFIG_DEFAULT_DEVICE_TREE="r8a77970-eagle-u-boot"
CONFIG_SMBIOS_PRODUCT_NAME=""
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y

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@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_RCAR_GEN3=y
CONFIG_R8A77995=y
CONFIG_TARGET_DRAAK=y
CONFIG_DEFAULT_DEVICE_TREE="r8a77995-draak"
CONFIG_DEFAULT_DEVICE_TREE="r8a77995-draak-u-boot"
CONFIG_SMBIOS_PRODUCT_NAME=""
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y