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ehci-mxc: Define host offsets
Some MXC SoCs like the i.MX35 have hosts located at unusual offsets, so prepare to the introduction of i.MX35 support by defining the ehci-mxc hosts offsets at SoC level. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
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@ -241,6 +241,7 @@ struct aips_regs {
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#define IMX_RTIC_BASE (0x53FEC000)
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#define IMX_IIM_BASE (0x53FF0000)
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#define IMX_USB_BASE (0x53FF4000)
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#define IMX_USB_PORT_OFFSET 0x200
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#define IMX_CSI_BASE (0x53FF8000)
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#define IMX_DRYICE_BASE (0x53FFC000)
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@ -895,6 +895,7 @@ struct esdc_regs {
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#define MX31_AIPS1_BASE_ADDR 0x43f00000
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#define IMX_USB_BASE (MX31_AIPS1_BASE_ADDR + 0x88000)
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#define IMX_USB_PORT_OFFSET 0x200
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/*
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* CSPI register definitions
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@ -169,7 +169,7 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
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udelay(80);
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ehci = (struct usb_ehci *)(IMX_USB_BASE +
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(0x200 * CONFIG_MXC_USB_PORT));
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IMX_USB_PORT_OFFSET * CONFIG_MXC_USB_PORT);
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*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
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*hcor = (struct ehci_hcor *)((uint32_t) *hccr +
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HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
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