brain-hackers_pepepper-mirror/u-boot-brain
1
0
Fork 0
mirror of https://github.com/brain-hackers/u-boot-brain synced 2024-07-06 03:06:16 +09:00
Code Issues Projects Releases Wiki Activity

arm: socfpga: Zap spl.h and ad-hoc related syms

Browse Source 
Switch to the common spl.h file and zap the arch/spl.h . Since the arch/spl.h
contained various ad-hoc symbols, zap those symbols as well and rework the
board configuration a little so it doesn't depend on them.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Acked-by: Pavel Machek <pavel@denx.de>
This commit is contained in:
Marek Vasut 2014-10-16 12:25:40 +02:00
parent fc520894d4
commit 34584d190d
4 changed files with 12 additions and 31 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
View File

@ -42,13 +42,4 @@ SECTIONS
. = ALIGN(4);
__bss_end = .;
} >.sdram
. = ALIGN(8);
__malloc_start = .;
. = . + CONFIG_SPL_MALLOC_SIZE;
__malloc_end = .;
. = . + CONFIG_SPL_STACK_SIZE;
. = ALIGN(8);
__stack_start = .;
}

15
arch/arm/include/asm/arch-socfpga/spl.h
View File

@ -1,15 +0,0 @@
/*
* Copyright (C) 2012 Pavel Machek <pavel@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _SOCFPGA_SPL_H_
#define _SOCFPGA_SPL_H_
/* Symbols from linker script */
extern char __malloc_start, __malloc_end, __stack_start;
#define BOOT_DEVICE_RAM 1
#endif

2
arch/arm/include/asm/spl.h
View File

@ -7,7 +7,7 @@
#ifndef _ASM_SPL_H_
#define _ASM_SPL_H_
#if defined(CONFIG_OMAP) || defined(CONFIG_SOCFPGA) \
#if defined(CONFIG_OMAP) \
|| defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5) \
|| defined(CONFIG_EXYNOS4210)
/* Platform-specific defines */

17
include/configs/socfpga_common.h
View File

@ -167,16 +167,21 @@
/*
* SPL
*
* SRAM Memory layout:
*
* 0xFFFF_0000 ...... Start of SRAM
* 0xFFFF_xxxx ...... Top of stack (grows down)
* 0xFFFF_yyyy ...... Malloc area
* 0xFFFF_zzzz ...... Global Data
* 0xFFFF_FF00 ...... End of SRAM
*/
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_RAM_DEVICE
#define CONFIG_SPL_TEXT_BASE 0xFFFF0000
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
#define CONFIG_SPL_STACK_SIZE (4 * 1024)
#define CONFIG_SPL_MALLOC_SIZE (5 * 1024) /* FIXME */
#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start))
#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start)
#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
#define CONFIG_SYS_SPL_MALLOC_START CONFIG_SYS_INIT_SP_ADDR
#define CONFIG_SYS_SPL_MALLOC_SIZE (5 * 1024)
#define CHUNKSZ_CRC32 (1 * 1024) /* FIXME: ewww */
#define CONFIG_CRC32_VERIFY